- DL manuals
- Aaeon
- Motherboard
- GENE-APL5
- User Manual
Aaeon GENE-APL5 User Manual
Summary of GENE-APL5
Page 1
Last updated: december 14, 2016 gene-apl5 3.5” subcompact board user’s manual 1 st ed.
Page 2
Preface ii 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 copyright notice this document is copyrighted, 2016. All rights are reserved. The original manufacturer reserves the right to make improvements to the products described in this manual at any time without notice. No part of this manual may be rep...
Page 3
Preface iii 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 acknowledgement all other products’ name or trademarks are properties of their respective owners. Microsoft windows is a registered trademark of microsoft corp. Intel, pentium, celeron, and xeon are registered trademarks of intel corporation cor...
Page 4
Preface iv 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 packing list before setting up your product, please make sure the following items have been shipped: item quantity gene-apl5 1 product dvd with user’s manual (in pdf) and drivers 1 if any of these items are missing or damaged, please contact your...
Page 5
Preface v 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 about this document this user’s manual contains all the essential information, such as detailed descriptions and explanations on the product’s hardware and software features (if any), its specifications, dimensions, jumper/connector settings/defin...
Page 6
Preface vi 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 safety precautions please read the following safety instructions carefully. It is advised that you keep this manual for future references 1. All cautions and warnings on the device should be noted. 2. Make sure the power source matches the power ...
Page 7
Preface vii 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 17. If any of the following situations arises, please the contact our service personnel: i. Damaged power cord or plug ii. Liquid intrusion to the device iii. Exposure to moisture iv. Device is not working as expected or in a manner as described...
Page 8
Preface viii 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 fcc statement this device complies with part 15 fcc rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interferenc...
Page 9
Preface ix 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 china rohs requirements (cn) 产品中有毒有害物质或元素名称及含量 aaeon main board/ daughter board/ backplane 部件名称 有毒有害物质或元素 铅 (pb) 汞 (hg) 镉 (cd) 六价铬 (cr(vi)) 多溴联苯 (pbb) 多溴二苯醚 (pbde) 印刷电路板 及其电子组件 ○ ○ ○ ○ ○ ○ 外部信号 连接器及线材 ○ ○ ○ ○ ○ ○ o：表示该有毒有害物质在该部件所有均质材料中的含量均在 sj/t ...
Page 10
Preface x 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 china rohs requirement (en) poisonous or hazardous substances or elements in products aaeon main board/ daughter board/ backplane component poisonous or hazardous substances or elements lead (pb) mercury (hg) cadmium (cd) hexavalent chromium (cr(v...
Page 11
Preface xi 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 table of contents chapter 1 - product specifications ........................................................................................ 1 1.1 specifications ......................................................................................
Page 12
Preface xii 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 2.5.5 external power input (cn5) ............................................................... 23 2.5.6 external +5vsb input (cn6) .............................................................. 24 2.5.7 audio i/o port (cn7) ......................
Page 13
Preface xiii 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 2.5.33 mini-card slot (half-mini) (cn33) .................................................... 48 2.5.34 msata (full-size) (cn34) ................................................................... 50 chapter 3 - ami bios setup ....................
Page 14
Preface xiv 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 4.1 product cd/dvd ................................................................................................... 84 appendix a - watchdog timer programming ................................................................... 86 a.1 watchdog...
Page 15
3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 chapter 1 chapter 1 - product specifications.
Page 16
Chapter 1 – product specifications 2 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 1.1specifications system form factor 3.5” cpu intel ® pentium® n4200 / celeron® n3350 processor soc cpu frequency up to 2.5 ghz chipset intel ® atom™ n4200/ n3350 processor soc memory type ddr3l 1867 mhz sodimm x 1 max m...
Page 17
Chapter 1 – product specifications 3 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 certification ce/fcc display vga/lcd controller intel ® pentium® n4200 / celeron® n3350 processor soc integrated video output vga/lvds/ lvds2 (co-layout with hdmi, optional) backlight inverter supply yes i/o ethernet int...
Page 18
Chapter 1 – product specifications 4 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 tpm 1 (option) touch option.
Page 19
3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 chapter 2 chapter 2 – hardware information.
Page 20
Chapter 2 – hardware information 6 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 2.1 dimensions component side a a a a a.
Page 21
Chapter 2 – hardware information 7 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 solder side.
Page 22
Chapter 2 – hardware information 8 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 2.1.1 dimensions (optional hdmi sku) component side a a a a a.
Page 23
Chapter 2 – hardware information 9 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 solder side.
Page 24
Chapter 2 – hardware information 10 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 2.2 jumpers and connectors component side.
Page 25
Chapter 2 – hardware information 11 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 solder side.
Page 26
Chapter 2 – hardware information 12 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 2.2.1 jumpers and connectors (optional hdmi sku) component side.
Page 27
Chapter 2 – hardware information 13 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 solder side.
Page 28
Chapter 2 – hardware information 14 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 2.3 block diagram.
Page 29
Chapter 2 – hardware information 15 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 2.4 list of jumpers please refer to the table below for all of the board’s jumpers that you can configure for your application label function jp1 lvds port1 backlight inverter vcc selection and operating vdd selection jp...
Page 30
Chapter 2 – hardware information 16 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 2.4.1 lvds port 1 backlight inverter vcc selection (jp1) +12v +5v (default) 2.4.2 lvds port 1 operating vdd selection (jp1) +3.3v (default) +5v 2.4.3 lvds port 1 backlight lightness control mode selection (jp2) vr mode (...
Page 31
Chapter 2 – hardware information 17 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 2.4.5 com3 pin8 function selection (jp4) +12v ring (default) +5v 2.4.6 auto power button enable/disable selection (jp5) disable/atx enable/at (default) ※ when disabled, the power button of jp6 (1-2) will be used to power...
Page 32
Chapter 2 – hardware information 18 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 2.4.8 lvds port 2 backlight inverter vcc selection (jp7) +12v +5v (default) 2.4.9 lvds port 2 operating vdd selection (jp7) +3.3v (default) +5v 2.4.10 lvds port 2 backlight lightness control mode selection (jp8) vr mode ...
Page 33
Chapter 2 – hardware information 19 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 2.4.12 clear cmos jumper (jp10) normal (default) clear cmos 1 2 3 1 2 3.
Page 34
Chapter 2 – hardware information 20 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 2.5 list of connectors please refer to the table below for all of the board’s connectors that you can configure for your application label function cn1 +5vsb output w/smbus cn2 lvds port1 inverter / backlight connector c...
Page 35
Chapter 2 – hardware information 21 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 label function cn24 lvds port2 inverter / backlight connector cn25 usb ports 0 and 1 cn26 lan (rj-45) port2 cn27 lan (rj-45) port1 cn28 com port 1 (d-sub 9) cn29 hdmi port (optional) cn30 battery cn31 vga port cn32 micro...
Page 36
Chapter 2 – hardware information 22 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 2.5.1 +5vsb output w/smbus (cn1) pin pin name signal type signal level 1 smb_data i/o +3.3v 2 gnd gnd 3 smb_clk i/o +3.3v 4 gnd gnd 5 ps_on# out +5v 6 +5vsb pwr +5v 2.5.2 lvds port 1 inverter / backlight connector (cn2) ...
Page 37
Chapter 2 – hardware information 23 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 2.5.3 +5v output for sata hdd (cn3) pin pin name signal type signal level 1 +5v pwr +5v 2 gnd gnd 2.5.4 sata port (cn4) pin pin name signal type signal level 1 gnd gnd 2 sata_tx+ diff 3 sata_tx- diff 4 gnd gnd 5 sata_rx-...
Page 38
Chapter 2 – hardware information 24 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 pin pin name signal type signal level 1 +vin pwr 9v~19v or 12v 2 gnd gnd ※ there are two types of power input, 9v~19v or 12v only, by bom change. 2.5.6 external +5vsb input (cn6) pin pin name signal type signal level 1 p...
Page 39
Chapter 2 – hardware information 25 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 pin pin name signal type signal level 6 gnd_audio gnd 7 left_out out 8 gnd_audio gnd 9 right_out out 10 +5v_audio pwr +5v 2.5.8 lvds port 1 (cn8) *lvds lcd_pwr can be set to +3.3v or +5v by jp1 pin pin name signal type s...
Page 40
Chapter 2 – hardware information 26 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 pin pin name signal type signal level 10 lvds_da0+ diff 11 lvds_da1- diff 12 lvds_da1+ diff 13 lvds_da2- diff 14 lvds_da2+ diff 15 lvds_da3- diff 16 lvds_da3+ diff 17 ddc_data i/o +3.3v 18 ddc_clk i/o +3.3v 19 lvds_db0- ...
Page 41
Chapter 2 – hardware information 27 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 rs-232 pin pin name signal type signal level 1 dcd2 in 2 dsr2 in 3 rx2 in 4 rts2 out ±5v 5 tx2 out ±5v 6 cts2 in 7 dtr2 out ±5v 8 ri2/+5v/+12v in +5v/+12v 9 gnd gnd rs-485 pin pin name signal type signal level 1 rs485_ d...
Page 42
Chapter 2 – hardware information 28 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 6 nc 7 nc 8 nc/+5v/+12v pwr +5v/+12v 9 gnd gnd rs-422 pin pin name signal type signal level 1 rs422_tx2- out ±5v 2 nc 3 rs422_tx2+ out ±5v 4 nc 5 rs422_rx2+ in 6 nc 7 rs422_rx2- in 8 nc/+5v/+12v pwr +5v/+12v 9 gnd gnd * ...
Page 43
Chapter 2 – hardware information 29 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 ※ lpt or digital i/o function can be selected by bios setting. Default is digital i/o. Lpt port pin pin name signal type signal level 1 strobe# in 2 afd# i/o 3 pd0 i/o 4 error# in 5 pd1 i/o 6 print# i/o 7 pd2 i/o 8 slin#...
Page 44
Chapter 2 – hardware information 30 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 lpt port pin pin name signal type signal level 25 slct in 26 5v pwr +5v digital i/o port pin pin name signal type signal level 1 nc 2 nc 3 dio0 i/o +5v 4 nc 5 dio1 i/o +5v 6 nc 7 dio2 i/o +5v 8 nc 9 dio3 i/o +5v 10 gnd g...
Page 45
Chapter 2 – hardware information 31 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 digital i/o port pin pin name signal type signal level 14 gnd gnd 15 dio6 i/o +5v 16 gnd gnd 17 dio7 i/o +5v 18 gnd gnd 19 nc 20 gnd gnd 21 nc 22 gnd gnd 23 nc 24 gnd gnd 25 nc 26 5v pwr +5v 2.5.11 lpc port (cn11) pin pi...
Page 46
Chapter 2 – hardware information 32 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 4 lad3 i/o +3.3v 5 +3.3v pwr +3.3v 6 lframe# in 7 lreset# out +3.3v 8 gnd gnd 9 lclk out 10 ldrq0 in 11 ldrq1 in 12 serirq i/o +3.3v 2.5.12 com port 3 (cn12) rs-232 pin pin name signal type signal level 1 dcd3 in 2 dsr3 ...
Page 47
Chapter 2 – hardware information 33 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 7 dtr3 out ±5v 8 ri3/+5v/+12v in +5v/+12v 9 gnd gnd rs-485 pin pin name signal type signal level 1 rs485_ d3- i/o ±5v 2 nc 3 rs485_d3+ i/o ±5v 4 nc 5 nc 6 nc 7 nc 8 nc/+5v/+12v pwr +5v/+12v 9 gnd gnd rs-422 pin pin name ...
Page 48
Chapter 2 – hardware information 34 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 9 gnd gnd * com3 rs-232/422/485 can be set by bios setting. Default is rs-232. * pin 8 function can be set by jp4. 2.5.13 bios debug port (cn13) pin pin name signal type signal level 1 spi_miso out 2 gnd gnd 3 spi_clk in...
Page 49
Chapter 2 – hardware information 35 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 pin pin name signal type signal level 1 dcd4 in 2 dsr4 in 3 rx4 in 4 rts4 out ±9v 5 tx4 out ±9v 6 cts4 in 7 dtr4 out ±9v 8 ri4 in 9 gnd gnd 2.5.15 ps/2 keyboard/mouse combo port (cn15) pin pin name signal type signal lev...
Page 50
Chapter 2 – hardware information 36 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 6 ms_clk i/o +5v 2.5.16 usb 2.0 port 2 (cn16) pin pin name signal type signal level 1 +5vsb pwr +5v 2 usb_d- diff 3 usb_d+ diff 4 gnd gnd 5 gnd gnd 2.5.17 usb 2.0 port 3 (cn17) pin pin name signal type signal level 1 +5v...
Page 51
Chapter 2 – hardware information 37 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 2.5.18 com port 1 (cn18) (wafer, opional) pin pin name signal type signal level 1 dcd1 in 2 dsr1 in 3 rx1 in 4 rts1 out ±9v 5 tx1 out ±9v 6 cts1 in 7 dtr1 out ±9v 8 ri1 in 9 gnd gnd 2.5.19 usb 2.0 port 4 (cn19) pin pin n...
Page 52
Chapter 2 – hardware information 38 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 2 usb_d- diff 3 usb_d+ diff 4 gnd gnd 5 gnd gnd 2.5.20 usb 2.0 port 5 (cn20) pin pin name signal type signal level 1 +5vsb pwr +5v 2 usb_d- diff 3 usb_d+ diff 4 gnd gnd 5 gnd gnd 2.5.21 lvds port 2 (cn21) +5vsb usb5_d- u...
Page 53
Chapter 2 – hardware information 39 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 *lvds2 lcd_pwr can be set to +3.3v or +5v by jp7 pin pin name signal type signal level 1 bkl_enable out 2 bkl_control out 3 lcd_pwr pwr +3.3v/+5v 4 gnd gnd 5 lvds_a_clk- diff 6 lvds_a_clk+ diff 7 lcd_pwr pwr +3.3v/+5v 8 ...
Page 54
Chapter 2 – hardware information 40 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 pin pin name signal type signal level 26 lvds_db3+ diff 27 lcd_pwr pwr +3.3v/+5v 28 gnd gnd 29 lvds_b_clk- diff 30 lvds_b_clk+ diff 2.5.22 touchscreen connector (cn22) 8-wire pin pin name signal type signal level 1 gnd g...
Page 55
Chapter 2 – hardware information 41 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 4-wire pin pin name signal type signal level 1 gnd gnd 2 top in 3 bottom in 4 left in 5 right in 6 nc 7 nc 8 nc 9 nc 5-wire pin pin name signal type signal level 1 gnd gnd 2 ul(y) in 1 9 gnd top bottom left right nc nc n...
Page 56
Chapter 2 – hardware information 42 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 3 ur(h) in 4 ll(l) in 5 lr(x) in 6 sense(s) in 7 nc 8 nc 9 nc 2.5.23 cpu fan (cn23, optional) pin pin name signal type signal level 1 gnd gnd 2 fan_power pwr +12v 3 fan_tac in 2.5.24 lvds port 2 inverter / backlight conn...
Page 57
Chapter 2 – hardware information 43 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 3 gnd gnd 4 gnd gnd 5 bkl_enable out +5v * lvds2 bkl_pwr can be set to +5v or +12v by jp7 * lvds2 bkl_control can be set by jp8 2.5.25 usb 3.0 ports 0 and 1 (cn25) pin pin name signal type signal level 1 +5vsb pwr +5v 2 ...
Page 58
Chapter 2 – hardware information 44 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 15 usb_ssrx+ diff 16 gnd gnd 17 usb_sstx− diff 18 usb_sstx+ diff 2.5.26 lan (rj-45) port 2 (cn26) pin pin name signal type signal level 1 mdi0+ diff 2 mdi0- diff 3 mdi1+ diff 4 mdi2+ diff 5 mdi2- diff 6 mdi1- diff 7 mdi3...
Page 59
Chapter 2 – hardware information 45 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 2 mdi0- diff 3 mdi1+ diff 4 mdi2+ diff 5 mdi2- diff 6 mdi1- diff 7 mdi3+ diff 8 mdi3- diff 2.5.28 com port 1 (cn28, d-sub 9) pin pin name signal type signal level 1 dcd in 2 rx in 3 tx out ±9v 4 dtr out ±9v 5 gnd gnd 6 d...
Page 60
Chapter 2 – hardware information 46 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 pin pin name signal type signal level 1 tmds_dat2+ diff 2 gnd gnd 3 tmds_dat2- diff 4 tmds_dat1+ diff 5 gnd gnd 6 tmds_dat1- diff 7 tmds_dat0+ diff 8 gnd gnd 9 tmds_dat0- diff 10 tmds_clk+ diff 11 gnd gnd 12 tmds_clk- di...
Page 61
Chapter 2 – hardware information 47 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 2.5.31 vga port (cn31) pin pin name signal type signal level 1 red out 2 green out 3 blue out 4 nc 5 gnd gnd 6 red_gnd_rtn gnd 7 green_gnd_rtn gnd 8 blue_gnd_rtn gnd 9 +5v pwr +5v 10 nc 11 nc 12 ddc_data i/o +5v 13 hsync...
Page 62
Chapter 2 – hardware information 48 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 pin pin name signal type signal level 1 uim_pwr pwr 2 uim_rst in 3 uim_clk in 4 nc 5 gnd gnd 6 uim_vpp pwr 7 uim_data i/o 8 nc 2.5.33 mini-card slot (half-mini) (cn33) pin pin name signal type signal level 1 pcie_wake# i...
Page 63
Chapter 2 – hardware information 49 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 pin pin name signal type signal level 10 uim_data i/o 11 pcie_ref_clk- diff 12 uim_clk in 13 pcie_ref_clk+ diff 14 uim_rst in 15 gnd gnd 16 uim_vpp pwr 17 nc 18 gnd gnd 19 nc 20 w_disable# out +3.3v 21 gnd gnd 22 pcie_rs...
Page 64
Chapter 2 – hardware information 50 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 pin pin name signal type signal level 36 usb_d- diff 37 gnd gnd 38 usb_d+ diff 39 +3.3vsb pwr +3.3v 40 gnd gnd 41 +3.3vsb pwr +3.3v 42 nc 43 gnd gnd 44 nc 45 nc 46 nc 47 nc 48 +1.5v pwr +1.5v 49 nc 50 gnd gnd 51 nc 52 +3...
Page 65
Chapter 2 – hardware information 51 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 pin pin name signal type signal level 6 +1.5v pwr +1.5v 7 nc 8 nc 9 gnd gnd 10 nc 11 nc 12 nc 13 nc 14 nc 15 gnd gnd 16 nc 17 nc 18 gnd gnd 19 nc gnd 20 nc 21 gnd gnd 22 nc out 23 sata_rx+ diff 24 +3.3v pwr +3.3v 25 sata...
Page 66
Chapter 2 – hardware information 52 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 pin pin name signal type signal level 32 smb_data i/o +3.3v 33 sata_tx+ diff 34 gnd gnd 35 gnd gnd 36 nc 37 gnd gnd 38 nc 39 +3.3v pwr +3.3v 40 gnd gnd 41 +3.3v pwr +3.3v 42 nc 43 gnd gnd 44 nc 45 nc 46 nc 47 nc 48 +1.5v...
Page 67
3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 chapter 3 chapter 3 - ami bios setup.
Page 68
Chapter 3 – ami bios setup 54 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 3.1 system test and initialization the board uses certain routines to perform testing and initialization. If an error, fatal or non-fatal, is encountered, a few short beeps or an error message will be outputted. The board can u...
Page 69
Chapter 3 – ami bios setup 55 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 3.2 ami bios setup the ami bios rom has a pre-installed setup program that allows users to modify basic system configurations, which is stored in the battery-backed cmos ram and bios nvram so that the information is retained wh...
Page 70
Chapter 3 – ami bios setup 56 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 3.3 setup submenu: main press ‘ delete ’ key to enter setup.
Page 71
Chapter 3 – ami bios setup 57 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 3.4 setup submenu: advanced.
Page 72
Chapter 3 – ami bios setup 58 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 3.4.1 advanced: trusted computing options summary: security device support disable optimal default, failsafe default enable enables or disables bios support for security device. O.S. Will not show security device. Tcg efi proto...
Page 73
Chapter 3 – ami bios setup 59 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 pending operation none optimal default, failsafe default tpm clear schedule an operation for the security device. Note: your computer will reboot during restart in order to change state of security device. Platform hierarchy di...
Page 74
Chapter 3 – ami bios setup 60 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 3.4.2 advanced: cpu management options summary: c-states disabled optimal default, failsafe default enabled enable/disable c states. Eist™ disabled optimal default, failsafe default enabled enable/disable intel speedstep. Intel...
Page 75
Chapter 3 – ami bios setup 61 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 enabled enable/disable cpu vt-d thermal monitor disabled optimal default, failsafe default enabled enable/disable thermal monitor.
Page 76
Chapter 3 – ami bios setup 62 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 3.4.3 advanced: hardware monitor options summary: smart fan disable optimal default, failsafe default enable enables or disables smart fan..
Page 77
Chapter 3 – ami bios setup 63 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 3.4.3.1 hardware monitor: cpu smart fan mode configuration options summary: fan 1 smart fan control manual rpm mode optimal default, failsafe default manual duty mode auto rpm mode auto duty-cycle mode smart fan mode select tem...
Page 78
Chapter 3 – ami bios setup 64 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 duty cycle 1 85 temperature 1 60 auto fan speed control. Fan speed will follow different temperature by different duty cycle 1-100
Page 79
Chapter 3 – ami bios setup 65 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 3.4.4 advanced: sio configuration.
Page 80
Chapter 3 – ami bios setup 66 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 3.4.4.1 sio configuration: serial port 1 configuration options summary: use this device disable optimal default, failsafe default enable enable or disable this logical device. Possible: use automatic settings optimal default, f...
Page 81
Chapter 3 – ami bios setup 67 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 3.4.4.2 sio configuration: serial port 2 configuration options summary: use this device disable optimal default, failsafe default enable enable or disable this logical device. Possible: use automatic settings optimal default, f...
Page 82
Chapter 3 – ami bios setup 68 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 3.4.4.3 sio configuration: serial port 3 configuration options summary: use this device disable optimal default, failsafe default enable enable or disable this logical device. Possible: use automatic settings optimal default, f...
Page 83
Chapter 3 – ami bios setup 69 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 3.4.4.4 sio configuration: serial port 4 configuration options summary: use this device disable optimal default, failsafe default enable enable or disable this logical device. Possible: use automatic settings optimal default, f...
Page 84
Chapter 3 – ami bios setup 70 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 3.4.4.5 sio configuration: parallel port configuration options summary: use this device disable optimal default, failsafe default enable enable or disable this logical device..
Page 85
Chapter 3 – ami bios setup 71 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 3.4.5 advanced: power management options summary: power mode atx type optimal default, failsafe default at type select system power mode power saving(erp) control disabled optimal default, failsafe default enabled configure pow...
Page 86
Chapter 3 – ami bios setup 72 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 rtc wake system from s5 disable optimal default, failsafe default fixed time dynamic time select system power mode.
Page 87
Chapter 3 – ami bios setup 73 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 3.4.6 advanced: digital io port configuration options summary: dio port* output input set dio as input or output output level high optimal default, failsafe default low set output level when dio pin is output.
Page 88
Chapter 3 – ami bios setup 74 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 3.5 setup submenu: chipset.
Page 89
Chapter 3 – ami bios setup 75 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 3.5.1 chipset: north bridge options summary: max tould 2 gb optimal default, failsafe default 2.25 gb 2.5 gb 2.75 gb 2 gb maximum value of tolud..
Page 90
Chapter 3 – ami bios setup 76 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 3.5.1.1 north bridge: lvds panel configuration * lvds2 only available for 2 lvds sku options summary: lvds disabled enabled optimal default, failsafe default enable/disabled this panel. Lvds panel type 640x480,18bit,60hz 800x48...
Page 91
Chapter 3 – ami bios setup 77 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 1366x768,24bit,60hz 1440x900,48bit,60hz 1600x1200,48bit,60hz 1920x1080,48bit,60hz 1920x1200,48bit,60hz select lcd panel used by internal graphics device by selecting the appropriate setup item. Color depth 18-bit optimal defaul...
Page 92
Chapter 3 – ami bios setup 78 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 backlight pwm freq 100hz 200hz 220hz optimal default, failsafe default 500hz 1khz 2.2khz 6.5khz select pwm frequency of backlight control signal.
Page 93
Chapter 3 – ami bios setup 79 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 3.6 setup submenu: security change user/administrator password if an administrator password is set, it will be required during boot up, or when the user enters the setup utility. Please note that a user password does not provid...
Page 94
Chapter 3 – ami bios setup 80 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 3.7 setup submenu: boot options summary: quiet boot disabled enabled optimal default, failsafe default enabledisable showing boot logo. Monitor mwait disable enabled auto optimal default, failsafe default enable/disable monitor...
Page 95
Chapter 3 – ami bios setup 81 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 3.8 setup submenu: save & exit.
Page 96
Chapter 3 – ami bios setup 82 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 3.9 note for users 1.To install linux os, set the monitor mwait to disabled (boot->monitor mwait->[disabled]) 2.Eist (enhanced intel speedstep technology) default is disabled, go to advanced->cpu configuration->eist to change t...
Page 97
3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 chapter 4 chapter 4 – drivers installation.
Page 98
Chapter 4 – driver installation 84 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 4.1 product cd/dvd the gene-apl5 comes with a product dvd that contains all the drivers and utilities you need to setup your product. Insert the dvd and follow the steps in the autorun program to install the drivers. In c...
Page 99
Chapter 4 – driver installation 85 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 3. Drivers will be installed automatically step 5 – install txe driver 1. Open the step5 - txe folder followed by setuptxe.Exe 2. Follow the instructions 3. Drivers will be installed automatically step 6 – install touch d...
Page 100
3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 appendix a appendix a - watchdog timer programming.
Page 101
Appendix a – watchdog timer programming 87 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 a.1 watchdog timer registers table 1 : watch dog relative io address default value note i/o base address 0xa10 i/o base address for watchdog operation. This address is assigned by sio ldn7, register 0x60-0x61. Tabl...
Page 102
Appendix a – watchdog timer programming 88 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 a.2 watchdog sample program ****************************************************************************** // wdt i/o operation relative definition (please reference to table 1) #define wdtaddr 0x510 // wdt i/o bas...
Page 103
Appendix a – watchdog timer programming 89 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 void aaeonwdtenable (){ wdtenabledisable(1); } // procedure : aaeonwdtconfig void aaeonwdtconfig (byte counter, boolean unit){ // disable wdt counting wdtenabledisable(0); // clear watchdog timeout status wdtcleart...
Page 104
Appendix a – watchdog timer programming 90 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 void wdtwritebyte(byte register, byte value){ iowritebyte(wdtaddr+register, value); } byte wdtreadbyte(byte register){ return ioreadbyte(wdtaddr+register); } void wdtsetbit(byte register, byte bit, byte val){ byte ...
Page 105
3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 appendix b appendix b - i/o information.
Page 106
Appendix b – i/o information 92 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 b.1 i/o address map.
Page 107
Appendix b – i/o information 93 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5.
Page 108
Appendix b – i/o information 94 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 b.2 memory address map.
Page 109
Appendix b – i/o information 95 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 b.3 irq mapping chart.
Page 110
Appendix b – i/o information 96 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5.
Page 111
Appendix b – i/o information 97 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5.
Page 112
Appendix b – i/o information 98 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5.
Page 113
Appendix b – i/o information 99 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5.
Page 114
3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 appendix c appendix c – mating connectors.
Page 115
Appendix c – electrical specifications for i/o ports 101 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 c.1 list of mating connectors and cables connector label function mating connector available cable cable p/n vendor model no cn1 external aux power and ps_on# jst phr-6 n/a n/a cn2 lvds port1 inverter...
Page 116
Appendix c – electrical specifications for i/o ports 102 3.5 ” s ub co m pa ct bo ard ge n e-a pl 5 connector cn15 ps/2 kb/ms connector jst phdr-06vs ps/2 kb/ms cable 1700060152 cn16 usb port #2 connector molex 51021-0500 usb cable 1700050207 cn17 usb port #3 connector molex 51021-0500 usb cable 170...
Page 117
3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 appendix d appendix d – digital i/o ports.
Page 118
Appendix d – digital i/o ports 104 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 d.1 digital i/o register.
Page 119
Appendix d – digital i/o ports 105 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5.
Page 120
Appendix d – digital i/o ports 106 3.5 ” s ub co m pa ct b oa rd ge n e-a pl 5 d.2 digital i/o sample code (4 in 4 out, 2 low 2 high) outportb(0x2e,0x87); //enter configuration outportb(0x2e,0x87); outportb(0x2e,0x07); //set ldn outportb(0x2f,0x06); outportb(0x2e,0xa0); //gpio set 5 register outport...