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Aaeon GENE-BT04 User Manual
Summary of GENE-BT04
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Last updated: november 9, 2015 gene-bt04 3.5” subcompact board user’s manual 1 st ed.
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Preface ii 3.5 ” s ub co mp act bo ard g ene -bt 04 copyright notice this document is copyrighted, 2015. All rights are reserved. The original manufacturer reserves the right to make improvements to the products described in this manual at any time without notice. No part of this manual may be repro...
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Preface iii 3.5 ” s ub co mp act bo ard g ene -bt 04 acknowledgement all other products’ name or trademarks are properties of their respective owners. Microsoft windows ® is a registered trademark of microsoft corp. Ite is a trademark of integrated technology express, inc. Ibm, pc/at, ps/2, and vga ...
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Preface iv 3.5 ” s ub co mp act bo ard g ene -bt 04 packing list before setting up your product, please make sure the following items have been shipped: item quantity gene-bt04 (with heat spreader) 1 product dvd with user’s manual (in pdf) and drivers 1 if any of these items are missing or damaged, ...
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Preface v 3.5 ” s ub co mp act bo ard g ene -bt 04 about this document this user’s manual contains all the essential information, such as detailed descriptions and explanations on the product’s hardware and software features (if any), its specifications, dimensions, jumper/connector settings/definit...
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Preface vi 3.5 ” s ub co mp act bo ard g ene -bt 04 safety precautions please read the following safety instructions carefully. It is advised that you keep this manual for future references 1. All cautions and warnings on the device should be noted. 2. Make sure the power source matches the power ra...
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Preface vii 3.5 ” s ub co mp act bo ard g ene -bt 04 17. If any of the following situations arises, please the contact our service personnel: i. Damaged power cord or plug ii. Liquid intrusion to the device iii. Exposure to moisture iv. Device is not working as expected or in a manner as described i...
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Preface viii 3.5 ” s ub co mp act bo ard g ene -bt 04 fcc statement this device complies with part 15 fcc rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference ...
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Preface ix 3.5 ” s ub co mp act bo ard g ene -bt 04 china rohs requirements (cn) 产品中有毒有害物质或元素名称及含量 aaeon main board/ daughter board/ backplane 部件名称 有毒有害物质或元素 铅 (pb) 汞 (hg) 镉 (cd) 六价铬 (cr(vi)) 多溴联苯 (pbb) 多溴二苯醚 (pbde) 印刷电路板 及其电子组件 × ○ ○ ○ ○ ○ 外部信号 连接器及线材 × ○ ○ ○ ○ ○ o：表示该有毒有害物质在该部件所有均质材料中的含量均在 sj/t 11...
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Preface x 3.5 ” s ub co mp act bo ard g ene -bt 04 china rohs requirement (en) poisonous or hazardous substances or elements in products aaeon main board/ daughter board/ backplane component poisonous or hazardous substances or elements lead (pb) mercury (hg) cadmium (cd) hexavalent chromium (cr(vi)...
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Preface xi 3.5 ” s ub co mp act bo ard g ene -bt 04 table of contents chapter 1 - product specifications ........................................................................................ 1 1.1 specifications ........................................................................................
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Preface xii 3.5 ” s ub co mp act bo ard g ene -bt 04 2.5.15 hdmi port 1 and 2 (cn20/ 21) ................................................... 23 2.5.16 lpc port (cn22) ............................................................................. 24 2.5.17 spi programming header (cn23) ..................
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Preface xiii 3.5 ” s ub co mp act bo ard g ene -bt 04 chapter 4 – drivers installation ............................................................................................ 56 4.1 product cd/dvd .....................................................................................................
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3.5 ” s ub co mp act bo ard g ene -bt 04 chapter 1 chapter 1 - product specifications.
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Chapter 1 – product specifications 2 3.5 ” s ub co mp act bo ard g ene -bt 04 1.1 specifications system form factor 3.5” processor intel ® atomtm n2807/ j1900 soc (1.58/ 2.0 ghz) system memory ddr3l 1333 mhz sodimm x 1, up to 8gb chipset intel ® atomtm n2807/ j1900 soc i/o chipset fintek 81801u ethe...
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Chapter 1 – product specifications 3 3.5 ” s ub co mp act bo ard g ene -bt 04 emi cd & fcc class a (pre-scan only) display chipset intel ® atomtm n2807/ j1900 soc engine intel ® atomtm n2807/ j1900 soc resolution up to 2560 x 1200 for hdmi output interface hdmi x 2 (hdmi1 with audio, hdmi2 without) ...
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3.5 ” s ub co mp act bo ard g ene -bt 04 chapter 2 chapter 2 – hardware information.
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Chapter 2 – hardware information 5 3.5 ” s ub co mp act bo ard g ene -bt 04 2.1 dimensions component side.
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Chapter 2 – hardware information 6 3.5 ” s ub co mp act bo ard g ene -bt 04 solder side.
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Chapter 2 – hardware information 7 3.5 ” s ub co mp act bo ard g ene -bt 04 2.2 jumpers and connectors component side.
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Chapter 2 – hardware information 8 3.5 ” s ub co mp act bo ard g ene -bt 04 solder side.
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Chapter 2 – hardware information 9 3.5 ” s ub co mp act bo ard g ene -bt 04 2.3 block diagram.
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Chapter 2 – hardware information 10 3.5 ” s ub co mp act bo ard g ene -bt 04 2.4 list of jumpers please refer to the table below for all of the board’s jumpers that you can configure for your application label function cn12 (1,3,5) clear cmos jumper cn12 (2,4,6) auto power button enable/disable sele...
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Chapter 2 – hardware information 11 3.5 ” s ub co mp act bo ard g ene -bt 04 2.5.1 clear cmos jumper (cn12, pin 1,3,5) normal (default) clear cmos 2.5.2 auto power button enable/disable selection (jp12, pin 2,4,6) enable (default) disable 2.5.3 push power button with orange led (sw4) pin pin name si...
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Chapter 2 – hardware information 12 3.5 ” s ub co mp act bo ard g ene -bt 04 l2 gnd gnd gnd 1 nc 2 pwrbtn# out 3 gnd gnd gnd 4 nc 5 nc 6 nc.
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Chapter 2 – hardware information 13 3.5 ” s ub co mp act bo ard g ene -bt 04 2.5 list of connectors please refer to the table below for all of the board’s connectors that you can configure for your application label function cn1 com port rs-232 cn2 +12v input cn3 lan (rj-45) port cn4 lan (rj-45) por...
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Chapter 2 – hardware information 14 3.5 ” s ub co mp act bo ard g ene -bt 04 2.5.1 com port rs-232 (cn1) 2.5.2 +12 v input (cn2) pin pin name signal type signal level 1 +12v pwr +12v 2-3 gnd gnd 2.5.3 lan port 1/2/3/4 (rj-45) (cn3,4,5,6) pin pin name signal type signal level 1 dcd in 2 rx in 3 tx ou...
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Chapter 2 – hardware information 15 3.5 ” s ub co mp act bo ard g ene -bt 04 pin pin name signal type signal level c1 mdi0+ diff c2 mdi0- diff c3 mdi1+ diff c4 mdi2+ diff c5 mdi2- diff c6 mdi1- diff c7 mdi3+ diff c8 mdi3- diff 2.5.4 +5 v output for sata hdd (cn7) pin pin name signal type signal leve...
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Chapter 2 – hardware information 16 3.5 ” s ub co mp act bo ard g ene -bt 04 2.5.5 sata port (cn8) pin pin name signal type signal level 1 gnd gnd 2 sata_txp1 diff 3 sata_txn1 diff 4 gnd gnd 5 sata_rxn1 diff 6 sata_rxp1 diff 7 gnd gnd 2.5.6 ddr3l sodimm slot (cn9) standard specification 2.5.7 digita...
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Chapter 2 – hardware information 17 3.5 ” s ub co mp act bo ard g ene -bt 04 4 dio2 i/o +5v 5 dio3 i/o +5v 6 gnd gnd 2.5.8 cfast card connector (cn11) pin pin name signal type signal level s1 gnd gnd s2 sata_txp0 diff s3 sata_txn0 diff s4 gnd gnd s5 sata_rxn0 diff s6 sata_rxp0 diff s7 gnd gnd p1 nc ...
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Chapter 2 – hardware information 18 3.5 ” s ub co mp act bo ard g ene -bt 04 p12 nc p13 +v3.3s pwr +3.3v p14 +v3.3s pwr +3.3v p15 gnd gnd p16 gnd gnd p17 nc 2.5.9 minicard slot (usb port2 only) (cn13) pin pin name signal type signal level 1 wake_pcie0#_3p3 in 2 +v3.3a pwr +3.3v 3 nc 4 gnd gnd 5 nc 6...
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Chapter 2 – hardware information 19 3.5 ” s ub co mp act bo ard g ene -bt 04 pin pin name signal type signal level 17 nc 18 gnd gnd 19 nc 20 wl_disable0# out +3.3v 21 gnd gnd 22 buf_plt_rst# out +3.3v 23 nc diff 24 +v3.3a pwr +3.3v 25 nc diff 26 gnd gnd 27 gnd gnd 28 +v1.5s pwr +1.5v 29 gnd gnd 30 s...
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Chapter 2 – hardware information 20 3.5 ” s ub co mp act bo ard g ene -bt 04 pin pin name signal type signal level 42 nc 43 nc 44 nc 45 nc 46 nc 47 nc 48 +v1.5s pwr +1.5v 49 nc 50 gnd gnd 51 nc 52 +v3.3a pwr +3.3v.
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Chapter 2 – hardware information 21 3.5 ” s ub co mp act bo ard g ene -bt 04 2.5.10 battery (cn14) pin pin name signal type signal level 1 +3.3v pwr 3.3v 2 gnd gnd 2.5.11 buzzer connector (cn15) pin pin name signal type signal level 1 +v3.3s pwr 3.3v 2 fp_buzzer out 3.3v 2.5.12 front panel connector...
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Chapter 2 – hardware information 22 3.5 ” s ub co mp act bo ard g ene -bt 04 4 +v3.3s pwr +3.3v 5 buzzer out 6 +v5s pwr +5v 7 gnd gnd 8 +v3.3s pwr +3.3v 9 gnd gnd 10 hwrst# in 2.5.13 usb 3.0 port 0 (cn17) pin pin name signal type signal level 1 +5vsb pwr +5v 2 usb0_d- diff 3 usb0_d+ diff 4 gnd gnd 5...
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Chapter 2 – hardware information 23 3.5 ” s ub co mp act bo ard g ene -bt 04 2.5.14 usb 2.0 port 3 and 1 (cn18/ 19) pin pin name signal type signal level 1 +5vsb pwr +5v 2 usb1_d- diff 3 usb1_d+ diff 4 gnd gnd 2.5.15 hdmi port 1 and 2 (cn20/ 21) pin pin name signal type signal level 1 tmds_dat2+ dif...
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Chapter 2 – hardware information 24 3.5 ” s ub co mp act bo ard g ene -bt 04 10 tmds_clk+ diff 11 gnd gnd 12 tmds_clk- diff 13 nc 14 nc 15 ddc_clk i/o +5v 16 ddc_data i/o +5v 17 gnd gnd 18 +5v i/o +5v 19 hplg_detect in 2.5.16 lpc port (cn22) pin pin name signal type signal level 1 lad0 i/o +3.3v 2 l...
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Chapter 2 – hardware information 25 3.5 ” s ub co mp act bo ard g ene -bt 04 9 lclk out 10 ldrq0 in 11 ldrq1 in 12 serirq i/o +3.3v 2.5.17 spi programming header (cn23) pin pin name signal type signal level 1 spi_so_f out 2 gnd gnd 3 spi_clk_f in 4 +v3.3a_spi pwr +3.3v 5 spi_si_f in 6 spi_cs0#_f in ...
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3.5 ” s ub co mp act bo ard g ene -bt 04 chapter 3 chapter 3 - ami bios setup.
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Chapter 3 – ami bios setup 27 3.5 ” s ub co mp act bo ard g ene -bt 04 3.1 system test and initialization the board uses certain routines to perform testing and initialization. If an error, fatal or non-fatal, is encountered, a few short beeps or an error message will be outputted. The board can usu...
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Chapter 3 – ami bios setup 28 3.5 ” s ub co mp act bo ard g ene -bt 04 3.2 ami bios setup the ami bios rom has a pre-installed setup program that allows users to modify basic system configurations, which is stored in the battery-backed cmos ram and bios nvram so that the information is retained when...
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Chapter 3 – ami bios setup 29 3.5 ” s ub co mp act bo ard g ene -bt 04 3.3 setup submenu: main press ‘ delete ’ key to enter setup.
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Chapter 3 – ami bios setup 30 3.5 ” s ub co mp act bo ard g ene -bt 04 3.4 setup submenu: advanced.
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Chapter 3 – ami bios setup 31 3.5 ” s ub co mp act bo ard g ene -bt 04 3.4.1 advanced: acpi settings options summary: acpi sleep state suspend disabled optimal default, failsafe default s3 (suspend to ram) select the highest acpi sleep state the system will enter when the suspend button is pressed. ...
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Chapter 3 – ami bios setup 32 3.5 ” s ub co mp act bo ard g ene -bt 04 at type select power supply mode wake on ring disabled optimal default, failsafe default enabled en/disabled wake from ring wake system with fixed time disabled optimal default, failsafe default enabled enable or disable system w...
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Chapter 3 – ami bios setup 33 3.5 ” s ub co mp act bo ard g ene -bt 04 3.4.2 advanced: f81801 super io configuration.
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Chapter 3 – ami bios setup 34 3.5 ” s ub co mp act bo ard g ene -bt 04 3.4.2.1 f81801 super io configuration: serial port 1 configuration options summary: serial port disabled enabled optimal default, failsafe default enable or disable serial port (com) change settings auto optimal default, failsafe...
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Chapter 3 – ami bios setup 35 3.5 ” s ub co mp act bo ard g ene -bt 04 io = 3e8h; irq = 3, 4, 5, 6, 7, 9, 10, 11, 12 io = 2e8h; irq = 3, 4, 5, 6, 7, 9, 10, 11, 12 select an optimal settings for super io device.
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Chapter 3 – ami bios setup 36 3.5 ” s ub co mp act bo ard g ene -bt 04 3.4.3 advanced: h/w monitor.
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Chapter 3 – ami bios setup 37 3.5 ” s ub co mp act bo ard g ene -bt 04 3.4.4 advanced: cpu configuration options summary: intel virtualization technology disabled enabled optimal default, failsafe default when enabled, a vmm can utilize the additional hardware capabilities provided by vander pool te...
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Chapter 3 – ami bios setup 38 3.5 ” s ub co mp act bo ard g ene -bt 04 3.4.4.1 cpu configuration: socket 0 cpu configuration.
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Chapter 3 – ami bios setup 39 3.5 ” s ub co mp act bo ard g ene -bt 04 3.4.5 advanced: ide configuration options summary: serial-ata (sata) enabled default disabled en/disable sata sata speed support gen1 gen2 default sata speed support gen1 or gen2 sata mode ide ahci default ide: configure sata con...
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Chapter 3 – ami bios setup 40 3.5 ” s ub co mp act bo ard g ene -bt 04 serial-ata port 0/1 enabled default disabled en/disable sata port sata port 0/1 hotplug enabled default disabled en/disable sata port hotplug.
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Chapter 3 – ami bios setup 41 3.5 ” s ub co mp act bo ard g ene -bt 04 3.4.6 advanced: dynamic digital io configuration options summary: digital port 1 /2 (gp30/ gp31) direction input default output set digital io port as input or output digital port 3 /4 (gp32/ gp33) direction input output default ...
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Chapter 3 – ami bios setup 42 3.5 ” s ub co mp act bo ard g ene -bt 04 3.4.7 advanced: usb configuration options summary: legacy usb support enabled optimal default, failsafe default disabled auto enables bios support for legacy usb support. When enabled, usb can be functional in legacy environment ...
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Chapter 3 – ami bios setup 43 3.5 ” s ub co mp act bo ard g ene -bt 04 cdrom if auto. Usb devices less than 530mb will be emulated as floppy and remaining as floppy and remaining as hard drive. Forced fdd option can be used to force a hdd formatted drive to boot as fdd(ex. Zip drive).
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Chapter 3 – ami bios setup 44 3.5 ” s ub co mp act bo ard g ene -bt 04 3.5 setup submenu: chipset.
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Chapter 3 – ami bios setup 45 3.5 ” s ub co mp act bo ard g ene -bt 04 3.5.1 chipset: host bridge.
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Chapter 3 – ami bios setup 46 3.5 ” s ub co mp act bo ard g ene -bt 04 3.5.1.1 host bridge: lcd control options summary: primary igfx boot display vbios default optimal default, failsafe default hdmi1 hdmi2 select the video device which will be activated during post. This has no effect if external g...
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Chapter 3 – ami bios setup 47 3.5 ” s ub co mp act bo ard g ene -bt 04 3.5.2 chipset: south bridge.
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Chapter 3 – ami bios setup 48 3.5 ” s ub co mp act bo ard g ene -bt 04 3.5.2.1 south bridge: usb configuration options summary: xhci mode enabled optimal default, failsafe default disabled auto smart auto mode of operation of xhci controller usb per port control enabled optimal default, failsafe def...
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Chapter 3 – ami bios setup 49 3.5 ” s ub co mp act bo ard g ene -bt 04 usb port 0/1/2/3 enabled optimal default, failsafe default disabled enable/disable usb port 0~3.
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Chapter 3 – ami bios setup 50 3.5 ” s ub co mp act bo ard g ene -bt 04 3.5.2.2 south bridge: pci express configuration options summary: pci express port 0/1/2/3 enabled optimal default, failsafe default disabled enable or disable the pci express port 0~3 in the chipset..
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Chapter 3 – ami bios setup 51 3.5 ” s ub co mp act bo ard g ene -bt 04 3.6 setup submenu: security change user/administrator password you can set a user password once an administrator password is set. The password will be required during boot up, or when the user enters the setup utility. Please not...
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Chapter 3 – ami bios setup 52 3.5 ” s ub co mp act bo ard g ene -bt 04 removing the password highlight this item and type in the current password. At the next dialog box press enter to disable password protection..
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Chapter 3 – ami bios setup 53 3.5 ” s ub co mp act bo ard g ene -bt 04 3.6.1 security: secure boot options summary: secure boot disabled optimal default, failsafe default enabled secure boot can be enabled if 1. System running in user mode with enrolled platform key (pk) 2. Csm function is disabled ...
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Chapter 3 – ami bios setup 54 3.5 ” s ub co mp act bo ard g ene -bt 04 3.7 setup submenu: boot options summary: quiet boot disabled default enabled en/disable showing boot logo. Pxe do not launch default enabled en/disable pxe boot.
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Chapter 3 – ami bios setup 55 3.5 ” s ub co mp act bo ard g ene -bt 04 3.8 setup submenu: save & exit.
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3.5 ” s ub co mp act bo ard g ene -bt 04 chapter 4 chapter 4 – drivers installation.
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Chapter 4 – driver installation 57 3.5 ” s ub co mp act bo ard g ene -bt 04 4.1 product cd/dvd the gene-bt04 comes with a product dvd that contains all the drivers and utilities you need to setup your product. Insert the dvd and follow the steps in the autorun program to install the drivers. In case...
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Chapter 4 – driver installation 58 3.5 ” s ub co mp act bo ard g ene -bt 04 2. Open the setuptxe.Exe file in the folder 3. Follow the instructions 4. Drivers will be installed automatically step 5 – install usb 3.0 driver (windows 7 only) 1. Open the step5 - usb3.0 folder followed by setup.Exe 2. Fo...
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3.5 ” s ub co mp act bo ard g ene -bt 04 appendix a appendix a - watchdog timer programming.
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Appendix a – watchdog timer programming 60 3.5 ” s ub co mp act bo ard g ene -bt 04 a.1 watchdog timer registers table 1 : watch dog relative io address default value note i/o base address 0xa00 i/o base address for watchdog operation. This address is assigned by sio ldn7, register 0x60-0x61. Table ...
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Appendix a – watchdog timer programming 61 3.5 ” s ub co mp act bo ard g ene -bt 04 a.2 watchdog sample program ****************************************************************************** // wdt i/o operation relative definition (please reference to table 1) #define wdtaddr 0xa00 // wdt i/o base ...
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Appendix a – watchdog timer programming 62 3.5 ” s ub co mp act bo ard g ene -bt 04 void aaeonwdtenable (){ wdtenabledisable(1); } // procedure : aaeonwdtconfig void aaeonwdtconfig (byte counter, boolean unit){ // disable wdt counting wdtenabledisable(0); // clear watchdog timeout status wdtcleartim...
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Appendix a – watchdog timer programming 63 3.5 ” s ub co mp act bo ard g ene -bt 04 void wdtwritebyte(byte register, byte value){ iowritebyte(wdtaddr+register, value); } byte wdtreadbyte(byte register){ return ioreadbyte(wdtaddr+register); } void wdtsetbit(byte register, byte bit, byte val){ byte tm...
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3.5 ” s ub co mp act bo ard g ene -bt 04 appendix b appendix b - i/o information.
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Appendix b – i/o information 65 3.5 ” s ub co mp act bo ard g ene -bt 04 b.1 i/o address map note: there is no ps/2 interface on the gene-bt04, hence the exclamation marks.
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Appendix b – i/o information 66 3.5 ” s ub co mp act bo ard g ene -bt 04.
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Appendix b – i/o information 67 3.5 ” s ub co mp act bo ard g ene -bt 04 b.2 memory address map.
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Appendix b – i/o information 68 3.5 ” s ub co mp act bo ard g ene -bt 04 b.3 irq mapping chart note: there is no ps/2 interface on the gene-bt04, hence the exclamation marks.
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Appendix b – i/o information 69 3.5 ” s ub co mp act bo ard g ene -bt 04.
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Appendix b – i/o information 70 3.5 ” s ub co mp act bo ard g ene -bt 04.
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Appendix b – i/o information 71 3.5 ” s ub co mp act bo ard g ene -bt 04.
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Appendix b – i/o information 72 3.5 ” s ub co mp act bo ard g ene -bt 04.
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Appendix b – i/o information 73 3.5 ” s ub co mp act bo ard g ene -bt 04.
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Appendix b – i/o information 74 3.5 ” s ub co mp act bo ard g ene -bt 04.
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Appendix b – i/o information 75 3.5 ” s ub co mp act bo ard g ene -bt 04.
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Appendix b – i/o information 76 3.5 ” s ub co mp act bo ard g ene -bt 04.
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Appendix b – i/o information 77 3.5 ” s ub co mp act bo ard g ene -bt 04.
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Appendix b – i/o information 78 3.5 ” s ub co mp act bo ard g ene -bt 04.
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Appendix b – i/o information 79 3.5 ” s ub co mp act bo ard g ene -bt 04.
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3.5 ” s ub co mp act bo ard g ene -bt 04 appendix c appendix c – mating connectors.
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Appendix c – mating connectors 81 3.5 ” s ub co mp act bo ard g ene -bt 04 c.1 list of mating connectors and cables connector label function mating connector available cable cable p/n vendor model no cn8 sata molex 88750-5318 sata cable.7p pitch 1.27mm.50 cm 170907050 0 cn7 +5vout connector jst phr-...
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3.5 ” s ub co mp act bo ard g ene -bt 04 appendix d appendix d – electrical specifications for i/o ports.
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Appendix d – electrical specifications for i/o ports 83 3.5 ” s ub co mp act bo ard g ene -bt 04 d.1 electrical specifications for i/o ports i/o reference signal name rate output com port cn1 +5v/+12v +5v/1a or +12v/1a +5v output for sata hdd cn7 +5v +5v/1a digital io port cn10 +5v +5v/1a c-fast slo...
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3.5 ” s ub co mp act bo ard g ene -bt 04 appendix e appendix e – digital i/o ports.
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Appendix e – digital i/o ports 85 3.5 ” s ub co mp act bo ard g ene -bt 04 e.1 electrical specifications for digital i/o ports table 1 : digital input/output pin electrical specification pin type input threshold voltage output voltage note low high low high dio1 i/o 0.8 2.0 0 3.3 dio2 i/o 0.8 2.0 0 ...
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Appendix e – digital i/o ports 86 3.5 ” s ub co mp act bo ard g ene -bt 04 e.2 di/o programming gene-bt04 utilizes fintek f81801u chipset as its digital i/o controller. Below are the procedures to complete its configuration and the aaeon initial di/o program is also attached, based on which you can ...
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Appendix e – digital i/o ports 87 3.5 ” s ub co mp act bo ard g ene -bt 04 e.3 digital i/o register table 2 : superio relative register table default value note index 0x2e sio mb pnp mode index register 0x2e or 0x4e data 0x2f) sio mb pnp mode data register 0x2f or 0x4f table 3 : digital input/output...
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Appendix e – digital i/o ports 88 3.5 ” s ub co mp act bo ard g ene -bt 04 e.4 digital i/o sample program ************************************************************************** // superio relative definition (please reference to table 2) #define sioindex 0x2e #define siodata 0x2f #define dioldn ...
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Appendix e – digital i/o ports 89 3.5 ” s ub co mp act bo ard g ene -bt 04 ************************************************************************** ************************************************************************** boolean aaeonreadpinstatus(byte pinbit){ boolean pinstatus ; pinstatus = si...
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Appendix e – digital i/o ports 90 3.5 ” s ub co mp act bo ard g ene -bt 04 void siobyteset(byte ldn, byte register, byte value){ sioentermbpnpmode(); sioselectldn(ldn); iowritebyte(sioindex, register); iowritebyte(siodata, value); sioexitmbpnpmode(); } ***********************************************...