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Aaeon GENE-KBU6 User Manual
Summary of GENE-KBU6
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Last updated: june 30, 2017 gene-kbu6 3.5” subcompact board user’s manual 1 st ed.
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Preface ii 3.5 ” s ub co mp act bo ard g ene -k bu6 copyright notice this document is copyrighted, 2017. All rights are reserved. The original manufacturer reserves the right to make improvements to the products described in this manual at any time without notice. No part of this manual may be repro...
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Preface iii 3.5 ” s ub co mp act bo ard g ene -k bu6 acknowledgement all other products’ name or trademarks are properties of their respective owners. Microsoft windows is a registered trademark of microsoft corp. Intel, pentium, celeron, and xeon are registered trademarks of intel corporation core,...
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Preface iv 3.5 ” s ub co mp act bo ard g ene -k bu6 packing list before setting up your product, please make sure the following items have been shipped: item quantity gene-kbu6 with heat spreader 1 product dvd with user’s manual (in pdf) and drivers 1 if any of these items are missing or damaged, pl...
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Preface v 3.5 ” s ub co mp act bo ard g ene -k bu6 about this document this user’s manual contains all the essential information, such as detailed descriptions and explanations on the product’s hardware and software features (if any), its specifications, dimensions, jumper/connector settings/definit...
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Preface vi 3.5 ” s ub co mp act bo ard g ene -k bu6 safety precautions please read the following safety instructions carefully. It is advised that you keep this manual for future references 1. All cautions and warnings on the device should be noted. 2. Make sure the power source matches the power ra...
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Preface vii 3.5 ” s ub co mp act bo ard g ene -k bu6 17. If any of the following situations arises, please the contact our service personnel: i. Damaged power cord or plug ii. Liquid intrusion to the device iii. Exposure to moisture iv. Device is not working as expected or in a manner as described i...
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Preface viii 3.5 ” s ub co mp act bo ard g ene -k bu6 fcc statement this device complies with part 15 fcc rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference ...
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Preface ix 3.5 ” s ub co mp act bo ard g ene -k bu6 china rohs requirements (cn) 产品中有毒有害物质或元素名称及含量 aaeon main board/ daughter board/ backplane 部件名称 有毒有害物质或元素 铅 (pb) 汞 (hg) 镉 (cd) 六价铬 (cr(vi)) 多溴联苯 (pbb) 多溴二苯醚 (pbde) 印刷电路板 及其电子组件 ○ ○ ○ ○ ○ ○ 外部信号 连接器及线材 ○ ○ ○ ○ ○ ○ o：表示该有毒有害物质在该部件所有均质材料中的含量均在 sj/t 11...
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Preface x 3.5 ” s ub co mp act bo ard g ene -k bu6 china rohs requirement (en) poisonous or hazardous substances or elements in products aaeon main board/ daughter board/ backplane component poisonous or hazardous substances or elements lead (pb) mercury (hg) cadmium (cd) hexavalent chromium (cr(vi)...
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Preface xi 3.5 ” s ub co mp act bo ard g ene -k bu6 table of contents chapter 1 - product specifications.......................................................................................... 1 1.1 specifications .......................................................................................
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Preface xii 3.5 ” s ub co mp act bo ard g ene -k bu6 2.6.7 lan (rj-45) port1 (cn9) .................................................................... 22 2.6.8 lan (rj-45) port2 (cn10) .................................................................. 23 2.6.9 mini-card slot (full-mini card) (cn11)...
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Preface xiii 3.5 ” s ub co mp act bo ard g ene -k bu6 3.3 setup submenu: main ........................................................................................... 51 3.4 setup submenu: advanced ................................................................................. 52 3.4.1 advanced...
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Preface xiv 3.5 ” s ub co mp act bo ard g ene -k bu6 3.242 setup submenu: exit .............................................................................................. 81 chapter 4 – drivers installation .............................................................................................
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Preface xv 3.5 ” s ub co mp act bo ard g ene -k bu6 d.2 di/o programming ............................................................................................. 106 d.3 digital i/o register .............................................................................................. 107 d.4 d...
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3.5 ” s ub co mp act bo ard g ene -kb u6 chapter 1 chapter 1 - product specifications.
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Chapter 1 – product specifications 2 3.5 ” s ub co mp act bo ard g ene -k bu6 1.1specifications system form factor 3.5'' subcompact board cpu intel® skylake-u i7-7600u/i5-7300u soc processor cpu frequency up to 3.4ghz chipset intel® skylake-u soc processor memory type ddr4 1866/2133, sodimm x1 max m...
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Chapter 1 – product specifications 3 3.5 ” s ub co mp act bo ard g ene -k bu6 certification ce/fcc display vga/lcd controller intel® skylake-u soc processor video output dvi, crt/dp, lvds (crt is shared with dp, and default is dp) backlight inverter supply yes i/o ethernet intel i210, 10/100/1000bas...
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3.5 ” s ub co mp act bo ard g ene -s ku6 chapter 2 chapter 2 – hardware information.
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Chapter 2 – hardware information 5 3.5 ” s ub co mp act bo ard g ene -k bu6 2.1 dimensions component side component side.
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Chapter 2 – hardware information 6 3.5 ” s ub co mp act bo ard g ene -k bu6 solder side (with heat spreader) solder side unit mm.
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Chapter 2 – hardware information 7 3.5 ” s ub co mp act bo ard g ene -k bu6 cooler option (part number: 17592sku60).
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Chapter 2 – hardware information 8 3.5 ” s ub co mp act bo ard g ene -k bu6 2.2 jumpers and connectors component side.
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Chapter 2 – hardware information 9 3.5 ” s ub co mp act bo ard g ene -k bu6 2.3 assembly options option 1.
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Chapter 2 – hardware information 10 3.5 ” s ub co mp act bo ard g ene -k bu6 option 2.
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Chapter 2 – hardware information 11 3.5 ” s ub co mp act bo ard g ene -k bu6 2.4 block diagram.
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Chapter 2 – hardware information 12 3.5 ” s ub co mp act bo ard g ene -k bu6 2.5 list of jumpers please refer to the table below for all of the board’s jumpers that you can configure for your application label function jp1 clear cmos jumper jp2 lvds port backlight inverter vcc selection jp3 lvds por...
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Chapter 2 – hardware information 13 3.5 ” s ub co mp act bo ard g ene -k bu6 2.5.1 clear cmos jumper (jp1) normal (default) clear cmos 2.5.2 lvds port backlight inverter vcc selection (jp2) +12v +5v (default) 2.5.3 lvds port backlight lightness control mode selection (jp3) vr mode (default) pwm mode...
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Chapter 2 – hardware information 14 3.5 ” s ub co mp act bo ard g ene -k bu6 2.5.5 msata/ mini-card operating vcc selection (jp5) msata (default) mini-card 2.5.6 touch screen 4,5,8 wire selection (jp6) 4/8 wires mode (default) 5 wires mode 2.5.7 auto power button enable/disable selection (jp7) disab...
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Chapter 2 – hardware information 15 3.5 ” s ub co mp act bo ard g ene -k bu6 2.5.9 com3 pin8 function selection (jp9) +12v ring (default) +5v 2.5.10 front panel connector (jp10) pin pin name pin pin name 1 pwr_btn- 2 pwr_btn+ 3 hdd_led- 4 hdd_led+ 5 speaker- 6 speaker+ 7 pwr_led- 8 pwr_led+ 9 h/w re...
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Chapter 2 – hardware information 16 3.5 ” s ub co mp act bo ard g ene -k bu6 2.6 list of connectors please refer to the table below for all of the board’s connectors that you can configure for your application. Label function cn1 battery cn3 dvi-i (digital and analog) cn5 dp port cn6 lvds port cn7 l...
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Chapter 2 – hardware information 17 3.5 ” s ub co mp act bo ard g ene -k bu6 cn28 com port 3 cn29 lpc port cn30 external power input cn32 +5vsb output w/smbus cn33 external +5vsb input cn35 bio connector cn36 cpu fan.
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Chapter 2 – hardware information 18 3.5 ” s ub co mp act bo ard g ene -k bu6 2.6.1 battery (cn1) pin pin name signal type signal level 1 +3.3v pwr 3.3v 2 gnd gnd 2.6.2 dvi-i (digital and analog) (cn3) pin pin name signal type signal level 1 dvi_d2- out 2 dvi_d2+ out 3 gnd gnd 4 vga_ddc_clk i/o 5 vga...
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Chapter 2 – hardware information 19 3.5 ” s ub co mp act bo ard g ene -k bu6 20 nc 21 nc 22 gnd gnd 23 dvi_clk+ out 24 dvi_clk- out c1 vga_red out c2 vga_green out c3 vga_blue out c4 vga_hsync out 2.6.3 dp port (cn5) pin pin name signal type signal level 1 dp_d0+ diff 2 gnd gnd 3 dp_d0- diff 4 dp_d1...
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Chapter 2 – hardware information 20 3.5 ” s ub co mp act bo ard g ene -k bu6 16 gnd gnd 17 dp_aux- diff 18 hplg_detect in 19 gnd gnd 20 +5v i/o +5v 2.6.4 lvds port (cn6) *lvds lcd_pwr can be set to +3.3v or +5v by jp4 pin pin name signal type signal level 1 bkl_enable out 2 bkl_control out 3 lcd_pwr...
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Chapter 2 – hardware information 21 3.5 ” s ub co mp act bo ard g ene -k bu6 11 lvds_da1- diff 12 lvds_da1+ diff 13 lvds_da2- diff 14 lvds_da2+ diff 15 lvds_da3- diff 16 lvds_da3+ diff 17 ddc_data i/o +3.3v 18 ddc_clk i/o +3.3v 19 lvds_db0- diff 20 lvds_db0+ diff 21 lvds_db1- diff 22 lvds_db1+ diff ...
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Chapter 2 – hardware information 22 3.5 ” s ub co mp act bo ard g ene -k bu6 pin pin name signal type signal level 1 bkl_pwr pwr +5v / +12v 2 bkl_control out 3 gnd gnd 4 gnd gnd 5 bkl_enable out +5v * lvds bkl_pwr can be set to +5v or +12v by jp2 * lvds bkl_control can be set by jp3 2.6.6 spi debug ...
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Chapter 2 – hardware information 23 3.5 ” s ub co mp act bo ard g ene -k bu6 2 mdi0- diff 3 mdi1+ diff 4 mdi2+ diff 5 mdi2- diff 6 mdi1- diff 7 mdi3+ diff 8 mdi3- diff 2.6.8 lan (rj-45) port2 (cn10) pin pin name signal type signal level 1 mdi0+ diff 2 mdi0- diff 3 mdi1+ diff 4 mdi2+ diff 5 mdi2- dif...
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Chapter 2 – hardware information 24 3.5 ” s ub co mp act bo ard g ene -k bu6 2 +3.3vsb pwr +3.3v 3 nc 4 gnd gnd 5 nc 6 +1.5v pwr +1.5v 7 pcie_clk_req# in 8 uim_pwr pwr 9 gnd gnd 10 uim_data i/o 11 pcie_ref_clk- diff 12 uim_clk in 13 pcie_ref_clk+ diff 14 uim_rst in 15 gnd gnd 16 uim_vpp pwr 17 nc 18...
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Chapter 2 – hardware information 25 3.5 ” s ub co mp act bo ard g ene -k bu6 29 gnd gnd 30 smb_clk i/o +3.3v 31 pcie_tx- diff 32 smb_data i/o +3.3v 33 pcie_tx+ diff 34 gnd gnd 35 gnd gnd 36 usb_d- diff 37 gnd gnd 38 usb_d+ diff 39 +3.3vsb pwr +3.3v 40 gnd gnd 41 +3.3vsb pwr +3.3v 42 nc 43 gnd gnd 44...
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Chapter 2 – hardware information 26 3.5 ” s ub co mp act bo ard g ene -k bu6 2.6.10 micro sim card socket (cn12) pin pin name signal type signal level 1 uim_pwr pwr 2 uim_rst in 3 uim_clk in 4 nc 5 gnd gnd 6 uim_vpp pwr 7 uim_data i/o 8 nc 2.6.11 mini-card slot (half-mini card) (cn13) pin pin name s...
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Chapter 2 – hardware information 27 3.5 ” s ub co mp act bo ard g ene -k bu6 13 pcie_ref_clk+ diff 14 nc 15 gnd gnd 16 nc 17 nc 18 gnd gnd 19 nc 20 w_disable# out +3.3v 21 gnd gnd 22 pcie_rst# out +3.3v 23 pcie_rx-/msata_rx+ diff 24 +3.3vsb pwr +3.3v 25 pcie_rx+/msata_rx- diff 26 gnd gnd 27 gnd gnd ...
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Chapter 2 – hardware information 28 3.5 ” s ub co mp act bo ard g ene -k bu6 40 gnd gnd 41 +3.3vsb pwr +3.3v 42 nc 43 gnd gnd 44 nc 45 nc 46 nc 47 nc 48 +1.5v pwr +1.5v 49 nc 50 gnd gnd 51 nc 52 +3.3vsb pwr +3.3v * cn13 can be selected for mini-card or msata by changing bios 2.6.12 sata port 1 (cn14...
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Chapter 2 – hardware information 29 3.5 ” s ub co mp act bo ard g ene -k bu6 2.6.13 +5v output for sata hdd (cn15) pin pin name signal type signal level 1 +5v pwr +5v 2 gnd gnd 2.6.14 usb 3.0 ports (cn18) pin pin name signal type signal level 1 +5vsb pwr +5v 2 usb_d- diff 3 usb_d+ diff 4 gnd gnd 5 u...
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Chapter 2 – hardware information 30 3.5 ” s ub co mp act bo ard g ene -k bu6 13 gnd gnd 14 usb_ssrx− diff 15 usb_ssrx+ diff 16 gnd gnd 17 usb_sstx− diff 18 usb_sstx+ diff 2.6.15 usb 3.0 ports (cn19) pin pin name signal type signal level 1 +5vsb pwr +5v 2 usb_d- diff 3 usb_d+ diff 4 gnd gnd 5 usb_ssr...
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Chapter 2 – hardware information 31 3.5 ” s ub co mp act bo ard g ene -k bu6 14 usb_ssrx− diff 15 usb_ssrx+ diff 16 gnd gnd 17 usb_sstx− diff 18 usb_sstx+ diff 2.6.16 usb 2.0 port (cn20) pin pin name signal type signal level 1 +5vsb pwr +5v 2 usb_d- diff 3 usb_d+ diff 4 gnd gnd 5 gnd gnd 2.6.17 usb ...
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Chapter 2 – hardware information 32 3.5 ” s ub co mp act bo ard g ene -k bu6 2 usb_d- diff 3 usb_d+ diff 4 gnd gnd 5 g nd gnd 2.6.18 audio i/o port (cn22) pin pin name signal type signal level 1 mic_l in 2 mic_r in 3 gnd_audio gnd 4 line_l_in in 5 line_r_in in 6 gnd_audio gnd 7 left_out out 8 gnd_au...
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Chapter 2 – hardware information 33 3.5 ” s ub co mp act bo ard g ene -k bu6 2.6.19 touchscreen connector (cn23) * touch mode can be set by jp6 4-wire pin pin name signal type signal level 1 gnd gnd 2 top in 3 bottom in 4 left in 5 right in 6 nc 7 nc 8 nc 9 nc 5-wire pin pin name signal type signal ...
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Chapter 2 – hardware information 34 3.5 ” s ub co mp act bo ard g ene -k bu6 1 gnd gnd 2 ul(y) in 3 ur(h) in 4 ll(l) in 5 lr(x) in 6 sense(s) in 7 nc 8 nc 9 nc 8-wire pin pin name signal type signal level 1 gnd gnd 2 top excite in 3 bottom excite in 4 left excite in 5 right excite in 6 top sense in ...
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Chapter 2 – hardware information 35 3.5 ” s ub co mp act bo ard g ene -k bu6 2.6.20 digital i/o port (cn24) pin pin name signal type signal level 1 dio0 i/o +5v 2 dio1 i/o +5v 3 dio2 i/o +5v 4 dio3 i/o +5v 5 dio4 i/o +5v 6 dio5 i/o +5v 7 dio6 i/o +5v 8 dio7 i/o +5v 9 +5v pwr +5v 10 gnd gnd 2.6.21 co...
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Chapter 2 – hardware information 36 3.5 ” s ub co mp act bo ard g ene -k bu6 3 rx in 4 rts out ±9v 5 tx out ±9v 6 cts in 7 dtr out ±9v 8 ri in 9 gnd gnd 2.6.22 com port 4 (cn26) rs-232 pin pin name signal type signal level 1 dcd in 2 dsr in 3 rx in 4 rts out ±5v 5 tx out ±5v 6 cts in 7 dtr out ±5v 8...
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Chapter 2 – hardware information 37 3.5 ” s ub co mp act bo ard g ene -k bu6 rs-422 pin pin name signal type signal level 1 rs422_tx- out ±5v 2 nc 3 rs422_tx+ out ±5v 4 nc 5 rs422_rx+ in 6 nc 7 rs422_rx- in 8 nc/+5v/+12v pwr +5v/+12v 9 gnd gnd rs-485 pin pin name signal type signal level 1 rs485_d- ...
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Chapter 2 – hardware information 38 3.5 ” s ub co mp act bo ard g ene -k bu6 3 rs485_d+ i/o ±5v 4 nc 5 nc 6 nc 7 nc 8 nc/+5v/+12v pwr +5v/+12v 9 gnd gnd * com4 rs-232/422/485 can be set by bios setting. Default is rs-232. * pin 8 function can be set by jp11. 2.6.23 com port 2 (cn27) rs-232 pin pin n...
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Chapter 2 – hardware information 39 3.5 ” s ub co mp act bo ard g ene -k bu6 8 ri/+5v/+12v in/ pwr +5v/+12v 9 gnd gnd rs-422 pin pin name signal type signal level 1 rs422_tx- out ±5v 2 nc 3 rs422_tx+ out ±5v 4 nc 5 rs422_rx+ in 6 nc 7 rs422_rx- in 8 nc/+5v/+12v pwr +5v/+12v 9 gnd gnd rs-485 rs422_tx...
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Chapter 2 – hardware information 40 3.5 ” s ub co mp act bo ard g ene -k bu6 pin pin name signal type signal level 1 rs485_d- i/o ±5v 2 nc 3 rs485_d+ i/o ±5v 4 nc 5 nc 6 nc 7 nc 8 nc/+5v/+12v pwr +5v/+12v 9 gnd gnd * com2 rs-232/422/485 can be set by bios setting. Default is rs-232. * pin 8 function...
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Chapter 2 – hardware information 41 3.5 ” s ub co mp act bo ard g ene -k bu6 5 tx out ±5v 6 cts in 7 dtr out ±5v 8 ri/+5v/+12v in/ pwr +5v/+12v 9 gnd gnd rs-422 pin pin name signal type signal level 1 rs422_tx- out ±5v 2 nc 3 rs422_tx+ out ±5v 4 nc 5 rs422_rx+ in 6 nc 7 rs422_rx- in 8 nc/+5v/+12v pw...
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Chapter 2 – hardware information 42 3.5 ” s ub co mp act bo ard g ene -k bu6 rs-485 pin pin name signal type signal level 1 rs485_d- i/o ±5v 2 nc 3 rs485_d+ i/o ±5v 4 nc 5 nc 6 nc 7 nc 8 nc/+5v/+12v pwr +5v/+12v 9 gnd gnd * com3 rs-232/422/485 can be set by bios setting. Default is rs-232. * pin 8 f...
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Chapter 2 – hardware information 43 3.5 ” s ub co mp act bo ard g ene -k bu6 6 lframe# in 7 lreset# out +3.3v 8 gnd gnd 9 lclk out 10 ldrq0 in 11 ldrq1 in 12 serirq i/o +3.3v 2.6.26 external power input (cn30) pin pin name signal type signal level 1 +12v pwr +9~+36v (or +12v) 2 gnd gnd 2.6.27 +5vsb ...
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Chapter 2 – hardware information 44 3.5 ” s ub co mp act bo ard g ene -k bu6 4 gnd gnd 5 ps_on# out +3.3v 6 +5vsb pwr +5v 2.6.28 external +5vsb input (cn33) pin pin name signal type signal level 1 ps_on# out +3.3v 2 gnd gnd 3 +5vsb pwr +5v 2.6.29 bio connector (cn35) pin pin name signal type signal ...
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Chapter 2 – hardware information 45 3.5 ” s ub co mp act bo ard g ene -k bu6 11 pcie2_rx- i/o 12 pcie2_tx+ i/o 13 pcie2_rx+ i/o 14 gnd gnd 15 gnd gnd 16 ps_on# out 17 nc 18 nc 19 +5v_dual pwr +5v 20 +5v_dual pwr +5v 21 +5v_dual pwr +5v 22 +5v_dual pwr +5v 23 pcie_clk+ out 24 plt_rst# out 25 pcie_clk...
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Chapter 2 – hardware information 46 3.5 ” s ub co mp act bo ard g ene -k bu6 38 gnd gnd 39 gnd gnd 40 nc 41 nc 42 gnd gnd 43 nc 44 usb 3.0_tx- i/o 45 gnd gnd 46 usb 3.0_tx+ i/o 47 usb 2.0_d- i/o 48 gnd gnd 49 usb 2.0_d+ i/o 50 usb 3.0_rx- i/o 51 gnd gnd 52 usb 3.0_rx+ i/o 53 smb_clk i/o 54 gnd gnd 5...
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Chapter 2 – hardware information 47 3.5 ” s ub co mp act bo ard g ene -k bu6 65 lpc_ad0 i/o 66 lpc_frame# i/o 67 lpc_ad1 i/o 68 serirq# i/o 69 lpc_ad2 i/o 70 nc 71 lpc_ad3 i/o 72 gpio i/o 73 gnd gnd 74 audio_gnd gnd 75 lpc_clk out 76 audio_out_l out 77 pme# in 78 audio_out_r out 79 gnd gnd 80 gnd gn...
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3.5 ” s ub co mp act bo ard g ene -s ku6 chapter 3 chapter 3 - ami bios setup.
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Chapter 3 – ami bios setup 49 3.5 ” s ub co mp act bo ard g ene -k bu6 3.1 system test and initialization these routines test and initialize board hardware. If the routines encounter an error during the tests, you will either hear a few short beeps or see an error message on the screen. There are tw...
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Chapter 3 – ami bios setup 50 3.5 ” s ub co mp act bo ard g ene -k bu6 3.2 ami bios setup ami bios rom has a built-in setup program that allows users to modify the basic system configuration. This type of information is stored in battery-backed cmos ram and bios nvram so that it retains the setup in...
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Chapter 3 – ami bios setup 51 3.5 ” s ub co mp act bo ard g ene -k bu6 3.3 setup submenu: main.
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Chapter 3 – ami bios setup 52 3.5 ” s ub co mp act bo ard g ene -k bu6 3.4 setup submenu: advanced.
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Chapter 3 – ami bios setup 53 3.5 ” s ub co mp act bo ard g ene -k bu6 3.4.1 advanced: cpu configuration options summary: (default setting) hyper-threading disabled enabled optimal default, failsafe default enabled for windows xp and linux (os optimized for hyper-threading technology) and disabled f...
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Chapter 3 – ami bios setup 54 3.5 ” s ub co mp act bo ard g ene -k bu6 intel(r) speedstep(tm) disabled enabled optimal default, failsafe default allows more than two frequency ranges to be supported. Turbo mode disabled enabled optimal default, failsafe default enable/disable processor turbo mode (r...
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Chapter 3 – ami bios setup 55 3.5 ” s ub co mp act bo ard g ene -k bu6 3.4.2 trusted computing options summary: (default setting) security device support disable enable optimal default, failsafe default enables or disables bios support for security device. O.S. Will not show security device. Tcg efi...
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Chapter 3 – ami bios setup 56 3.5 ” s ub co mp act bo ard g ene -k bu6 platform hierarchy disable enable optimal default, failsafe default enable or disable platform hierarchy storage hierarchy disable enable optimal default, failsafe default enable or disable storage hierarchy endorsement hierarchy...
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Chapter 3 – ami bios setup 57 3.5 ” s ub co mp act bo ard g ene -k bu6 3.5 sata configuration options summary: sata controller(s) enabled optimal default, failsafe default disabled enable or disable sata device. Sata mode ahci mode optimal default, failsafe default raid mode determines how sata cont...
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Chapter 3 – ami bios setup 58 3.5 ” s ub co mp act bo ard g ene -k bu6 3.6 hardware monitor smart fan enabled enable or disable smart fan disabled.
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Chapter 3 – ami bios setup 59 3.5 ” s ub co mp act bo ard g ene -k bu6 3.7 smart fan mode configuration options summary: fan mode manual duty auto duty optimal default, failsafe default smart fan mode select duty cycle auto fan speed control. Fan speed will follow different temperature by different ...
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Chapter 3 – ami bios setup 60 3.5 ” s ub co mp act bo ard g ene -k bu6 options summary: manual duty mode 60 optimal default, failsafe default manual mode fan control, user can write expected duty cycle (pwm fan type) 1-100
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Chapter 3 – ami bios setup 61 3.5 ” s ub co mp act bo ard g ene -k bu6 options summary: monitor thermal cpu temperature(dts) optimal default, failsafe default chassis temperature(cpu) chassis temperature(pch) select monitor thermal source temperature of start 30 optimal default, failsafe default tem...
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Chapter 3 – ami bios setup 62 3.5 ” s ub co mp act bo ard g ene -k bu6 slope (pwm) 0 (pwm) 1 (pwm) optimal default, failsafe default 2 (pwm) 4 (pwm) 8 (pwm) 16 (pwm) 32 (pwm) 64 (pwm) slope (pwm).
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Chapter 3 – ami bios setup 63 3.5 ” s ub co mp act bo ard g ene -k bu6 3.8 sio configuration.
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Chapter 3 – ami bios setup 64 3.5 ” s ub co mp act bo ard g ene -k bu6 3.9 serial port configuration options summary: use this device disabled enabled optimal default, failsafe default en/disable serial port (com) possible: use automatic settings optimal default, failsafe default io=3f8; irq=4; io=2...
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Chapter 3 – ami bios setup 65 3.5 ” s ub co mp act bo ard g ene -k bu6 3.10 serial port configuration options summary: use this device disabled enabled optimal default, failsafe default en/disable serial port (com) possible: use automatic settings optimal default, failsafe default io=2f8; irq=3; io=...
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Chapter 3 – ami bios setup 66 3.5 ” s ub co mp act bo ard g ene -k bu6 3.11 serial port configuration options summary: use this device disabled enabled optimal default, failsafe default en/disable serial port (com) possible: use automatic settings optimal default, failsafe default io=3e8; irq=11; io...
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Chapter 3 – ami bios setup 67 3.5 ” s ub co mp act bo ard g ene -k bu6 3.12 serial port configuration options summary: use this device disabled enabled optimal default, failsafe default en/disable serial port (com) possible: use automatic settings optimal default, failsafe default io=2e8; irq=11; io...
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Chapter 3 – ami bios setup 68 3.5 ” s ub co mp act bo ard g ene -k bu6 3.13 usb configuration options summary: legacy usb support enabled optimal default, failsafe default disabled auto enables bios support for legacy usb support. When enabled, usb can be functional in legacy environment like dos. A...
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Chapter 3 – ami bios setup 69 3.5 ” s ub co mp act bo ard g ene -k bu6 3.14 digital io port configuration options summary: dio port* output input set dio as input or output output level high optimal default, failsafe default low set output level when dio pin is output.
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Chapter 3 – ami bios setup 70 3.5 ” s ub co mp act bo ard g ene -k bu6 3.15 power management options summary: power mode atx type optimal default, failsafe default at type select system power mode. Power saving(erp) control disabled optimal default, failsafe default enabled configure power mode for ...
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Chapter 3 – ami bios setup 71 3.5 ” s ub co mp act bo ard g ene -k bu6 resume from pcie disabled enabled optimal default, failsafe default enable/disable resume from pcie resume from lan/ri disabled enabled optimal default, failsafe default enable/disable resume from lan/ri.
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Chapter 3 – ami bios setup 72 3.5 ” s ub co mp act bo ard g ene -k bu6 3.16 compatibility support module configuration boot option filter uefi and legacy optimal default, failsafe default legacy only uefi only this option controls legacy/uefi roms priority storage do not launch uefi legacy optimal d...
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Chapter 3 – ami bios setup 73 3.5 ” s ub co mp act bo ard g ene -k bu6 3.17 setup submenu: chipset.
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Chapter 3 – ami bios setup 74 3.5 ” s ub co mp act bo ard g ene -k bu6 3.18 system agent (sa) configuration options summary: max tolud dynamic optimal default, failsafe default 1 gb 1.25 gb 1.5 gb 1.75 gb 2 gb 2.25 gb 2.5 gb 2.75 gb 3 gb 3.25 gb 3.5 gb maximum value of tolud dynamic assignment would...
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Chapter 3 – ami bios setup 75 3.5 ” s ub co mp act bo ard g ene -k bu6 3.19 graphics configuration options summary: primary igfx boot display vbios default optimal default, failsafe default dvi crt/dp lvds select the video device which will be activated during post. This has no effect if external gr...
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Chapter 3 – ami bios setup 76 3.5 ” s ub co mp act bo ard g ene -k bu6 3.20 lvds panel configuration lvds disabled enabled optimal default, failsafe default enable/disabled this panel. Lvds panel type 640x480,18bit,60hz 800x480,18bit,60hz 800x600,18bit,60hz 1024x600,18bit,60hz 1024x768,18bit,60hz op...
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Chapter 3 – ami bios setup 77 3.5 ” s ub co mp act bo ard g ene -k bu6 color depth 18-bit optimal default, failsafe default 24-bit 36-bit 48-bit select panel type backlight type normal optimal default, failsafe default inverted select backlight control signal type backlight level 0% 10% 20% 30% 40% ...
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Chapter 3 – ami bios setup 78 3.5 ” s ub co mp act bo ard g ene -k bu6 3.21 pch-io configuration options summary: hd audio disabled enabled optimal default, failsafe default control detection of the hd-audio device. Disabled = hda will be unconditionally disabled enabled = hda will be unconditionall...
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Chapter 3 – ami bios setup 79 3.5 ” s ub co mp act bo ard g ene -k bu6 3.22 security change user/supervisor password you can install a supervisor password, and if you install a supervisor password, you can then install a user password. A user password does not provide access to many of the features ...
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Chapter 3 – ami bios setup 80 3.5 ” s ub co mp act bo ard g ene -k bu6 3.23 setup submenu: boot options summary: quiet boot disabled enabled optimal default, failsafe default en/disable showing boot logo. Launch pxe oprom disabled optimal default, failsafe default enabled controls the execution of u...
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Chapter 3 – ami bios setup 81 3.5 ” s ub co mp act bo ard g ene -k bu6 bbs priorities.
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Chapter 3 – ami bios setup 82 3.5 ” s ub co mp act bo ard g ene -k bu6 3.242 setup submenu: exit.
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3.5 ” s ub co mp act bo ard g ene -kb u6 chapter 4 chapter 4 – drivers installation.
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Chapter 4 – driver installation 84 3.5 ” s ub co mp act bo ard g ene -k bu6 4.1 product cd/dvd the gene-sku6 comes with a product dvd that contains all the drivers and utilities you need to setup your product. Insert the dvd and follow the steps in the autorun program to install the drivers. In case...
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Chapter 4 – driver installation 85 3.5 ” s ub co mp act bo ard g ene -k bu6 3. Follow the instructions 4. Drivers will be installed automatically step 5 – install usb 3.0 driver (windows 7 only) 1. Open thestep5 - usb3.0 folder followed by setup.Exe 2. Follow the instructions 3. Drivers will be inst...
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Chapter 4 – driver installation 86 3.5 ” s ub co mp act bo ard g ene -k bu6 step 8 – install serial port drivers for windows 7: 1. Change user account control settings to never notify 2. Reboot and log in as administrator.
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Chapter 4 – driver installation 87 3.5 ” s ub co mp act bo ard g ene -k bu6 3. Run patch.Bat as administrator for windows 8/10: 1. Click on the step8 - serial port driver (optional) folder and select your os 2. Open the setup.Exe file in the folder 3. Follow the instructions 4. Drivers will be insta...
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Chapter 4 – driver installation 88 3.5 ” s ub co mp act bo ard g ene -k bu6 4.2 note on ehci with the ehci controller no longer available on the 6th gen intel ® core™ platforms, it is recommended to install windows 7 through a sata bus, eg sata dvd-rom, or patch the xhci driver onto an installation ...
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3.5 ” s ub co mp act bo ard g ene -kb u6 appendix a appendix a - watchdog timer programming.
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Appendix a – watchdog timer programming 90 3.5 ” s ub co mp act bo ard g ene -k bu6 a.1 watchdog timer registers table 1 : watch dog relative io address default value note i/o base address 0xa10 i/o base address for watchdog operation. This address is assigned by sio ldn7, register 0x60-0x61. Table ...
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Appendix a – watchdog timer programming 91 3.5 ” s ub co mp act bo ard g ene -k bu6 a.2 watchdog sample program ****************************************************************************** // wdt i/o operation relative definition (please reference to table 1) #define wdtaddr 0x510 // wdt i/o base ...
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Appendix a – watchdog timer programming 92 3.5 ” s ub co mp act bo ard g ene -k bu6 void aaeonwdtenable (){ wdtenabledisable(1); } // procedure : aaeonwdtconfig void aaeonwdtconfig (byte counter, boolean unit){ // disable wdt counting wdtenabledisable(0); // clear watchdog timeout status wdtcleartim...
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Appendix a – watchdog timer programming 93 3.5 ” s ub co mp act bo ard g ene -k bu6 void wdtwritebyte(byte register, byte value){ iowritebyte(wdtaddr+register, value); } byte wdtreadbyte(byte register){ return ioreadbyte(wdtaddr+register); } void wdtsetbit(byte register, byte bit, byte val){ byte tm...
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3.5 ” s ub co mp act bo ard g ene -kb u6 appendix b appendix b - i/o information.
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Appendix b – i/o information 95 3.5 ” s ub co mp act bo ard g ene -k bu6 b.1 i/o address map.
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Appendix b – i/o information 96 3.5 ” s ub co mp act bo ard g ene -k bu6.
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Appendix b – i/o information 97 3.5 ” s ub co mp act bo ard g ene -k bu6 b.2 memory address map.
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Appendix b – i/o information 98 3.5 ” s ub co mp act bo ard g ene -k bu6.
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Appendix b – i/o information 99 3.5 ” s ub co mp act bo ard g ene -k bu6 b.3 irq mapping chart.
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Appendix b – i/o information 100 3.5 ” s ub co mp act bo ard g ene -k bu6.
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3.5 ” s ub co mp act bo ard g ene -kb u6 appendix c appendix c – electrical specifications for i/o ports.
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Appendix c – electrical specifications for i/o ports 102 3.5 ” s ub co mp act bo ard g ene -k bu6 c.1 electrical specifications for i/o ports i/o reference signal name rate output dvi port cn3 +5v +5v/1a (reserved) dp port cn5 +3.3v +3.3v/1a lvds port cn6 +3.3v/+5v +3.3v/2a or +5v/2a lvds port inver...
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Appendix c – electrical specifications for i/o ports 103 3.5 ” s ub co mp act bo ard g ene -k bu6 audio i/o port cn22 +5v +5v/1a digital io port cn24 +5v +5v/1a com port 4 cn26 +5v/+12v +5v/0.5a or +12v/0.5a com port 2 cn27 +5v/+12v +5v/0.5a or +12v/0.5a com port 3 cn28 +5v/+12v +5v/0.5a or +12v/0.5...
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3.5 ” s ub co mp act bo ard g ene -kb u6 appendix d appendix d – digital i/o ports.
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Appendix d – digital i/o ports 105 3.5 ” s ub co mp act bo ard g ene -k bu6 d.1 electrical specifications for digital i/o ports table 1 : digital input/output pin electrical specification pin type input threshold voltage output voltage note low high low high dio0 i/o 0.8 2.0 0 5 dio1 i/o 0.8 2.0 0 5...
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Appendix d – digital i/o ports 106 3.5 ” s ub co mp act bo ard g ene -k bu6 d.2 di/o programming gene-sku6 utilizes fintek f81866d chipset as its digital i/o controller. Below are the procedures to complete its configuration and the aaeon initial di/o program is also attached, based on which you can...
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Appendix d – digital i/o ports 107 3.5 ” s ub co mp act bo ard g ene -k bu6 d.3 digital i/o register table 2 : superio relative register table default value note index 0x2e sio mb pnp mode index register 0x2e or 0x4e data 0x2f) sio mb pnp mode data register 0x2f or 0x4f table 3 : digital input/outpu...
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Appendix d – digital i/o ports 108 3.5 ” s ub co mp act bo ard g ene -k bu6 d.4 digital i/o sample program ************************************************************************** // superio relative definition (please reference to table 2) #define sioindex 0x2e #define siodata 0x2f #define dioldn...
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Appendix d – digital i/o ports 109 3.5 ” s ub co mp act bo ard g ene -k bu6 // input : // example, set digital i/o pin 2 to high level aaeonsetoutputlevel(pin2bit, pinhigh); } ************************************************************************** *************************************************...
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Appendix d – digital i/o ports 110 3.5 ” s ub co mp act bo ard g ene -k bu6 iowritebyte(siodata, tmpvalue); sioexitmbpnpmode(); } void siobyteset(byte ldn, byte register, byte value){ sioentermbpnpmode(); sioselectldn(ldn); iowritebyte(sioindex, register); iowritebyte(siodata, value); sioexitmbpnpmo...
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3.5 ” s ub co mp act bo ard g ene -kb u6 appendix e appendix e – list of mating connectors and cables.
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Appendix e – mating connectors and cables 112 3.5 ” s ub co mp act bo ard g ene -k bu6 e.1 electrical specifications for i/o ports connector label function mating connector available cable cable p/n vendor model no. Cn1 external rtc connector molex 51021-0200 battery cable 175011901c cn6 lvds connec...
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Appendix e – mating connectors and cables 113 3.5 ” s ub co mp act bo ard g ene -k bu6 cn24 digital i/o connector neltron 2026b-10 n/a n/a cn25 com port 1 connector molex 51021-0900 serial port cable 1701090150 cn26 com port 4 connector molex 51021-0900 serial port cable 1701090150 cn27 com port 2 c...
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Appendix e – mating connectors and cables 114 3.5 ” s ub co mp act bo ard g ene -k bu6 cn36 cpu fan connector molex 22-01-2035 n/a n/a.