Cadence CADENCE INCYTE CHIP ESTIMATOR Datasheet - page 2
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www.cadence.com
CADENCE INCYTE CHIP ESTIMATOR
BENEFITS
• Improves predictability of success
- Closes early on a specification that
best balances size, power, and costs
- Uses real IP, process, and architecture
data to determine specifications
• Addresses the impact of power compre
-
hensively
- Estimates power at the architectural
level
- Plans block-level and chip-level power
strategies
- Models different power modes
- Generates a Common Power Format
(CPF) file to drive downstream imple
-
mentation
• Provides access to ChipEstimate.com,
the foremost IP ecosystem
- 7,000+ IP components from 200+ IP
suppliers and foundries
- Compares digital, analog, and
mixed-signal IP in the context of your
design, before contacting multiple IP
providers directly
- Provides a wide set of design options
to explore
• Quantifies the cost impact of chip
architecture and implementation
decisions
- Draws on built-in economic and yield
data
• Reduces implementation risk
- Enables early planning followed by a
convergent flow
- Passes architecture and library data
forward to drive implementation
tools
- Feeds back implemented block data
to refine accuracy of the model and
to drive in-project decisions
• Ease-of-use enables collaboration
- Promotes communication among
business and technical teams
- Starts with early planning and con-
tinues throughout the course of the
project
FEATURES
Cadence InCyte Chip Estimator operates
in a client-server model and has the
libraries you need already built-in. The
client is the InCyte Chip Estimator
application on your Windows or Linux
desktop. The server brings that same
IP catalog and foundry libraries from
ChipEstimate.com directly into the client
application. InCyte Chip Estimator is
available in several different configu-
rations.
INCYTE CHIP ESTIMATOR L
For accurate technical estimation of
design size and power, InCyte Chip
Estimator L combines foundry-specific
models with the ChipEstimate.com IP
portal inside an easy-to-use estimation
environment.
• Access the ChipEstimate.com IP catalog
(built into the software)
• Select foundry-specific foundation
libraries of standard cells, I/Os, and
memories.
• Select a specific foundry library at a
specific process node
• Filter the built-in IP catalog to show IP
suitable for that node
• Define custom IP macros
• Estimate design size
• Estimate design power (dynamic and
leakage)
• Compare size, power, and performance
of multiple designs or design variations
• Estimate performance achievability in
specific manufacturing processes with
specific IP components
• Create and edit a block diagram of the
design using drag-and-drop for blocks
and drawing tools for connectivity
• Edit the floorplan view to analyze
impact of movement and rotation on
size, power, performance, and cost
• Export the design intent downstream to
synthesis, low-power verification, and
physical implementation: DEF, LEF,
high-level Verilog
®
, CPF, SDC, synthesis
scripts, implementation scripts, and
compiled memory scripts
INCYTE CHIP ESTIMATOR XL
InCyte Chip Estimator XL adds advanced
analysis capabilities, including economic
analysis, power profile analysis, and
power management, on top of the core
chip planning features of the L edition.
• View economic lifecycle tables and
graphs that offer cost analysis of yield-
affected wafers, packaging, test and
assembly, and non-recurring
engineering (NRE) charges
• Generate complete IC economic
analysis reports and budgetary quotes
• Create power profiles with various
modes, assign percent active time for
modes
• Easily include advanced power
management techniques (power
shutoff, multi-supply/multi-voltage,
clock gating) while measuring the size
and power impact of these techniques
• Automatically takes into account the
cost overhead of advanced low-power
techniques
• Visualize the impact of techniques on
dynamic power, leakage power, size,
and performance
• Interfaces bi-directionally with Cadence
Encounter
®
RTL Compiler synthesis
solution
- Feeds forward SDC, module defini-
tions, floorplan hints, and synthesis
scripts
- Feeds back synthesized gate counts
of random logic blocks and compares
to earlier estimates