Cadence VIRTUOSO LAYOUT MIGRATE Datasheet - page 3
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VIrTuoSo LAyouT MIgrATE
Virtuoso environment
(see Figure 5)
. With
this menu system, the user can configure,
run, and evaluate the results. The configu-
rations menu allows the user to define an
optimization flow consisting of preprocess,
optimization, and postprocess commands.
After a flow has been defined, the user
needs only ”one button“ to optimize or
migrate similar designs. A high degree
of control within the familiar Virtuoso
environment allows the user to freeze
parts of the layout, relax a set of design
rules, and set the amount of change
introduced to achieve a design-rule-correct
layout
(see Figure 6)
.
ecO SUppORT WITh vIRTUOSO
SchemaTIc edITOR and neTlIST-
BaSed devIce SIZeS
When using Virtuoso Layout Migrate in
the ECo process, the user can update
device sizes from within the schematics of
Virtuoso Schematic Editor, and Virtuoso
Layout Migrate will enforce the new
device sizes while adhering to the design
rules and maintaining circuit connectivity.
Virtuoso Layout Migrate can also read in
a SPICE netlist, which is then used during
layout optimization. The transistor sizes
within the layout are matched to the
transistor sizes within the SPICE netlist.
This device-matching technology works
hierarchically and supports mismatched
netlist/layout hierarchies.
SpecIfIcaTIOnS
laYOUT pROceSS and
deSIgn RUle mIgRaTIOn
•
Hierarchical two-dimensional optimization
•
Structure preservation including paths,
MPPs, symbolics, connectivity, and
properties
•
Pcell substitution to replace Pcells
or update their parameters during
migration
•
Menu-driven setup and flow configura-
tion system
•
ECo support with Virtuoso Schematic
Editor and netlist-based device sizes
Figure 4:
Example of fast layout migration showing the ability to handle complex design rules
DEF: 0.25 µm
45˚ angles in gates
and routing
Migrate to 0.15 µm
Remove 45˚ angles
Optimize contacts
Migrate to 0.15 µm
Single pass
Cadence 7105_Figure 4
Figure 5:
Easy-to-use menu-driven setup and flow configuration system—the fast track to productivity
Figure 6:
Technology files are easy to understand and write—this example shows how to implement a gate spacing rule