Cadence VIRTUOSO LAYOUT SUITE XL Datasheet - page 2
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VirTuoSo LAyouT SuiTE XL
Backed by the largest number of process
design kits (PDKs) available from the
world’s leading foundries—for process
nodes from 0.5um to 28nm, and
everything in between—the Virtuoso
custom design platform is built on the
openAccess database, engineered by
Cadence for industry-wide interoperability.
The Virtuoso custom design platform
accelerates the design of custom iCs
across various process nodes. By selectively
automating aspects of custom analog
design and providing advanced technologies
integrated on a common database, it allows
engineers to focus on precision-crafting
their designs—without sacrificing creativity
to repetitive manual tasks.
VIRTUOSO LAYOUT
SUITE
The Virtuoso Layout Suite comprises three
tiers of increasing layout automation and
designer productivity. Virtuoso Layout
Suite L is the basic design creation and
implementation environment. Virtuoso
Layout Suite XL is an extension to the
L configuration, designed with layout
productivity as its focus. And finally,
Virtuoso Layout Suite GXL is a robust set
of advanced automated design tools that
satisfy demanding physical design tasks
such as automatic placement, routing,
and optimization.
VIRTUOSO LAYOUT
SUITE XL
Virtuoso Layout Suite XL is the
connectivity- and constraint-driven layout
environment of the industry-standard
Virtuoso custom design platform. it
supports the physical implementation of
analog, custom-digital, and mixed-signal
designs at the device, cell, block, and chip
level. Virtuoso Layout Suite XL accelerates
custom layout with a comprehensive
set of user-configurable and easy-to-use
pure polygon layout features within a
fully hierarchical environment. Additional
acceleration is provided through optional
parameterized cells (Pcells) and SKiLL, the
powerful scripting language that provides
direct database access, tool configuration,
and interoperability with other tools.
Virtuoso Layout Suite XL has set the
standard for layout productivity and
changed the way custom block authoring
is done. it is driven by a connectivity
source from Virtuoso Schematic Editor
or a netlist source such as CDL or SPiCE.
An LVS-correct layout can then be
created in real time, promoting correct-
by-construction layout, improving
productivity, and reducing verification
time. Additionally, tedious design tasks
such as device generation, placement, and
routing are automated. Schematic and
layout can be cross-probed to highlight
instances and devices and quickly identify
unconnected nets.
in Virtuoso Layout Suite XL, a new
incremental connectivity-driven binding
technology has been introduced. This
approach is far superior to traditional
name-based schematic-to-layout binders,
which had severe limitations when
supporting schematic-to-layout name
mismatches. The connectivity-driven
binder enables better support of legacy
layouts that have name mismatches, and
also improves handling of engineering
change orders (ECos) that involve
renaming instances and terminals in the
layout. The incremental nature of the
connectivity binder also greatly improves
the performance of a connectivity-driven
layout flow.
Virtuoso Layout Suite XL is also built
on the Virtuoso platform’s common
constraint system to greatly improve
productivity. Topological constraints,
electrical constraints, and/or design-rule–
specific constraints can be specified and
managed in Virtuoso Schematic Editor,
Virtuoso Analog Design Environment,
or Virtuoso Layout Suite XL. Simply set
the constraints in Virtuoso Schematic
Editor XL and Virtuoso Layout Suite XL
can be easily configured to either enforce
the constrains while generating layout
or automatically flag and log constraint
violations that can later be resolved in
subsequent design reviews.
This common constraint system, at the
core of the Virtuoso platform, ensures
correct-by-construction layout, improved
productivity, and fewer physical verification
iterations. Constraints and connectivity-
driven layout are the fundamental building
blocks for generating first-time correct and
optimal silicon.
BENEFITS
• Includes all Virtuoso Layout Suite L
features (see respective datasheet)
• Connectivity- and constraint-driven
environment tackles challenging next-
generation design problems and speeds
the design cycle
• Constraint-aware and design-rule–
driven editing enable correct-by-
construction layout techniques that
improve designer productivity
• High-performance connectivity-driven
binder is ideal for designs that have
schematic-to-layout name mismatches
• Can be Virtuoso Schematic Editor-
driven or netlist-driven
• Modern, redesigned, common user
interface focuses on ease-of-use and
intuitive layout
• Eases creation and navigation of
complex designs with unlimited
hierarchy support coupled with a
multi-window, multi-tabbed editing
environment
• Offers interactive Pick-From-Schematic
or automated Gen-From-Source device
generation
• Automates SKILL Pcell-based device
editing including abutment, pin
permutation, folding, chaining, and
cloning
• Accelerates layout entry with easy-to-use
and easily accessed editing functions
• Assisted wire editing functionality
targets designer productivity when
creating custom interconnect
• Offers a menu-driven or programmable
Multi-Part Path (MPP) feature for
guardrings and slotting
• Advanced cloning capabilities enable
generation and editing of complex
repeated layout patterns