Daewoo DVDP485 Service Manual - page 21
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SA[7:0]/GPA[15:
8]
I/O
When LATS=1, SA[7:0] input is specified, representing the low byte
address bus, input.
When LATS=0, two options: one is SA[7:0] output of the low byte
address latched from SAD[7:0] input by ALE; the other is GPA[15:8],
general purpose IO bus A bits[15:8], bi-directional; SA[7:0] output is
default.
SA[15:8]
I
The high byte of the address bus.
INTS#
O
Interrupt request of servo, active low.
INTM#
O
Interrupt request of AV decoder, active low.
WR#
I
Write enable, active low.
RD#
I
Read enable, active low.
4.3 SDRAM Interface Signals
Pin name
Type
Description
MA[11:0]
O
SDRAM Address bus output
BS[1:0]
O
SDRAM Bank Select output
MD[15:0]
I/O
SDRAM Data bus keeps as input state except for WRITE operation
SDCLKO
O
SDRAM Clock Output
SDCLKI
I
SDRAM Clock Input
SCS#
O
SDRAM Chip Select output, active Low
RAS#
O
Row Address Strobe output, active Low
CAS#
O
Column Address Strobe output, active Low
SWE#
O
Write Enable output, active Low
DQM
O
SDRAM data mask, active HIGH