Fairchild FEB146-001 User manual - page 6
© 2005 Fairchild Semiconductor
Page 6
of 9
Rev 1.0 December 2005
www.fairchildsemi.com
4.4 Troubleshooting
• The µSerDes Evaluation boards and the µSerDes ICs are both completely tested and should not
cause problems.
• If deserializer output is not correct, ensure that the proper power-up sequence is being used.
For correct operation, power up the devices first, then provide data and clock signals.
• To effectively troubleshoot, the data and clock paths may be probed on either side of the flex.
Be aware when probing these locations, as the signals are LVDS by design, meaning the peak to
peak voltage will be approximately 200mV, with slightly less than 1.0 Volt bias.
• True differential probes must be used to examine the LVDS signals. Using a terminated oscilloscope
with a probe ground to one side of an LVDS signal, will force the 1.0 Volt bias to ground, resulting
in a very incorrect signal. Alternatively, a board ground may be offset to accommodate the ground of
an oscilloscope. Contact your Fairchild µSerDes representative for further assistance with this.
• Be aware with the FIN24A Serializer that input data Terminal 21 is output from Terminal 23 on the
Deserializer, and Serializer input data Terminal 22 is output at the Deserializer on Terminal 24.
• Be aware that the FIN24 has a set frequency range, and that S1 and S2 control the direction of data
bits[21:24].
• A careful examination of the serial clock will result in periodic discontinuities. This is normal and
represents the imbedded word boundary.
• For additional information pertaining to µSerDes, please see Application Note
AN-5058 µSerDes
Family Frequently Asked Questions (FAQ)
and the corresponding device data sheets.