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A2 Processor

User’s Manual

for Blue Gene/Q

Note: This document and the information it contains are provided on an as-is basis.

There is no plan for providing for future updates and corrections to this document.

October 23, 2012

Version 1.3

Title Page

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Summary of A2

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A2 processor user’s manual for blue gene/q note: this document and the information it contains are provided on an as-is basis. There is no plan for providing for future updates and corrections to this document. October 23, 2012 version 1.3 title page.
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® copyright and disclaimer © copyright international business machines corporation 2010, 2012 printed in the united states of america october 2012 ibm, the ibm logo, and ibm.Com are trademarks or registered trademarks of international business machines corp., registered in many jurisdictions worldwi...
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User’s manual a2 processor version 1.3 october 23, 2012 contents page 3 of 864 contents list of figures ............................................................................................................... 21 list of tables .....................................................................
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User’s manual a2 processor contents page 4 of 864 version 1.3 october 23, 2012 2. Cpu programming model ......................................................................................... 61 2.1 logical partitioning .................................................................................
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User’s manual a2 processor version 1.3 october 23, 2012 contents page 5 of 864 2.6 instruction categories ..................................................................................................................... 86 2.7 instruction classes ....................................................
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User’s manual a2 processor contents page 6 of 864 version 1.3 october 23, 2012 2.10.2.3 carry (ca) field .......................................................................................................... 112 2.10.2.4 transfer byte count (tbc) field ..............................................
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User’s manual a2 processor version 1.3 october 23, 2012 contents page 7 of 864 3.6.2 load and store instructions ................................................................................................. 145 3.6.3 floating-point store instructions ................................................
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User’s manual a2 processor contents page 8 of 864 version 1.3 october 23, 2012 5.5.3.6 data cache disable ...................................................................................................... 183 6. Memory management .....................................................................
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User’s manual a2 processor version 1.3 october 23, 2012 contents page 9 of 864 6.11.2 32-bit mode tlb search instruction (tlbsx[.]) ................................................................. 225 6.11.3 32-bit mode tlb search and reserve instruction (tlbsrx.) .....................................
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User’s manual a2 processor contents page 10 of 864 version 1.3 october 23, 2012 6.17.27 logical page exception register upper (lperu) ........................................................... 274 6.17.28 mas register update summary .....................................................................
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User’s manual a2 processor version 1.3 october 23, 2012 contents page 11 of 864 7.6.8 floating-point unavailable interrupt .................................................................................... 342 7.6.9 system call interrupt ...............................................................
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User’s manual a2 processor contents page 12 of 864 version 1.3 october 23, 2012 8.4.1 invalid operation exception ................................................................................................. 375 8.4.1.1 action ........................................................................
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User’s manual a2 processor version 1.3 october 23, 2012 contents page 13 of 864 10.4.2.3 dac debug events applied to instructions that result in multiple storage accesses 407 10.4.2.4 dac debug events applied to various instruction types ......................................... 408 10.4.3 data valu...
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User’s manual a2 processor contents page 14 of 864 version 1.3 october 23, 2012 10.11 pc configuration register 0 (pccr0) ...................................................................................... 444 10.12 trace and trigger bus ..............................................................
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User’s manual a2 processor version 1.3 october 23, 2012 contents page 15 of 864 12.3.1 erat read entry (eratre) ................................................................................................. 496 12.3.2 erat write entry (eratwe) ........................................................
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User’s manual a2 processor contents page 16 of 864 version 1.3 october 23, 2012 14.5.15 dac4 - data address compare 4 .................................................................................... 557 14.5.16 dbcr0 - debug control register 0 .......................................................
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User’s manual a2 processor version 1.3 october 23, 2012 contents page 17 of 864 14.5.65 lpidr - logical partition id register .............................................................................. 616 14.5.66 lr - link register ...................................................................
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User’s manual a2 processor contents page 18 of 864 version 1.3 october 23, 2012 14.5.115 tenc - thread enable clear register .......................................................................... 675 14.5.116 tens - thread enable set register ........................................................
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User’s manual a2 processor version 1.3 october 23, 2012 contents page 19 of 864 appendix a. Processor instruction summary ......................................................... 737 a.1 instruction formats ...............................................................................................
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User’s manual a2 processor contents page 20 of 864 version 1.3 october 23, 2012 d.4.11 tlb management instruction dependencies .................................................................... 845 d.4.12 processor control instruction operation ........................................................
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User’s manual a2 processor version 1.3 october 23, 2012 list of figures page 21 of 864 list of figures figure 1-1. A2 core organization ............................................................................................................. 50 figure 1-2. A2 processor block diagram ...............
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User’s manual a2 processor list of figures page 22 of 864 version 1.3 october 23, 2012.
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User’s manual a2 processor version 1.3 october 23, 2012 list of tables page 23 of 864 list of tables table 2-1. Data operand definitions ....................................................................................................... 63 table 2-2. Alignment effects for storage access instruct...
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User’s manual a2 processor list of tables page 24 of 864 version 1.3 october 23, 2012 table 2-39. Xer[ca] updating instructions ............................................................................................111 table 2-40. Sprg0 register ....................................................
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User’s manual a2 processor version 1.3 october 23, 2012 list of tables page 25 of 864 table 4-2. Shadow tlb array entry initialization .................................................................................. 158 table 5-1. Data cache array organization ........................................
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User’s manual a2 processor list of tables page 26 of 864 version 1.3 october 23, 2012 table 10-1. Pccr0[dba] (debug action) definition per thread ............................................................400 table 10-2. Debug events ....................................................................
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User’s manual a2 processor version 1.3 october 23, 2012 list of tables page 27 of 864 table 15-17. Ram data register high (ramdh) ...................................................................................... 726 table 15-18. Ram data register low (ramdl) .......................................
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User’s manual a2 processor list of tables page 28 of 864 version 1.3 october 23, 2012.
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User’s manual a2 processor version 1.3 october 23, 2012 revision log page 29 of 864 revision log each release of this document supersedes all previously released versions. The revision log lists all signifi- cant changes made to the document since its initial release. In the rest of the document, ch...
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User’s manual a2 processor revision log page 30 of 864 version 1.3 october 23, 2012.
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User’s manual a2 processor version 1.3 october 23, 2012 about this book page 31 of 864 about this book this user’s manual provides the architectural overview, programming model, and detailed information about the instruction set, registers, and other facilities of the ibm® power isa a2 64-bit embedd...
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User’s manual a2 processor about this book page 32 of 864 version 1.3 october 23, 2012 • debug facilities on page 399 • performance events and event selection on page 449 • implementation dependent instructions on page 481 • power management methods on page 525 • register summary on page 529 • scom ...
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User’s manual a2 processor version 1.3 october 23, 2012 about this book page 33 of 864 • the symbol  is used to describe the concatenation of two values. For example, 0b010  0b111 is the same as 0b010111. • x n means x raised to the n power. • n x means the replication of x, n times (that is, x ...
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User’s manual a2 processor about this book page 34 of 864 version 1.3 october 23, 2012.
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User’s manual a2 processor version 1.3 october 23, 2012 list of acronyms and abbreviations page 35 of 864 list of acronyms and abbreviations abist automatic built-in self test alu arithmetic logic unit ansi american national standards institute are auto-reload enable as address space atb alternate t...
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User’s manual a2 processor list of acronyms and abbreviations page 36 of 864 version 1.3 october 23, 2012 csb control status block csi context synchronizing instruction dac data address compare dba debug action dbell doorbell interrupt dcc data cache controller dch data channel dci data cache invali...
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User’s manual a2 processor version 1.3 october 23, 2012 list of acronyms and abbreviations page 37 of 864 e.Pt embedded.Page table category e.Twc embedded.Tlb write conditional category ea effective address ecc error-correcting code ecl embedded cache locking category edm external debug mode een err...
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User’s manual a2 processor list of acronyms and abbreviations page 38 of 864 version 1.3 october 23, 2012 fu floating-point unit fxu fixed-point unit g guarded gb gigabyte gb/sec gigabytes per second ghz gigahertz gpr general purpose register gs guest state htm hardware trace macro hwt hardware tabl...
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User’s manual a2 processor version 1.3 october 23, 2012 list of acronyms and abbreviations page 39 of 864 is instruction fetch address space or invalidation select isa instruction set architecture isi instruction storage interrupt iu instruction unit iu0 - iu6 instruction unit pipeline stage ivc ins...
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User’s manual a2 processor list of acronyms and abbreviations page 40 of 864 version 1.3 october 23, 2012 mas mmu assist mav mmu architecture version mb megabyte mesi modified, exclusive, shared, invalid mhz megahertz mmc memory coherence category mmu memory management unit msb most significant byte...
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User’s manual a2 processor version 1.3 october 23, 2012 list of acronyms and abbreviations page 41 of 864 qnan quiet nan ra real address raw read-after-write ree reference exception enable ret return risc reduced instruction set computing rmt replacement management table ro read only rom read-only m...
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User’s manual a2 processor list of acronyms and abbreviations page 42 of 864 version 1.3 october 23, 2012 sprn special purpose register number sprg special purpose registers general sr supervisor mode read access sram static random access memory stm stream category sw supervisor mode write access sx...
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User’s manual a2 processor version 1.3 october 23, 2012 list of acronyms and abbreviations page 43 of 864 ux underflow exception or user mode execution access v vector category v.Le little-endian category va virtual addresses vf virtualization fault vhdl very-high-speed integrated circuit (vhsic) ha...
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User’s manual a2 processor list of acronyms and abbreviations page 44 of 864 version 1.3 october 23, 2012.
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User’s manual a2 processor version 1.3 october 23, 2012 overview page 45 of 864 1. Overview the ibm power isa a2 64-bit embedded processor core is an implementation of the scalable and flexible power isa architecture. The a2 core implements four simultaneous threads of execution within the core. Eac...
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User’s manual a2 processor overview page 46 of 864 version 1.3 october 23, 2012 1.2 a2 core features the a2 core is a high-performance, low-power engine that implements the flexible and powerful power isa architecture. The a2 core contains a single-issue, in-order, pipelined processing unit, along w...
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User’s manual a2 processor version 1.3 october 23, 2012 overview page 47 of 864 • cache line locking supported • caches can be partitioned to provide separate regions for transient instructions and data • critical-word-first data access and forwarding • pseudo lru replacement policy • cache tags and...
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User’s manual a2 processor overview page 48 of 864 version 1.3 october 23, 2012 • timer facilities • 64-bit time base • decrementer with auto-reload capability • fixed interval timer (fit) • watchdog timer with critical interrupt and/or auto-reset • multiple core interfaces operating at core frequen...
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User’s manual a2 processor version 1.3 october 23, 2012 overview page 49 of 864 1.3 the a2 core as a power isa implementation the a2 core implements the full, 64-bit fixed-point power isa architecture. The a2 core fully complies with these architectural specifications. The core does not implement th...
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User’s manual a2 processor overview page 50 of 864 version 1.3 october 23, 2012 1.4.1 instruction unit the instruction unit of the a2 core fetches, decodes, and issues two instructions from different threads per cycle to any combination of the one execution pipeline and the axu interface (see sectio...
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User’s manual a2 processor version 1.3 october 23, 2012 overview page 51 of 864 1.4.2 execution unit the a2 core contains a single execution pipeline. The pipeline consists of seven stages and can access the 5-ported (three read, two write) gpr file. The pipeline handles all arithmetic, logical, bra...
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User’s manual a2 processor overview page 52 of 864 version 1.3 october 23, 2012 the dcc interfaces to the axu port to provide direct load/store access to the data cache for axu load and store operations. Such axu load and store instructions can access up to 32 bytes (a double quadword) in a single c...
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User’s manual a2 processor version 1.3 october 23, 2012 overview page 53 of 864 the establishment and replacement of tlb entries by simply not using indirect entries (that is, by using only direct ind = 0 entries). This gives system software significant flexibility in implementing a custom page repl...
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User’s manual a2 processor overview page 54 of 864 version 1.3 october 23, 2012 1.4.5 timers the a2 core contains a time base and three timers: a decrementer (dec), a fixed interval timer (fit), and a watchdog timer. The time base is a 64-bit counter that gets incremented at a frequency either equal...
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User’s manual a2 processor version 1.3 october 23, 2012 overview page 55 of 864 internal debug mode supports accessing architected processor resources, setting hardware and software breakpoints, and monitoring processor status. In internal debug mode, debug events can generate debug exceptions, whic...
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User’s manual a2 processor overview page 56 of 864 version 1.3 october 23, 2012 1.4.7.1 arithmetic and load/store pipelines the a2 core has a single execution pipeline. The pipeline handles all computational instructions and reads from and writes to the fprs, floating-point status and control regist...
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User’s manual a2 processor version 1.3 october 23, 2012 overview page 57 of 864 1.4.8.1 ieee 754 compliance ieee 754 requires a certain set of operations to be included in any implementation that claims to be compliant. Such operations can be implemented in hardware, software, or a combination of th...
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User’s manual a2 processor overview page 58 of 864 version 1.3 october 23, 2012 1.4.10.2 clock and power management interface the cpm interface supports clock distribution and power management to reduce power consumption below the normal operational level. External logic is necessary for the sleep m...
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User’s manual a2 processor version 1.3 october 23, 2012 overview page 59 of 864 an entity outside the a2 core is expected to be able to queue the s store-type operations and give a pop indi- cation to the a2 core for each as it is processed and the queue entry is available. For an entity outside the...
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User’s manual a2 processor overview page 60 of 864 version 1.3 october 23, 2012.
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 61 of 864 2. Cpu programming model the programming model of the a2 core describes how the following features and operations of the core appear to programmers: • logical partitioning on page 61 • storage addressing on ...
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User’s manual a2 processor cpu programming model page 62 of 864 version 1.3 october 23, 2012 a processor is assigned to one partition at any given time. A processor can be assigned to any given partition without consideration of the physical configuration of the system (for example, shared registers...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 63 of 864 the alignment of the operand effective address of some storage access instructions might affect perfor- mance; in some cases, it might cause an alignment exception to occur. For such storage access instructi...
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User’s manual a2 processor cpu programming model page 64 of 864 version 1.3 october 23, 2012 cache management instructions access cache block operands; for the a2 core, the cache block size is 64 bytes. However, the effective addresses calculated by cache management instructions are not required to ...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 65 of 864 2.2.2.1 data storage addressing modes there are two data storage addressing modes supported by the a2 core: • base + displacement (d-mode) addressing mode: the 16-bit d field is sign-extended and added to th...
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User’s manual a2 processor cpu programming model page 66 of 864 version 1.3 october 23, 2012 2.2.3 byte ordering if scalars (individual data items and instructions) were indivisible, there would be no such concept as “byte ordering.” it is meaningless to consider the order of bits or groups of bits ...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 67 of 864 short e; /* 0x5152 halfword */ int f; /* 0x6162_6364 word */ } s; c structure mapping rules permit the use of padding (skipped bytes) to align scalars on desirable boundaries. The following structure mapping...
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User’s manual a2 processor cpu programming model page 68 of 864 version 1.3 october 23, 2012 consider the big-endian mapping of instruction p at address 0x00, where, for example, p = add r7, r7, r4: on the other hand, in a little-endian mapping the same instruction is arranged with the least-signifi...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 69 of 864 • for byte loads and stores, including strings, no reordering of bytes occurs regardless of byte ordering. • for halfword loads and stores, bytes are reversed within the halfword for one byte order with resp...
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User’s manual a2 processor cpu programming model page 70 of 864 version 1.3 october 23, 2012 2.3 multithreading the a2 core has four threads that allow simultaneous execution within the processor and can be viewed as a 4-way multiprocessor with shared dataflow. This gives the effective appearance of...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 71 of 864 2.3.1.3 guest processor identification register (gpir) the gpir is a register that identifies a specific instance of a processor thread for the guest operating system. The gpir is used to filter incoming pro...
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User’s manual a2 processor cpu programming model page 72 of 864 version 1.3 october 23, 2012 2.3.2.3 core configuration register 0 (ccr0) the ccr0 is used to disable or enable threads. When a thread is disabled by setting the ccr0 bit corre- sponding to the thread to 0, all instructions that have be...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 73 of 864 the ten is accessed by using two registers: tens and tenc. When tens is written, threads for which the corresponding bit in tens is 1 are enabled; threads for which the corresponding bit in tens is 0 are una...
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User’s manual a2 processor cpu programming model page 74 of 864 version 1.3 october 23, 2012 2.3.3 wake on interrupt the a2 core can be configured to wake on interrupts or other conditions, if the thread was disabled by a write to ccr0 or by executing a wait instruction. 2.3.3.1 core configuration r...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 75 of 864 2.3.4 thread priority thread priority can be changed by writing the ppr32 register, executing an or rx,rx,rx instruction, or by causing an interrupt. 2.3.4.1 program priority register (ppr32) the program pri...
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User’s manual a2 processor cpu programming model page 76 of 864 version 1.3 october 23, 2012 table 2-5. Program priority register (ppr32) table 2-3. Priority levels rx ppr32[pri] isa priority a2 hardware priority with iucr1[hipri] setting privileged 00 01 10 11 31 001 very low a2low a2low a2low a2lo...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 77 of 864 2.3.4.2 instruction unit configuration register 1 (iucr1) 2.3.5 resources shared between threads all architected states are duplicated for each thread except for logical partitioning and memory. This allows ...
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User’s manual a2 processor cpu programming model page 78 of 864 version 1.3 october 23, 2012 2.3.6.1 accessing shared resources when software executing in thread t n writes a new value in an spr (mtspr) that is shared with other threads, either of the following sequences of operations can be perform...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 79 of 864 2.3.8 pipeline sharing figure 2-1 shows the instruction flow for the a2 core. Figure 2-1. A2 core instruction unit.
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User’s manual a2 processor cpu programming model page 80 of 864 version 1.3 october 23, 2012 2.3.8.1 instruction cache the instruction cache is a shared resource between all threads where a single thread can be selected each cycle dependent upon the number of instructions currently contained within ...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 81 of 864 . 2.3.8.4 ram unit the ram unit allows an external command to be issued within a given thread’s instruction stream. This unit is a shared resource within a core in that only one thread can issue a ram comman...
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User’s manual a2 processor cpu programming model page 82 of 864 version 1.3 october 23, 2012 2.3.8.5 microcode unit the microcode unit (ucode) is partially shared and partially duplicated logic. The rom that contains the actual stream of instructions to be issued is a shared unit; however, each thre...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 83 of 864 perform the initial write to a register with reserved fields set to 0, and to perform all subsequent writes to the register using a read-modify-write strategy: read the register; use logical instructions to ...
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User’s manual a2 processor cpu programming model page 84 of 864 version 1.3 october 23, 2012 2.4.1 register mapping some special purpose register (spr) accesses in guest state are mapped to analogous registers for the guest state. This removes the requirement for the hypervisor software to handle em...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 85 of 864 sprs control the use of the debug facilities, timers, interrupts, memory management, caches, and other architected processor resources. Table 14-1 on page 530 shows the mnemonic, name, and number for each sp...
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User’s manual a2 processor cpu programming model page 86 of 864 version 1.3 october 23, 2012 2.6 instruction categories the power isa defines that each facility (including registers and fields therein) and instruction is in exactly one category. Table 2-7 indicate the categories that are implemented...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 87 of 864 2.7 instruction classes power isa architecture defines all instructions as falling into exactly one of the following three classes, as determined by the primary opcode (and the extended opcode, if any): 1. D...
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User’s manual a2 processor cpu programming model page 88 of 864 version 1.3 october 23, 2012 • perform the actions described in the rest of this document, if the instruction is recognized and supported by the implementation. The architected behavior might cause other exceptions. The a2 core recogniz...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 89 of 864 table 2-8 summarizes the a2 core instruction set by category. Instructions within each category are described in subsequent sections. 2.8.1 integer instructions integer instructions transfer data between mem...
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User’s manual a2 processor cpu programming model page 90 of 864 version 1.3 october 23, 2012 table 2-11 shows how operands are handled depending on alignment. Optimal performance and configura- tion is achieved when operands are aligned. Table 2-9. Integer storage access instructions loads stores by...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 91 of 864 2.8.1.2 integer arithmetic instructions arithmetic operations are performed on integer or ordinal operands stored in registers. Instructions that perform operations on two operands are defined in a 3-operand...
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User’s manual a2 processor cpu programming model page 92 of 864 version 1.3 october 23, 2012 2.8.1.3 integer logical instructions table 2-13 lists the integer logical instructions in the a2 core. See integer arithmetic instructions on page 91 for an explanation of the “[.]” syntax. 2.8.1.4 integer c...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 93 of 864 2.8.1.7 integer shift instructions table 2-17 lists the integer shift instructions in the a2 core. Note that the shift right algebraic instructions implicitly update the xer[ca] field. See integer arithmetic...
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User’s manual a2 processor cpu programming model page 94 of 864 version 1.3 october 23, 2012 2.8.2 branch instructions these instructions unconditionally or conditionally branch to an address. Conditional branch instructions can test condition codes set in the cr by a previous instruction and branch...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 95 of 864 2.8.3.2 register management instructions these instructions move data between the gprs and control registers in the a2 core. Table 2-22 lists the register management instructions in the a2 core. 2.8.3.3 syst...
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User’s manual a2 processor cpu programming model page 96 of 864 version 1.3 october 23, 2012 2.8.4.1 cache management instructions these instructions control the operation of the data and instruction caches. Instructions are provided to fill, flush, invalidate, or zero data cache blocks, where a blo...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 97 of 864 2.8.4.3 processor synchronization instruction the processor synchronization instruction, isync, forces the processor to complete all instructions preceding the isync before allowing any context changes as a ...
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User’s manual a2 processor cpu programming model page 98 of 864 version 1.3 october 23, 2012 2.8.4.6 wait instruction the wait instruction allows instruction fetching and execution to be suspended under certain conditions, depending on the value of the wc field. Wc = 11 is treated as a no-op instruc...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 99 of 864 2.9 branch processing the four branch instructions provided by a2 core are summarized in table 2.8.2 on page 94. The following sections provide additional information about branch addressing, instruction fie...
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User’s manual a2 processor cpu programming model page 100 of 864 version 1.3 october 23, 2012 the “a” and “t” bits of the bo field can be used by software to provide a hint about whether the branch is likely to be taken or is likely not to be taken, as shown in table 2-35. This implementation has dy...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 101 of 864 ultimately, the branch decoder generates four flags that will be used by the branch predictor at a later stage. These bits are appended to the original 32-bit instruction and are carried along as part of th...
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User’s manual a2 processor cpu programming model page 102 of 864 version 1.3 october 23, 2012 dynamic prediction begins when a valid instruction initiates a read access to the bht in iu0. The bht is indexed based on the current instruction ifar, and returns a 2-bit history value for that instruction...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 103 of 864 the effect could be minimized by increasing the depth of the bht (and the number of ifar bits used), but with an ifar that is potentially 62 bits long, aliasing can never be eliminated entirely. A depth of ...
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User’s manual a2 processor cpu programming model page 104 of 864 version 1.3 october 23, 2012 2.9.4.3 branch prioritization after all valid branch instructions within a cache line have been evaluated, they are prioritized in the order they occur. The first branch within a cache line to be evaluated ...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 105 of 864 shadow pointer. The shadow pointer becomes valid for predictions at this point because all branch instruc- tions that have not yet been resolved by the execution unit will be flushed with the rest of the pi...
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User’s manual a2 processor cpu programming model page 106 of 864 version 1.3 october 23, 2012 instruction). Thus, the lr contents can be used as a return address for a subroutine that was entered using a link update form of branch. The bclr instruction uses the lr in this fashion, enabling indirect ...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 107 of 864 2.9.5.3 condition register (cr) the cr is used to record certain information (“conditions”) related to the results of the various instructions that are enabled to update the cr. A bit in the cr can also be ...
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User’s manual a2 processor cpu programming model page 108 of 864 version 1.3 october 23, 2012 to summarize, the cr can be accessed in any of the following ways: • mfcr reads the cr into a gpr. Note that this instruction does not update the cr and is therefore not listed in table 2-36. • conditional ...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 109 of 864 • certain forms of various integer instructions (the “.” forms) implicitly update cr[cr0], as do certain forms of the auxiliary processor instructions implemented within the a2 core. • auxiliary processor i...
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User’s manual a2 processor cpu programming model page 110 of 864 version 1.3 october 23, 2012 cr update by integer compare instructions integer compare instructions update a specified cr field with the result of a comparison of two 64-bit numbers in 64-bit mode or two 32-bit numbers in 32-bit mode, ...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 111 of 864 the following table illustrates the fields of the xer, while table 2-38 and table 2-39 list the instructions that update xer[so,ov] and the xer[ca] fields, respectively. The sections that follow the figure ...
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User’s manual a2 processor cpu programming model page 112 of 864 version 1.3 october 23, 2012 2.10.2.1 summary overflow (so) field this field is set to 1 when an instruction is executed that causes xer[ov] to be set to 1, except for the case of mtspr(xer), which writes xer[so,ov] with the values in ...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 113 of 864 2.10.2.4 transfer byte count (tbc) field the tbc field is used by the string indexed integer storage access instructions (lswx and stswx) as a byte count. The tbc field is also written by mtspr(xer) with th...
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User’s manual a2 processor cpu programming model page 114 of 864 version 1.3 october 23, 2012 2.11.1 special purpose registers general (sprg0–sprg8) sprg0 through sprg8 are provided for general purpose, system-dependent software use. One common system usage of these registers is as temporary storage...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 115 of 864 table 2-42. Sprg2 register table 2-43. Sprg3 register table 2-44. Sprg4 register register short name: sprg2 read access: priv decimal spr number: 274 write access: priv initial value: 0x0000000000000000 dup...
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User’s manual a2 processor cpu programming model page 116 of 864 version 1.3 october 23, 2012 table 2-45. Sprg5 register table 2-46. Sprg6 register table 2-47. Sprg7 register register short name: sprg5 read access: priv/any decimal spr number: 277/261 write access: priv/none initial value: 0x0000000...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 117 of 864 table 2-48. Sprg8 register table 2-49. Gsprg0 register table 2-50. Gsprg1 register register short name: sprg8 read access: hypv decimal spr number: 604 write access: hypv initial value: 0x0000000000000000 d...
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User’s manual a2 processor cpu programming model page 118 of 864 version 1.3 october 23, 2012 table 2-51. Gsprg2 register table 2-52. Gsprg3 register register short name: gsprg2 read access: priv decimal spr number: 370 write access: priv initial value: 0x0000000000000000 duplicated for multithread:...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 119 of 864 2.11.2 external process id load context (eplc) register the eplc register contains fields to provide the context for external process id load instructions. 2.11.3 external process id store context (epsc) re...
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User’s manual a2 processor cpu programming model page 120 of 864 version 1.3 october 23, 2012 2.12 privileged modes the power isa architecture defines two operating “states” or “modes”: supervisor (privileged) and user (nonprivileged). Which mode the processor is operating in is controlled by msr[pr...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 121 of 864 2.12.1 privileged instructions an instruction that is hypervisor privileged must be in the hypervisor state (msr[gs,pr] = 0b00) to success- fully execute. If executed from guest privileged state (msr[gs,pr]...
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User’s manual a2 processor cpu programming model page 122 of 864 version 1.3 october 23, 2012 endif else // msrp[uclep]=0 or msr[gs] = 0 if msr[pr]=1 and msr[ucle]=0 cache locking type data storage interrupt endif end 2.12.2 privileged sprs most sprs are privileged. The only defined nonprivileged sp...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 123 of 864 under certain circumstances, it is necessary for the hardware or software to force the synchronization of a program’s context. Context synchronizing operations include all interrupts except machine check, a...
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User’s manual a2 processor cpu programming model page 124 of 864 version 1.3 october 23, 2012 iac event is recognized on the execution of this instruction; without the isync, the xyz instruction might be prefetched and dispatched to execution before recog- nizing that the iac event has been enabled....
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User’s manual a2 processor version 1.3 october 23, 2012 cpu programming model page 125 of 864 in this example, the mtdcr is reconfiguring the i/o device in a manner that would cause the preceding store instruction to fail, were the mtdcr to change the device before the completion of the store. Becau...
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User’s manual a2 processor cpu programming model page 126 of 864 version 1.3 october 23, 2012 2.15.2.1 l1 d-cache four bits are added per cache block, representing the set of watches that exist for that block corresponding to each thread. If not already available, the a2 core needs to provide a thre...
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User’s manual a2 processor version 1.3 october 23, 2012 fu programming model page 127 of 864 3. Fu programming model the programming model of the a2 core describes how the following features and operations appear to programmers: • storage addressing, including storage operands, effective address cal...
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User’s manual a2 processor fu programming model page 128 of 864 version 1.3 october 23, 2012 the alignment of the operand effective address of some storage access instructions can affect performance and in some cases can cause an alignment exception to occur. For such storage access instructions, th...
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User’s manual a2 processor version 1.3 october 23, 2012 fu programming model page 129 of 864 3.2 floating-point exceptions each floating-point exception, and each category of invalid operation exception, is associated with an excep- tion bit in the fpscr. The following floating-point exceptions are ...
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User’s manual a2 processor fu programming model page 130 of 864 version 1.3 october 23, 2012 3.3.1 register types the a2 core core provides two types of registers, floating-point registers (fprs) and the fpscr. Each type is characterized by the instructions used to read and write the registers. The ...
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User’s manual a2 processor version 1.3 october 23, 2012 fu programming model page 131 of 864 3.3.1.2 floating-point status and control register (fpscr) the fpscr controls the handling of floating-point exceptions and records status resulting from the floating- point operations. Table 3-4. Floating-p...
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User’s manual a2 processor fu programming model page 132 of 864 version 1.3 october 23, 2012 39 vxsnan floating-point invalid operation exception (snan) 0 a floating-point invalid operation exception (vxsnan) did not occur. 1 a floating-point invalid operation exception (vxsnan) occurred. See invali...
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User’s manual a2 processor version 1.3 october 23, 2012 fu programming model page 133 of 864 programming note: all floating-point operations conform to the ieee standard. All floating-point operations produce the same results regardless of the value of ieee mode (ni) bit. 3.4 floating-point data for...
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User’s manual a2 processor fu programming model page 134 of 864 version 1.3 october 23, 2012 load single instruction, it is converted to double format and placed in the target fpr. Conversely, a floating- point value stored from an fpr into storage using a store single instruction is converted to si...
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User’s manual a2 processor version 1.3 october 23, 2012 fu programming model page 135 of 864 the fprs support the floating-point double format only. The numeric and nonnumeric values representable within each of the two supported formats are approxima- tions to the real numbers and include the norma...
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User’s manual a2 processor fu programming model page 136 of 864 version 1.3 october 23, 2012 3.4.2.2 denormalized numbers denormalized numbers (±den) are values that have a biased exponent value of zero and a nonzero fraction value. They are nonzero numbers smaller in magnitude than the representabl...
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29 0 else fpr(frt)  fpr(frb) else if fpr(frc) is a nan then fpr(frt)  fp...
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User’s manual a2 processor fu programming model page 138 of 864 version 1.3 october 23, 2012 3.4.5 normalization and denormalization • the intermediate result of an arithmetic or frsp instruction might require normalization and/or denormal- ization. Normalization and denormalization do not affect th...
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User’s manual a2 processor version 1.3 october 23, 2012 fu programming model page 139 of 864 ments, or used directly as operands for single-precision arithmetic instructions, without preceding the store, or the arithmetic instruction, by an frsp instruction. • single-precision arithmetic instruction...
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User’s manual a2 processor fu programming model page 140 of 864 version 1.3 october 23, 2012 figure 3-2 shows the relation of z, z1, and z2 in this case. The following rules specify the rounding in the four modes. “lsb” means “least-significant bit.” table 3-9 describes the rounding modes. 3.5 float...
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User’s manual a2 processor version 1.3 october 23, 2012 fu programming model page 141 of 864 arithmetic instructions require all operands to be single-precision. Double-precision arithmetic instructions produce double-precision values, while single-precision arithmetic instructions produce single-pr...
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User’s manual a2 processor fu programming model page 142 of 864 version 1.3 october 23, 2012 after normalization, the intermediate result is rounded using the rounding mode specified by fpscr[rn]. If rounding results in a carry into c, the significand is shifted right one position and the exponent i...
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User’s manual a2 processor version 1.3 october 23, 2012 fu programming model page 143 of 864 3.5.2 execution model for multiply-add type instructions the a2 core provides a special form of instruction that performs up to three operations in one instruction (a multiplication, an addition, and a negat...
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User’s manual a2 processor fu programming model page 144 of 864 version 1.3 october 23, 2012 the single-precision instructions for which there is a corresponding double-precision instruction have the same format and extended opcode as the corresponding double-precision instruction. Instructions are ...
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User’s manual a2 processor version 1.3 october 23, 2012 fu programming model page 145 of 864 for consistency, to reduce the likelihood of causing a serious malfunction due to user error, and to enable random testing, single-precision operations are performed on double-precision operands. For all cas...
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29 0 for double-precision load f...
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User’s manual a2 processor version 1.3 october 23, 2012 fu programming model page 147 of 864 no denormalization required (includes zero / infinity / nan) if fpr(frs) 1:11 > 896 or fpr(frs) 1:63 = 0 then word 0:1  fpr(frs) 0:1 word 2:31  fpr(frs) 5:34 denormalization required if 874  frs 1:11  89...
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User’s manual a2 processor fu programming model page 148 of 864 version 1.3 october 23, 2012 note: for complete instruction descriptions, see the power isa v2.06 specification. 3.6.4 floating-point move instructions these instructions copy data from one floating-point register to another, altering t...
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User’s manual a2 processor version 1.3 october 23, 2012 fu programming model page 149 of 864 note: for complete instruction descriptions, see the power isa v2.06 specification. 3.6.5.1 floating-point multiply-add instructions these instructions combine a multiply and an add operation without an inte...
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User’s manual a2 processor fu programming model page 150 of 864 version 1.3 october 23, 2012 note: for complete instruction descriptions, see the power isa v2.06 specification. 3.6.7 floating-point compare instructions the floating-point compare instructions compare the contents of two floating-poin...
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User’s manual a2 processor version 1.3 october 23, 2012 fu programming model page 151 of 864 note: for complete instruction descriptions, see the power isa v2.06 specification. 3.6.8 floating-point status and control register instructions every floating-point status and control register instruction ...
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User’s manual a2 processor fu programming model page 152 of 864 version 1.3 october 23, 2012.
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User’s manual a2 processor version 1.3 october 23, 2012 initialization page 153 of 864 4. Initialization reset of the a2 core is performed by a flush 0 scan of all rings followed by scan initialization of specific rings as required. Reset controls external to the core drive scan ring selection and c...
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User’s manual a2 processor initialization page 154 of 864 version 1.3 october 23, 2012 thrctl register. A scom write to the thrctl register can then reset the stop bit for the desig- nated thread, and instruction execution commences. B. The ten register can be initialized such that individual thread...
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User’s manual a2 processor version 1.3 october 23, 2012 initialization page 155 of 864 instruction execution starts at the iar effective address scanned into the boot configuration ring during hard- ware reset (0x0000_0000_ffff_fffc, the last word of the effective address space, or some other locati...
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User’s manual a2 processor initialization page 156 of 864 version 1.3 october 23, 2012 iucr0 0x000010fa default reset value can be altered via a scan of the boot configuration ring. Initializes the various branch prediction options. Iucr1 0x00001000 default reset value can be altered via a scan of t...
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User’s manual a2 processor version 1.3 october 23, 2012 initialization page 157 of 864 xucr0 0x000708c0 default reset value can be altered via a scan of the boot configuration ring. Initializes various xu control parameter fields. Xucr1 0x00000000 default reset value can be altered via a scan of the...
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User’s manual a2 processor initialization page 158 of 864 version 1.3 october 23, 2012 table 4-2. Shadow tlb array entry initialization (sheet 1 of 3) resource field reset value comment tlbentry[1] 1 epn 0:51 system-dependent c. Reset value is specified by the boot configuration ring. X 0 exclusion ...
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User’s manual a2 processor version 1.3 october 23, 2012 initialization page 159 of 864 tlbentry[2] 2 epn 0:51 0x0000000000000 effective page number (matches ivpr(0:51) reset value). X 0 exclusion range enable bit (disabled). Size 0b0001 page size selection (set to 4 kb). This field is recoded to a 3...
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User’s manual a2 processor initialization page 160 of 864 version 1.3 october 23, 2012 4.3 software initiated reset requests the power isa book iii-e defines two sets of facilities that can be used by software to request a reset: debug and the watchdog timer. Whether or not these facilities are used...
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User’s manual a2 processor version 1.3 october 23, 2012 initialization page 161 of 864 because the reset request logic is implemented in multiple thread-specific sources, it is possible that more than one reset request output signal can be active at the same time. Software should coordinate the use ...
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User’s manual a2 processor initialization page 162 of 864 version 1.3 october 23, 2012 the an_ac_reset_x_complete inputs must be active for a minimum of one clock pulse to set the dbsr[mrr] and tsr[wrs] reset status bits. If more than one reset input is active at the same time, they are set using th...
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User’s manual a2 processor version 1.3 october 23, 2012 initialization page 163 of 864 4.4 initialization software requirements after a reset operation occurs, the a2 core is initialized to a minimum configuration to enable the fetching and execution of the software initialization code and to guaran...
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User’s manual a2 processor initialization page 164 of 864 version 1.3 october 23, 2012 2. Invalidate the instruction cache (ici). 3. Invalidate the data cache (dci). 4. Synchronize memory accesses (msync). This step forces any data operations that might have been in progress before the reset operati...
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User’s manual a2 processor version 1.3 october 23, 2012 initialization page 165 of 864 • specify the invalidation class for the entry (can be used by subsequent erativax instructions). • disable the exclusion range function (x = 0); otherwise, one or more tlb entries must be config- ured to fit with...
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User’s manual a2 processor initialization page 166 of 864 version 1.3 october 23, 2012 • use rfi if changing the msr to match the new ts field of the tlb entry. (srr1 will be copied into the msr, and program execution will resume at the value in srr0.) • use rfi if changing the next instruction fetc...
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User’s manual a2 processor version 1.3 october 23, 2012 initialization page 167 of 864 • disable the exclusion range function (x = 0); otherwise, one or more erat entries needs to be configured to fit within the exclusion range. 9. Initialize interrupt resources. A. Initialize ivpr and givpr to spec...
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User’s manual a2 processor initialization page 168 of 864 version 1.3 october 23, 2012 13. Initialize the msr to enable interrupts as desired. A. Set msr[ce] to enable or disable critical input, watchdog timer, guest processor doorbell critical, and processor doorbell critical interrupts. B. Set msr...
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User’s manual a2 processor version 1.3 october 23, 2012 instruction and data caches page 169 of 864 5. Instruction and data caches the a2 core provides separate instruction and data cache controllers and arrays, which allow concurrent access and minimize pipeline stalls. The storage capacity of the ...
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User’s manual a2 processor instruction and data caches page 170 of 864 version 1.3 october 23, 2012 5.2 instruction cache array organization and operation the instruction is 4-way set-associative, with 64 sets and a 64-byte line size. Table 5-3 illustrates generically the ways and sets of the cache ...
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User’s manual a2 processor version 1.3 october 23, 2012 instruction and data caches page 171 of 864 the icc provides a speculative prefetch mechanism that automatically prefetches up to one line per thread upon any fetch request that misses in the instruction cache. The icc also handles the executio...
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User’s manual a2 processor instruction and data caches page 172 of 864 version 1.3 october 23, 2012 cache or within memory itself, by the a2 core through the execution of store instructions or by some other mechanism in the system writing to memory, software must use cache management instructions to...
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User’s manual a2 processor version 1.3 october 23, 2012 instruction and data caches page 173 of 864 5.4.3.2 instruction cache parity operations the instruction cache contains parity bits to protect against soft data errors. Both the instruction tags and data are protected. Instruction cache lines co...
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User’s manual a2 processor instruction and data caches page 174 of 864 version 1.3 october 23, 2012 extensive load, store, and flush queues are also provided, such that up to eight outstanding load misses with the dcc continuing to service subsequent load and store hits in an in-order fashion. The r...
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User’s manual a2 processor version 1.3 october 23, 2012 instruction and data caches page 175 of 864 software must make sure that no lines from that page remain valid in the data cache (typically by using the dcbf instruction) before attempting to access the (now caching inhibited) page with load, st...
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User’s manual a2 processor instruction and data caches page 176 of 864 version 1.3 october 23, 2012 (of only accessing the requested bytes) is only architecturally required when the guarded storage attribute is also set, but the dcc enforces this requirement on any load to a caching inhibited memory...
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User’s manual a2 processor version 1.3 october 23, 2012 instruction and data caches page 177 of 864 • 16-byte write request (any byte address 0–16 within a double quadword) only possible due to an axu quadword store. • 32-byte write request (must be to byte address 0 of a double quadword) only possi...
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User’s manual a2 processor instruction and data caches page 178 of 864 version 1.3 october 23, 2012 section 2.12.1 privileged instructions on page 121 summarizes which data cache management instructions are privileged. The following instructions are used by software to manage the data cache. 5.5.3.2...
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User’s manual a2 processor version 1.3 october 23, 2012 instruction and data caches page 179 of 864 the dcbt instruction can also be used as a convenient mechanism for setting up a fixed, known environment within the data cache. This is useful for deterministic performance on a particular sequence o...
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User’s manual a2 processor instruction and data caches page 180 of 864 version 1.3 october 23, 2012 • ct = 0 indicates l1 only. Note that icbtls ct = 0 is treated the same as icbt ct = 0 because instruction cache locking/unlocking is not supported. • ct = 2 indicates l2 only. The cache line is not p...
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User’s manual a2 processor version 1.3 october 23, 2012 instruction and data caches page 181 of 864 4. Execute an rfi. If the locking instruction is a clear lock instruction, to unlock the line, the handler should do the following: 1. Remove the line address from its list of locked lines. 2. Execute...
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User’s manual a2 processor instruction and data caches page 182 of 864 version 1.3 october 23, 2012 instructions: notes: • in the l1 data cache, the a2 implements a lock bit for every index and way, allowing a line locking granu- larity. Setting ct = 0 specifies the l1 cache. • the a2 supports ct = ...
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User’s manual a2 processor version 1.3 october 23, 2012 instruction and data caches page 183 of 864 the a2 implements a flash clear for all data cache lock bits (using xucr0[clfc]). This allows system soft- ware to clear all data cache locking bits without knowing the addresses of the lines locked. ...
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User’s manual a2 processor instruction and data caches page 184 of 864 version 1.3 october 23, 2012 are treated as misses and do not update the contents of the directory, and back-invalidates from the l2 do not invalidate any cache lines. A dci instruction does however invalidate the entire data cac...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 185 of 864 6. Memory management the a2 core supports a uniform, 2 64 bytes (64 bits) effective address (ea) space and a 4 tb (42-bit) real address (ra) space. The a2 memory management unit (mmu) performs address translati...
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User’s manual a2 processor memory management page 186 of 864 version 1.3 october 23, 2012 the tlb is parity protected against soft errors. The details of parity checking are described in the following sections. 6.1.1 support for power isa mmu architecture the a2 memory management unit is based on po...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 187 of 864 6.2.1 virtual address formation the first step in page identification is the expansion of the effective address into a virtual address. Again, the effective address is the 64-bit address calculated by a load, s...
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User’s manual a2 processor memory management page 188 of 864 version 1.3 october 23, 2012 by convention, application-level code runs with msr[is,ds] set to 1 and uses corresponding tlb entries with the ts = 1. Conversely, system-level code runs with msr[is,ds] set to 0 and uses corresponding tlb ent...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 189 of 864 8. Not all of the address space defined by the hole needs to be mapped by other entries. 9. Pages mapped in the hole must be page-size aligned. 10. Pages mapped in the hole must not overlap. 11. Pages mapped in...
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User’s manual a2 processor memory management page 190 of 864 version 1.3 october 23, 2012 figure 6-1 illustrates the criteria for a virtual address to match a specific direct or indirect tlb entry, while table 6-1 defines the page sizes associated with each size field value and the associated compar...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 191 of 864 6.3 address translation after a direct (ind = 0) tlb entry is found that matches the virtual address associated with a given storage access, as described in section 6.2 page identification on page 186, the virt...
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User’s manual a2 processor memory management page 192 of 864 version 1.3 october 23, 2012 figure 6-2. Effective-to-real address translation flow table 6-2. Page size and real address formation size 1 page size rpn bits required to be 0 real address 0b0000 0b0001 0b0010 0b0011 0b0100 0b0101 0b0110 0b...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 193 of 864 6.4 access control after a matching tlb entry has been identified and the address has been translated, the access control mechanism determines whether the program has execute, read, and/or write access to the p...
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User’s manual a2 processor memory management page 194 of 864 version 1.3 october 23, 2012 6.4.3 read access the user state read enable (ur) or supervisor state read enable (sr) bit of a tlb entry controls read access to a page, depending on the operating mode (user or supervisor) of the processor. •...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 195 of 864 6.5 storage attributes each tlb entry specifies a number of storage attributes for the memory page with which it is associated. Storage attributes affect the manner in which storage accesses to a given page are...
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User’s manual a2 processor memory management page 196 of 864 version 1.3 october 23, 2012 6.5.1 write-through (w) the a2 core data cache ignores the write-through attribute. The data for all store operations is written to memory, as opposed to only being written into the data cache. If the reference...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 197 of 864 a data access to a guarded storage location is performed only if either the access is caused by an instruction that is known to be required by the sequential execution model, or the access is a load and the sto...
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User’s manual a2 processor memory management page 198 of 864 version 1.3 october 23, 2012 • the m bits do not need to match on all pages; however, it is then software’s responsibility to maintain data coherency. 2. If the multiple pages exist on multiple processors, then: • the i bits do not need to...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 199 of 864 each tlb entry identifies a page and defines its translation, access controls, and storage attributes. Accord- ingly, fields in the tlb entry fall into four categories: • page identification fields (information...
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User’s manual a2 processor memory management page 200 of 864 version 1.3 october 23, 2012 0 67 ts translation address space (1 bit) this bit indicates the address space with which this tlb entry is associated. For instruction storage accesses, msr[is] must match the value of ts in the tlb entry for ...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 201 of 864 address translation fields 1 18:21 - reserved (4 bits) reserved for real page number extension. 1 22:51 rpn 9 real page number (variable size, from 18 - 30 bits) bits 22:n–1 of the rpn field are used to replace...
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User’s manual a2 processor memory management page 202 of 864 version 1.3 october 23, 2012 1 59 sx (ind = 0) spsize 1 (ind = 1) supervisor state execute enable (ind = 0) or spsize 1 (ind = 1) 9 (1 bit) 0 (ind = 0) instruction fetch is not permitted from this page while msr[pr] = 0, and the attempt to...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 203 of 864 6.7 effective to real address translation arrays the a2 core implements two fully-associative effective to real address translation (erat) arrays also called shadow tlb arrays): one for instruction fetches and ...
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User’s manual a2 processor memory management page 204 of 864 version 1.3 october 23, 2012 lookup finds no direct entries, but does find an indirect entry (ind = 1), then the address is forwarded to the hardware page table walker for page table lookup. If the address also misses the indirect entry lo...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 205 of 864 eratilx instructions. By invalidating the erat arrays, a context-altering instruction forces the hardware to refresh the erat entries with the updated information in the utlb as each memory page is accessed (wh...
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User’s manual a2 processor memory management page 206 of 864 version 1.3 october 23, 2012 occur in mmu mode. The erat lru index number is incremented (the mod number of entries below the watermark is described section 6.7.5) in a round-robin fashion each time an entry is written as the result of a t...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 207 of 864 installed with extclass = 0 regardless of the value of the tlb entry iprot bit. Tlb entries created via page table translation (that is, by the hardware page table walker) are always created with iprot = 0 and ...
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User’s manual a2 processor memory management page 208 of 864 version 1.3 october 23, 2012 the tlbwe with mas0[hes] = 0 back-invalidate scenario above is intended to represent software overwriting a specific, valid tlb entry whose virtual address matches that of a shadow erat copy. This is particular...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 209 of 864 when translations occur in the i-erat due to instruction fetches, the class field is not used as part of the compare function (assuming mmucr1[ictid] = 0). When translations occur in the d-erat, however, the cl...
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User’s manual a2 processor memory management page 210 of 864 version 1.3 october 23, 2012 this, hypervisor software must always ensure that at least one valid logical to real address translation (lrat) entry exists. The a2 core implements an 8-entry, fully-associative logical to lrat array in suppor...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 211 of 864 include: 1 mb, 16 mb, 256 mb, 1 gb, 4 gb, 16 gb, 256 gb, and 1 tb. These logical pages, or sectors, can be sized by the hypervisor to encompass a single large effective page or many smaller effective pages mapp...
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User’s manual a2 processor memory management page 212 of 864 version 1.3 october 23, 2012 6.9 tlb management instructions (architected) to enable software to manage the tlb, a set of tlb management instructions is implemented within the a2 core. These instructions are described briefly in the sectio...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 213 of 864 this processor is compliant with category e.Pt, and the size and location of the hardware page tables and format of the associated hardware page table entries are well defined. Aside from this, this processor c...
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User’s manual a2 processor memory management page 214 of 864 version 1.3 october 23, 2012 ferred. When mas0[hes] = 1, the entry way is defined by the hardware lru mechanism (which always excludes entries with iprot = 1). Finally, the contents of the selected tlb entry are transferred from the approp...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 215 of 864 writing tlb entries with tlbwe is supervisory privileged and is executable by either the hypervisor or a guest operating system (msr[gs] = 1). The guest’s view of real addresses are actually termed “logical add...
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User’s manual a2 processor memory management page 216 of 864 version 1.3 october 23, 2012 6.9.4 tlb invalidate virtual address (indexed) instruction (tlbivax) the tlbivax instruction is used to invalidate tlb and erat entries that contain the virtual page number asso- ciated with the effective addre...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 217 of 864 incoming invalidation snoop lpid value matches the current value of the lpidr[lpid] field, there is no rejec- tion of the transaction by the mmu; and a tlbi_complete is issued to the memory subsystem as after t...
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User’s manual a2 processor memory management page 218 of 864 version 1.3 october 23, 2012 6.9.5 tlb invalidate local (indexed) instruction (tlbilx) the tlbilx instruction is used to invalidate tlb and erat entries that contain the virtual page number associ- ated with the effective address of this i...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 219 of 864 the tlbsync instruction can be used (in memory subsystems that support this behavior) to ensure that the effects of global tlbivax and erativax operations have been made globally visible. Generally, this behavi...
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User’s manual a2 processor memory management page 220 of 864 version 1.3 october 23, 2012 erat entry is to be transferred (that is, ws = 0 specifies erat word 0, and so on). Finally, the contents of the selected erat word are transferred to or from a designated target or source gpr (and the mmucr0 g...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 221 of 864 page 189). Finally, the index of the matching entry is written into the target register (rt). This index value can then serve as the source value for a subsequent eratre or eratwe instruction, to read or update...
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User’s manual a2 processor memory management page 222 of 864 version 1.3 october 23, 2012 the erativax invalidation snoops from the bus contain a target lpid value. The handling of the invalidation snoops based on this lpid value is dependent on the configured mode of the receiving core. While a het...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 223 of 864 when global erativax operations are sent over certain system bus structures (such as the pbus), some of the information associated with the invalidate transaction needs to be condensed to conform to the bus wid...
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User’s manual a2 processor memory management page 224 of 864 version 1.3 october 23, 2012 6.10.4 erat invalidate local (indexed) instruction (eratilx) the eratilx instruction is used to invalidate local erat entries that contain the virtual page number associ- ated with the effective address of this...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 225 of 864 tlb hit reloads in mmu mode, need to have the upper 32 bits of the effective page number zeroed at the time of installation to have effective addresses compare successfully on these entries. This is done automa...
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User’s manual a2 processor memory management page 226 of 864 version 1.3 october 23, 2012 6.11.4 32-bit mode tlb invalidate virtual address (indexed) instruction (tlbivax) the tlbivax instruction is used to invalidate tlb (and erat) entries that contain the virtual page number associated with the ef...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 227 of 864 6.11.8 32-bit mode erat search instruction (eratsx[.]) in 32-bit mode, the eratsx[.] instruction is used to locate an entry in the i-erat or d-erat that is associated with a particular virtual address. This ins...
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User’s manual a2 processor memory management page 228 of 864 version 1.3 october 23, 2012 forwarding invalidation snoops to target processors. This implies that the effective page number (epn) in the erat entries that pertain to the current 32-bit process need to have been created with zeros in the ...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 229 of 864 if a write access is later attempted, a write access control exception type of data storage interrupt occurs. The interrupt handler can choose to record the change status to the memory page in a software table,...
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User’s manual a2 processor memory management page 230 of 864 version 1.3 october 23, 2012 a result of an eratsx or eratre instruction). When executing an i-erat or d-erat translation, parity is checked for the tag and data words. When executing an eratsx, only the tag parity is checked. When executi...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 231 of 864 achieved by protecting 511 out of 512 tlb entries is sufficient. Further, the software technique of simply dedi- cating a tlb entry to the page that contains the machine check handler and periodically refreshin...
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User’s manual a2 processor memory management page 232 of 864 version 1.3 october 23, 2012 mtspr mmucr1,rx ; set some mmucr1[pei] bits, and [csinv]=11. Isync ; wait for the mmmur1 context to update. Eratwe rs,ra,1 ; set up real portion word 1 of erat data. Eratwe rs,ra,0 ; write some data to the erat...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 233 of 864 based on this tlb reservation. Because tlb writes by other threads reset the reservation and the tlbsrx. Instruction can be used to detect tlb entries created by other threads, there is protection against dupli...
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User’s manual a2 processor memory management page 234 of 864 version 1.3 october 23, 2012 a tlb reservation is established or set (the reservation latch fields are updated and the valid bit is set to ‘1’), only by execution of the tlbsrx. Instruction. The result of the search of the tlb is irrelevan...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 235 of 864 f. The mas1 ts value used by the tlbwe matches the as value associated with the tlb reservation. G. Bits 0:(n-1) of mas2 epn used by the tlbwe match the epn 0:n-1 values associated with the tlb reser- vation, w...
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User’s manual a2 processor memory management page 236 of 864 version 1.3 october 23, 2012 (2) the mas0 wq used by the tlbwe instruction is 0b11 (this mas0 wq reserved setting is treated the same as the setting of 0b00, or write tlb always). 2. A tlbilx instruction is executed by the thread holding t...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 237 of 864 6.16 hardware page table walking (category e.Pt) this processor supports the power isa category embedded.Page table (e.Pt) and the embedded mmu architecture version 2.0 (mav 2.0). Because this processor also su...
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User’s manual a2 processor memory management page 238 of 864 version 1.3 october 23, 2012 6.16.2 indirect tlb entry page and sub-page sizes each indirect tlb entry represents a hardware page table in memory, and there can be many disjoint page tables existing in various areas of real memory. Each in...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 239 of 864 lar page table. To accomplish this, the operating system needs to install 16 mb/64 kb = 256 duplicates of the 16 mb size pte so that the first virtual address falling in this 1/16 “chunk” of the 256 mb indirect...
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User’s manual a2 processor memory management page 240 of 864 version 1.3 october 23, 2012 6.16.4 calculation of hardware page table entry real address although this processor implements only power of 4  1 k page sizes and sub-page sizes, for the sake of this example, tsize and spsize are interprete...
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ea 64-p:63 , where p = log 2 (page size specified by pte ps ). Finally, if the indirect entry’s tgs = 1 (a guest pa...
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User’s manual a2 processor memory management page 242 of 864 version 1.3 october 23, 2012 subsystem when the hardware walker fetches a pte entry. It is the responsibility of software installing the indirect tlb entry to ensure that the wimge settings are valid. Execution of a tlbwe with mas1 ind = 1...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 243 of 864 c n pte c wlc n 0b00 resvattr n 0 table 6-14. Tlb update after page table translation (sheet 2 of 2) tlb field architected? New value after page table translation 1. The tlb page size field supported by this im...
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User’s manual a2 processor memory management page 244 of 864 version 1.3 october 23, 2012 6.17 storage control registers (architected) this section describes the specific implementation of the architected storage control related registers. In addi- tion to the registers described below, the msr[is,d...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 245 of 864 6.17.2 logical partition id register (lpidr) the lpidr is written from a gpr using mtspr and can be read into a gpr using mfspr. This register is shared between all processing threads. Therefore, software locki...
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User’s manual a2 processor memory management page 246 of 864 version 1.3 october 23, 2012 6.17.3 external pid load context (eplc) register the eplc is written from a gpr using mtspr and can be read into a gpr using mfspr. The eplc register contains fields that provide the context for external pid lo...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 247 of 864 6.17.4 external pid store context (epsc) register the epsc is written from a gpr using mtspr and can be read into a gpr using mfspr. The epsc register contains fields that provide the context for external pid s...
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User’s manual a2 processor memory management page 248 of 864 version 1.3 october 23, 2012 6.17.5 mmu assist register 0 (mas0) the mas0 register is written from a gpr using mtspr and can be read into a gpr using mfspr. This register is replicated for all processing threads. Mas0 is used to define whi...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 249 of 864 6.17.6 mmu assist register 1 (mas1) the mas1 register is written from a gpr using mtspr and can be read into a gpr using mfspr. This register is replicated for all processing threads. Mas1 is used by certain tl...
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User’s manual a2 processor memory management page 250 of 864 version 1.3 october 23, 2012 programming note 1: this register provides for setting the iprot protection bit of tlb entries. For this implementation, it is recommended that no more than two entries in any single congruence class of the tlb...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 251 of 864 tlbilx instructions regardless of where they are placed within a tlb congruence class). As such, when imple- menting a totally software-managed tlb system, using only tlbwe with mas0[hes] = 0 to install tlb ent...
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User’s manual a2 processor memory management page 252 of 864 version 1.3 october 23, 2012 6.17.8 mmu assist register 2 upper (mas2u) the mas2u register is written from a gpr using mtspr and can be read into a gpr using mfspr. This register is replicated for all processing threads. Mas2u is used by c...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 253 of 864 6.17.9 mmu assist register 3 (mas3) the mas3 register is written from a gpr using mtspr, and can be read into a gpr using mfspr. This register is replicated for all processing threads. Mas3 is used by certain t...
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User’s manual a2 processor memory management page 254 of 864 version 1.3 october 23, 2012 59 sx/spsize1 0b0 supervisor mode execute enable (ind = 0) / spsize1 (ind = 1) for direct tlb (ind = 0) entries, specifies supervisor mode (msr.Pr = 0) execute access permission. See section 6.4 access control ...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 255 of 864 6.17.10 mmu assist register 4 (mas4) the mas4 register is written from a gpr using mtspr and can be read into a gpr using mfspr. This register is replicated for all processing threads. Mas4 is used by certain e...
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User’s manual a2 processor memory management page 256 of 864 version 1.3 october 23, 2012 6.17.11 mmu assist register 5 (mas5) the mas5 register is written from a gpr using mtspr and can be read into a gpr using mfspr. This register is replicated for all processing threads. Mas5 is used to supply hy...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 257 of 864 6.17.12 mmu assist register 6 (mas6) the mas6 register is written from a gpr using mtspr and can be read into a gpr using mfspr. This register is replicated for all processing threads. Mas6 is used to supply se...
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User’s manual a2 processor memory management page 258 of 864 version 1.3 october 23, 2012 6.17.13 mmu assist register 7 (mas7) the mas7 register is written from a gpr using mtspr, and can be read into a gpr using mfspr. This register is replicated for all processing threads. Mas7 is used to transfer...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 259 of 864 6.17.14 mmu assist register 8 (mas8) the mas8 register is written from a gpr using mtspr and can be read into a gpr using mfspr. This register is replicated for all processing threads. Mas8 is used to transfer ...
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User’s manual a2 processor memory management page 260 of 864 version 1.3 october 23, 2012 6.17.15 mas0_mas1 register the mas0_mas1 register is written from a 64-bit gpr using mtspr and can be read into a 64-bit gpr using mfspr. This register is replicated for all processing threads. Mas0_mas1 is use...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 261 of 864 6.17.16 mas5_mas6 register the mas5_mas6 register is written from a 64-bit gpr using mtspr and can be read into a 64-bit gpr using mfspr. This register is replicated for all processing threads. Mas5_mas6 is use...
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User’s manual a2 processor memory management page 262 of 864 version 1.3 october 23, 2012 6.17.17 mas7_mas3 register the mas7_mas3 register is written from a 64-bit gpr using mtspr and can be read into a 64-bit gpr using mfspr. This register is replicated for all processing threads. Mas7_mas3 is use...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 263 of 864 6.17.18 mas8_mas1 register the mas8_mas1 register is written from a 64-bit gpr using mtspr and can be read into a 64-bit gpr using mfspr. This register is replicated for all processing threads. Mas8_mas1 is use...
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User’s manual a2 processor memory management page 264 of 864 version 1.3 october 23, 2012 6.17.19 mmu configuration register (mmucfg) the mmucfg register is a read-only register that can be read into a gpr using mfspr. Mmucfg is used to provide implementation-specific parameters to a guest operating...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 265 of 864 6.17.20 mmu control and status register 0 (mmucsr0) the mmucsr0 register is written from a gpr using mtspr and can be read into a gpr using mfspr. Mmucsr0 is used to provide a register-based invalidate all func...
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User’s manual a2 processor memory management page 266 of 864 version 1.3 october 23, 2012 6.17.21 tlb 0 configuration register (tlb0cfg) the tlb0cfg register is a read-only register that can be read into a gpr using mfspr. Tlb0cfg is used to provide implementation-specific parameters regarding the t...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 267 of 864 engineering note: the tlb0cfg[pt] and [ind] bits are both resident on the boot configuration scan chain. Therefore, it is possible to set these bits independently. For a2, because there is only one shared tlb p...
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User’s manual a2 processor memory management page 268 of 864 version 1.3 october 23, 2012 6.17.22 tlb 0 page size register (tlb0ps) the tlb0ps register is a read-only register that can be read into a gpr using mfspr. Tlb0ps is used to provide additional implementation-specific parameters regarding t...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 269 of 864 6.17.23 lrat configuration register (lratcfg) the lratcfg register is a read-only register that can be read into a gpr using mfspr. Lratcfg is used to provide implementation-specific parameters regarding the lr...
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User’s manual a2 processor memory management page 270 of 864 version 1.3 october 23, 2012 6.17.24 lrat page size register (lratps) the lratps register is a read-only register that can be read into a gpr using mfspr. Lratps is used to provide additional implementation-specific parameters about the su...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 271 of 864 53 ps10 0b1 page size 10 indicates whether a 2 10 kb (1 mb) page size is supported by this processor's lrat. This bit is always set to ‘1’ for this processor (the a2 supports 1 mb page sizes for the lrat). 54:6...
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User’s manual a2 processor memory management page 272 of 864 version 1.3 october 23, 2012 6.17.25 embedded page table configuration register (eptcfg) the eptcfg register is a read-only register that can be read into a gpr using mfspr. Eptcfg is used to provide additional implementation-specific para...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 273 of 864 6.17.26 logical page exception register (lper) the lper register captures the logical page number and page size of a page table entry (pte) logical-to-real translation that results in an lrat miss exception. Re...
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User’s manual a2 processor memory management page 274 of 864 version 1.3 october 23, 2012 6.17.27 logical page exception register upper (lperu) the lperu register captures the most-significant bits of the logical page number of a pte logical-to-real translation that results in an lrat miss exception...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 275 of 864 6.17.28 mas register update summary table 6-15 summarizes how this implementation’s mas registers are modified by instruction tlb error inter- rupts, data tlb error interrupts, and the tlb management instructio...
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User’s manual a2 processor memory management page 276 of 864 version 1.3 october 23, 2012 mas6 sas msr ds or msr is or eplc eas 8 or epsc eas 9 — — — mas7 rpnu 0 tlb rpn[22:31] 0 tlb rpn[22:31] 4 mas8 tgs vf tlpid — 7 tlb tgs vf tlpid — tlb tgs vf tlpid table 6-15. Mas register update summary (sheet...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 277 of 864 6.18 storage control registers (non-architected) this section describes the implementation-specific (nonarchitected) storage control registers. 6.18.1 memory management unit control register 0 (mmucr0) the mmuc...
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User’s manual a2 processor memory management page 278 of 864 version 1.3 october 23, 2012 zero by default. The mmucr0[ecl] field can be used by supervisory software to create erat entries that are “immune” to the local or global invalidations and context synchronizing event invalidations that would ...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 279 of 864 the mmucr0[tid] field is also used to transfer the erat entry’s tid field on eratre and eratwe instructions that target erat word 0. There are two reasons for this: there are not enough bits in the gpr used for...
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User’s manual a2 processor memory management page 280 of 864 version 1.3 october 23, 2012 6.18.2 memory management unit control register 1 (mmucr1) the mmucr1 register is written from a gpr using mtspr and can be read into a gpr using mfspr. This register is shared between all processing threads. Th...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 281 of 864 38:43 pei 0x0 parity error inject parity error inject bits: 0 normal parity calculation. 1 invert parity (when writing). 38 i-erat ws = 0 parity error inject. 39 i-erat ws = 1 parity error inject. 40 d-erat ws ...
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User’s manual a2 processor memory management page 282 of 864 version 1.3 october 23, 2012 sa8ui lru round-robin enable (irre) bit the mmucr1[irre] bit is used to enable the i-erat lru round-robin mode of operation. See section 6.7.4 erat lru round-robin replacement mode for a description of this beh...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 283 of 864 parity error inject (pei) field the mmucr1[pei] field is used to inject parity errors into the i-erat, d-erat, and/or the tlb entry targeted by a subsequent eratwe or tlbwe instruction. One bit is provided for ...
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User’s manual a2 processor memory management page 284 of 864 version 1.3 october 23, 2012 when this bit is set to a ‘1’, the d-erat logic treats the class field of each entry as 2 additional bits of the tid. In this mode, the 2-bit class field is used as tid[0:1] of the full tid[0:13] value (that is...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 285 of 864 external pid load/store translations. This puts the d-erat into a mode of operation similar to that of the i-erat in which the class field is used only for invalidation compares (caused by invalidation instruct...
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User’s manual a2 processor memory management page 286 of 864 version 1.3 october 23, 2012 i-erat error detect (ierrdet) bit the mmucr1[ierrdet] bit is set to a ‘1’ by hardware when the i-erat detects a multihit error or parity error, and the current values of the ierrdet, derrdet, and terrdet bits a...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 287 of 864 6.18.3 memory management unit control register 2 (mmucr2) the mmucr2 register is written from a gpr using mtspr and can be read into a gpr using mfspr. This register is shared between all processing threads. Th...
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User’s manual a2 processor memory management page 288 of 864 version 1.3 october 23, 2012 page size 0 (ps0) field the mmucr2[ps0] field is used to select which page size should be used first in the congruence class calcu- lation for multiple probes of the tlb. Setting this field to ‘0000’ disables p...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 289 of 864 page size 1 (ps1) field the mmucr2[ps1] field is used to select which page size should be used second in the congruence class calculation for multiple probes of the tlb. Setting this field to ‘0000’ disables pr...
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User’s manual a2 processor memory management page 290 of 864 version 1.3 october 23, 2012 6.18.4 memory management unit control register 3 (mmucr3) the mmucr3 register is written from a gpr using mtspr and can be read into a gpr using mfspr. This register is replicated for each thread. Mmucr3 is use...
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User’s manual a2 processor version 1.3 october 23, 2012 memory management page 291 of 864 the setting of the mas1[iprot] field controls how this field is used when writing tlb entries. When tlb entries are created via tlbwe instructions while mas1[iprot] = 0, this field is ignored, and the extclass ...
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User’s manual a2 processor memory management page 292 of 864 version 1.3 october 23, 2012.
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 293 of 864 7. Cpu interrupts and exceptions this chapter begins by defining the terminology and classification of interrupts and exceptions in overview and directed interrupts. Interrupt processing on page 297...
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User’s manual a2 processor cpu interrupts and exceptions page 294 of 864 version 1.3 october 23, 2012 syndrome information and the data exception address register (dear) to post the effective address of a data reference. Doorbell interrupts are directed to embedded hypervisor state, but use guest sa...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 295 of 864 ated the interrupt, or the instruction immediately following this instruction. Which instruction is addressed can be determined from a combination of the interrupt type and the setting of certain fi...
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User’s manual a2 processor cpu interrupts and exceptions page 296 of 864 version 1.3 october 23, 2012 executed next (that is, the instruction after the one that updated msr[fe0,fe1]). If the msr was updated by an rfi, rfci, rfgi, or rfmci instruction, srr0 is set to the address to which the rfi, rfc...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 297 of 864 going to complete appear to have done so already, and have done so within the context existing before the machine check interrupt. No further interrupt (other than possible additional machine check ...
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addr 32:63 • if (msr[cm...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 299 of 864 programming note: in general, at process switch, due to possible process interlocks and possible data availability requirements, the operating system needs to consider executing the following instru...
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User’s manual a2 processor cpu interrupts and exceptions page 300 of 864 version 1.3 october 23, 2012 as previously stated, the only load or store instructions that are guaranteed to not be interrupted after being partially executed are elementary-aligned and guarded loads and stores. All others can...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 301 of 864 • guest interrupt vector prefix register (givpr) on page 318 • exception syndrome register (esr) on page 318 • guest exception syndrome register (gesr) on page 320 • machine check status register (m...
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User’s manual a2 processor cpu interrupts and exceptions page 302 of 864 version 1.3 october 23, 2012 register short name: msr read access: priv decimal spr number: n/a write access: priv initial value: 0x0000000000000000 duplicated for multithread: y slow spr: n notes: guest supervisor mapping: sca...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 303 of 864 7.5.3 machine state register protect (msrp) 51 me 0b0 machine check enable 0 machine check interrupts are disabled. 1 machine check interrupts are enabled. 52 fe0 0b0 floating-point exception mode 0...
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User’s manual a2 processor cpu interrupts and exceptions page 304 of 864 version 1.3 october 23, 2012 7.5.4 embedded processor control register (epcr) 55:63 /// 0x0 reserved register short name: epcr read access: hypv decimal spr number: 307 write access: hypv initial value: 0x0000000000000000 dupli...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 305 of 864 7.5.5 save/restore register 0 (srr0) srr0 is an spr that is used to save the machine state on noncritical interrupts and to restore the machine state when an rfi is executed. When a noncritical inte...
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User’s manual a2 processor cpu interrupts and exceptions page 306 of 864 version 1.3 october 23, 2012 7.5.6 save/restore register 1 (srr1) srr1 is an spr that is used to save the machine state on noncritical interrupts and to restore the machine state when an rfi is executed. When a noncritical inte...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 307 of 864 37 ucle 0b0 user cache locking enable 0 cache locking instructions are privileged. 1 cache locking instructions can be executed in user mode (msr[pr] = 1). 38 spv 0b0 vector available 0 the processo...
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User’s manual a2 processor cpu interrupts and exceptions page 308 of 864 version 1.3 october 23, 2012 7.5.7 guest save/restore register 0 (gsrr0) gsrr0 is an spr that is used to save the machine state on interrupts directed to the guest state and to restore the machine state when an rfgi is executed...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 309 of 864 gsrr1 can be written from a gpr using mtspr and can be read into a gpr using mfspr. Gsrr1 is also accessed by reading srr1 when in the guest state (msr[gs] = 1). Register short name: gsrr1 read acce...
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User’s manual a2 processor cpu interrupts and exceptions page 310 of 864 version 1.3 october 23, 2012 7.5.9 critical save/restore register 0 (csrr0) csrr0 is an spr that is used to save the machine state on critical interrupts and to restore the machine state when an rfci is executed. When a critica...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 311 of 864 7.5.10 critical save/restore register 1 (csrr1) csrr1 is an spr that is used to save the machine state on critical interrupts and to restore the machine state when an rfci is executed. When a critic...
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User’s manual a2 processor cpu interrupts and exceptions page 312 of 864 version 1.3 october 23, 2012 37 ucle 0b0 user cache locking enable 0 cache locking instructions are privileged. 1 cache locking instructions can be executed in user mode (msr[pr] = 1). 38 spv 0b0 vector available 0 the processo...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 313 of 864 7.5.11 machine check save/restore register 0 (mcsrr0) mcsrr0 is an spr that is used to save the machine state on machine check interrupts and to restore the machine state when an rfmci is executed. ...
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User’s manual a2 processor cpu interrupts and exceptions page 314 of 864 version 1.3 october 23, 2012 mcsrr1 can be written from a gpr using mtspr and can be read into a gpr using mfspr. Register short name: mcsrr1 read access: hypv decimal spr number: 571 write access: hypv initial value: 0x0000000...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 315 of 864 7.5.13 data exception address register (dear) the dear contains the address that was referenced by a load, store, or cache management instruction that caused an alignment, data tlb miss, or data sto...
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User’s manual a2 processor cpu interrupts and exceptions page 316 of 864 version 1.3 october 23, 2012 7.5.14 guest data exception address register (gdear) the gdear contains the address that was referenced by a load, store, or cache management instruction that caused an alignment, data tlb miss, or ...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 317 of 864 0x0e0 program 0x100 floating-point unavailable 0x120 system call 0x140 auxiliary processor unavailable 0x160 decrementer 0x180 fixed interval timer 0x1a0 watchdog timer 0x1c0 data tlb error 0x1e0 in...
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User’s manual a2 processor cpu interrupts and exceptions page 318 of 864 version 1.3 october 23, 2012 7.5.15 interrupt vector prefix register (ivpr) the ivpr provides the high-order 52 bits of the effective address of the interrupt vectors for interrupts that are not directed to the guest state. The...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 319 of 864 the esr can be written from a gpr using mtspr and can be read into a gpr using mfspr. The esr is mapped to gesr when in the guest state (msr[gs] = 1). Register short name: esr read access: priv deci...
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User’s manual a2 processor cpu interrupts and exceptions page 320 of 864 version 1.3 october 23, 2012 7.5.18 guest exception syndrome register (gesr) the gesr provides a syndrome to differentiate between the different kinds of exceptions that can generate the same interrupt type for interrupts that ...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 321 of 864 41 /// 0b0 reserved 42 dlk0 0b0 data locking exception 0 1 indicates that a dcbtls, dcbtstls, or dcblc instruction was executed in user mode. 43 dlk1 0b0 data locking exception 1 1 indicates that an...
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User’s manual a2 processor cpu interrupts and exceptions page 322 of 864 version 1.3 october 23, 2012 7.5.19 machine check status register (mcsr) the mcsr contains status to allow the machine check interrupt handler software to determine the cause of a machine check exception. See machine check inte...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 323 of 864 7.6 interrupt definitions table 7-3 provides a summary of each interrupt type in the order corresponding to their associated offset. The table also summarizes the various exception types that can ca...
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User’s manual a2 processor cpu interrupts and exceptions page 324 of 864 version 1.3 october 23, 2012 0x060 data storage read access control x [fp,ap,spv] [epid] write access control x st [fp,ap,spv] [epid] cache locking x [st] {dlk, ilk} byte ordering x bo [st] [fp,ap,spv] [epid] 5 storage synchron...
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User’s manual a2 processor cpu interrupts and exceptions page 326 of 864 version 1.3 october 23, 2012 7.6.1 critical input interrupt a critical input interrupt occurs when no higher priority exception exists, a critical input exception is presented to the interrupt mechanism, and (msr[ce] or msr[gs]...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 327 of 864 programming note: software is responsible for taking any actions that are required by the implementation to clear any critical input exception status (such that the input signal of the critical inpu...
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User’s manual a2 processor cpu interrupts and exceptions page 328 of 864 version 1.3 october 23, 2012 data asynchronous machine check exception a data asynchronous machine check exception is caused when one of the following occurs: • a timeout, read error, or read interrupt request is signaled on th...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 329 of 864 7.6.2.1 machine check status register (mcsr) the mcsr collects status for the machine check exceptions that are handled as asynchronous interrupts: data asynchronous machine check exception or tlb a...
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User’s manual a2 processor cpu interrupts and exceptions page 330 of 864 version 1.3 october 23, 2012 see machine check interrupts on page 296 for more information about the handling of machine check inter- rupts within the a2 core. 7.6.3 data storage interrupt a data storage interrupt might occur w...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 331 of 864 programming note: the instruction cache management instructions icbi and icbt are treated as loads from the addressed byte with respect to address translation and protection. These instruction cache...
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User’s manual a2 processor cpu interrupts and exceptions page 332 of 864 version 1.3 october 23, 2012 virtualization fault exception a virtualization fault exception occurs when a load, store, or cache management instruction attempts to access a location in storage that has the virtualization fault ...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 333 of 864 save/restore register 0 (srr0) set to the effective address of the instruction causing the data storage interrupt. Save/restore register 1 (srr1) set to the contents of the msr at the time of the in...
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User’s manual a2 processor cpu interrupts and exceptions page 334 of 864 version 1.3 october 23, 2012 the following is a prioritized listing of the various exceptions that cause a data storage interrupt and the corre- sponding esr bit, if applicable. Even though multiples of these exceptions can occ...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 335 of 864 execute access control exception an execute access control exception is caused by one of the following: • while in user mode (msr[pr] = 1), an instruction fetch attempts to access a location in stor...
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User’s manual a2 processor cpu interrupts and exceptions page 336 of 864 version 1.3 october 23, 2012 the following is a prioritized listing of the various exceptions that cause a data storage interrupt and the corre- sponding esr bit, if applicable. Even though multiples of these exceptions can occ...
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User’s manual a2 processor cpu interrupts and exceptions page 338 of 864 version 1.3 october 23, 2012 • a floating-point or axu load or store instruction that references a data storage operand that is not aligned on an operand-sized boundary, when xucr0[aflsta]. • an icswx[.] or icswepx[.] instructi...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 339 of 864 illegal instruction exception an illegal instruction exception occurs when execution is attempted of any of the following kinds of instruc- tions: • a reserved-illegal instruction. • an mtspr or mfs...
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User’s manual a2 processor cpu interrupts and exceptions page 340 of 864 version 1.3 october 23, 2012 • an instruction that is disabled: – attn and ccr[en_attn] = 0. – msgsnd or msgclr and ccr2[en_pc] = 0. – icswx or icswepx and ccr2[en_icswx] = 0. • an illegal form of other defined instructions: – ...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 341 of 864 if msr[fe0,fe1] is nonzero when the floating-point enabled exception is presented to the interrupt mecha- nism, a program interrupt occurs, and the interrupt processing registers are updated as desc...
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User’s manual a2 processor cpu interrupts and exceptions page 342 of 864 version 1.3 october 23, 2012 7.6.8 floating-point unavailable interrupt a floating-point unavailable interrupt occurs when no higher priority exception exists, an attempt is made to execute a floating-point instruction that is ...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 343 of 864 7.6.10 auxiliary processor unavailable interrupt an auxiliary processor unavailable interrupt occurs when no higher priority exception exists, an attempt is made to execute an auxiliary processor in...
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User’s manual a2 processor cpu interrupts and exceptions page 344 of 864 version 1.3 october 23, 2012 programming note: software is responsible for clearing the decrementer exception status by writing to tsr[dis] before reenabling msr[ee] to avoid another, redundant decrementer interrupt. 7.6.12 fix...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 345 of 864 programming note: software is responsible for clearing the watchdog timer exception status by writing to tsr[wis] before reenabling msr[ce] to avoid another, redundant watchdog timer interrupt. 7.6....
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User’s manual a2 processor cpu interrupts and exceptions page 346 of 864 version 1.3 october 23, 2012 7.6.15 instruction tlb error interrupt an instruction tlb error interrupt occurs when no higher priority exception exists and an instruction tlb miss exception is presented to the interrupt mechanis...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 347 of 864 mechanism until an attempt is made to execute that instruction. An instruction tlb miss exception occurs when an instruction fetch attempts to access a virtual address for which a valid tlb entry do...
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User’s manual a2 processor cpu interrupts and exceptions page 348 of 864 version 1.3 october 23, 2012 instruction address compare (iac) exception an iac debug exception occurs when execution is attempted of an instruction whose address matches the iac conditions specified by the various debug facili...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 349 of 864 programming note: if icmp debug events are enabled and debug interrupts (previously disabled) are sub- sequently enabled, the icmp debug interrupt occurs sometime after the instruction that enabled ...
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User’s manual a2 processor cpu interrupts and exceptions page 350 of 864 version 1.3 october 23, 2012 for all other cases, when a debug exception occurs, it is immediately presented to the interrupt handling mechanism. A debug interrupt occurs immediately if msr[de] is 1, and the interrupt processin...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 351 of 864 7.6.18 processor doorbell interrupt a processor doorbell interrupt occurs when no higher priority exception exists, a processor doorbell exception is present, and the interrupt is enabled (msr[gs] =...
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User’s manual a2 processor cpu interrupts and exceptions page 352 of 864 version 1.3 october 23, 2012 7.6.19 processor doorbell critical interrupt a processor doorbell critical interrupt occurs when no higher priority exception exists, a processor doorbell critical exception is present, and the inte...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 353 of 864 7.6.21 guest processor doorbell critical interrupt a guest processor doorbell critical interrupt occurs when no higher priority exception exists, a guest processor doorbell critical exception is pre...
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User’s manual a2 processor cpu interrupts and exceptions page 354 of 864 version 1.3 october 23, 2012 7.6.23 embedded hypervisor system call interrupt an embedded hypervisor system call interrupt occurs when no higher priority exception exists and a system call (sc) instruction with lev = 1 is execu...
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0x320. 7.6.25 lra...
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User’s manual a2 processor cpu interrupts and exceptions page 356 of 864 version 1.3 october 23, 2012 7.6.26 user decrementer interrupt a user decrementer interrupt occurs when no higher priority exception exists, a user decrementer exception exists (tsr[udis] = 1), and the interrupt is enabled (tcr...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 357 of 864 programming note: software is responsible for taking any actions that are required by the implementation to clear any performance monitor exception status (such that the performance monitor interrup...
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User’s manual a2 processor cpu interrupts and exceptions page 358 of 864 version 1.3 october 23, 2012 2 guest doorbell interrupt (g_dbell) a guest processor doorbell exception is generated on the processor when the processor has filtered the message based on the payload and has determined that it sh...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 359 of 864 the exception condition remains until a processor doorbell interrupt is taken or an msgclr instruction is executed on the receiving processor with a message type of dbell. A change to any of the fil...
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User’s manual a2 processor cpu interrupts and exceptions page 360 of 864 version 1.3 october 23, 2012 7.7.4 guest doorbell message filtering a processor receiving a g_dbell message type filters the message and either ignores the message or accepts the message and generates a guest processor doorbell...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 361 of 864 if a g_dbell_crit message is received by a processor, the message is accepted if one of the following conditions exist: • the message is for this partition (payload lpidtag = lpidr). • the message i...
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User’s manual a2 processor cpu interrupts and exceptions page 362 of 864 version 1.3 october 23, 2012 if a g_dbell_mc message is received by a processor, the message is accepted if one of the following conditions exist: • the message is for this partition (payload lpidtag = lpidr). • the message is ...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 363 of 864 disables any further asynchronous, noncritical class interrupts (external input, decrementer, user decre- menter, and fixed interval timer) by clearing msr[ee]. Likewise, upon any critical class int...
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User’s manual a2 processor cpu interrupts and exceptions page 364 of 864 version 1.3 october 23, 2012 • execution of any auxiliary processor instructions that are not implemented in the a2 core this prevents auxiliary processor unavailable interrupts. Note that the auxiliary processor instructions t...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 365 of 864 only one of the these types of synchronous interrupts can have an existing exception generating it at any given time. This is guaranteed by the exception priority mechanism (see exception priorities...
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User’s manual a2 processor cpu interrupts and exceptions page 366 of 864 version 1.3 october 23, 2012 nous interrupt types listed in item 1 of interrupt order on page 364. The exception priority mechanism also prevents certain debug exceptions from existing in combination with certain other synchron...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 367 of 864 7.9.2 exception priorities for floating-point load and store instructions the following list identifies the priority order of the exception types that can occur within the a2 core as the result of t...
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User’s manual a2 processor cpu interrupts and exceptions page 368 of 864 version 1.3 october 23, 2012 7.9.4 exception priorities for privileged instructions the following list identifies the priority order of the exception types that can occur within the a2 core as the result of the attempted execut...
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User’s manual a2 processor version 1.3 october 23, 2012 cpu interrupts and exceptions page 369 of 864 6. Embedded system call (system call exception) 7. Debug (icmp exception) because the system call exception does not suppress the execution of the sc instruction, but rather the exception occurs onc...
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User’s manual a2 processor cpu interrupts and exceptions page 370 of 864 version 1.3 october 23, 2012 6. Debug (icmp exception) only applies to the reserved-nop instruction opcodes. 7.9.10 exception priorities for all other instructions the following list identifies the priority order of the excepti...
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User’s manual a2 processor version 1.3 october 23, 2012 fu interrupts and exceptions page 371 of 864 8. Fu interrupts and exceptions an interrupt is the action in which the processor saves its old context (machine state register [msr] and next instruction address [nia]) and begins execution at a pre...
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User’s manual a2 processor fu interrupts and exceptions page 372 of 864 version 1.3 october 23, 2012 8.2 exceptions list book iii-e defines the following floating-point exceptions: • invalid operation exception (vx) • zero divide exception (zx) • overflow exception (ox) • underflow exception (ux) • ...
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User’s manual a2 processor version 1.3 october 23, 2012 fu interrupts and exceptions page 373 of 864 • invalid operation exception (snan) can be set with an invalid operation exception (invalid integer convert) for convert-to-integer instructions. When an exception occurs, instruction execution migh...
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User’s manual a2 processor fu interrupts and exceptions page 374 of 864 version 1.3 october 23, 2012 msr[fe0, fe1] control whether and how enabled exception type of program interrupts are taken when an enabled floating-point exception occurs. An enabled exception type of program interrupt is never t...
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User’s manual a2 processor version 1.3 october 23, 2012 fu interrupts and exceptions page 375 of 864 8.3 floating-point interrupts the following interrupts are taken under the control of the a2 processor core and are not enabled by or reported in fpscr bits: • floating-point unavailable • floating-p...
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User’s manual a2 processor fu interrupts and exceptions page 376 of 864 version 1.3 october 23, 2012 in addition, an invalid operation exception occurs if software explicitly requests this by executing an mtfsf, mtfsfi, or mtfsb1 instruction that sets fpscr[vxsoft] = 1. Programming note: the purpose...
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User’s manual a2 processor version 1.3 october 23, 2012 fu interrupts and exceptions page 377 of 864 when invalid operation exception is disabled (fpscr[ve] = 0) and an invalid operation exception occurs, or software explicitly requests the exception, the following actions are taken: • one or two fp...
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User’s manual a2 processor fu interrupts and exceptions page 378 of 864 version 1.3 october 23, 2012 when a zero divide exception is disabled (fpscr[ze] = 0) and a zero divide occurs, the following actions are taken: • the zero divide exception bit is set. Fpscr zx  1 • fpr(frt)  infinity (the si...
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User’s manual a2 processor version 1.3 october 23, 2012 fu interrupts and exceptions page 379 of 864 – round toward –infinity for negative overflow, store –infinity; for positive overflow, store the largest finite number of the for- mat. • fpr(frt)  result • fpscr[fr]  undefined • fpscr[fi]  1 • ...
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User’s manual a2 processor fu interrupts and exceptions page 380 of 864 version 1.3 october 23, 2012 when underflow exception is disabled (fpscr[ue] = 0) and underflow occurs, the following actions are taken: • the underflow exception bit is set. Fpscr[ux]  1 • fpr(frt)  rounded result • fpscr[fpr...
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User’s manual a2 processor version 1.3 october 23, 2012 fu interrupts and exceptions page 381 of 864 9. Alignment 10. Debug (data address compare, data value compare) 11. Debug (instruction complete) if an instruction causes both a debug (instruction address compare) exception, and a debug (data add...
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User’s manual a2 processor fu interrupts and exceptions page 382 of 864 version 1.3 october 23, 2012 8.8 updating fprs on exceptions the target fpr is never updated on enabled invalid exceptions and enabled divide by zero exceptions. This requirement exists because an instruction can potentially use...
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User’s manual a2 processor version 1.3 october 23, 2012 fu interrupts and exceptions page 383 of 864 table 8-6. Floating-point status and control register (fpscr) (sheet 1 of 3) bits field name description 0:28 reserved note: fpscr[28] is reserved for extension of the drn field; therefore drn can be...
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User’s manual a2 processor fu interrupts and exceptions page 384 of 864 version 1.3 october 23, 2012 40 vxisi floating-point invalid operation exception (  – ) 0 a floating-point invalid operation exception (vxisi) did not occur. 1 a floating-point invalid operation exception (vxisi) occurred. See...
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User’s manual a2 processor version 1.3 october 23, 2012 fu interrupts and exceptions page 385 of 864 8.10 updating the condition register architecturally, excepting floating-point instructions do not block the updating of the condition register in the a2 processor core. 8.10.1 condition register (cr...
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User’s manual a2 processor fu interrupts and exceptions page 386 of 864 version 1.3 october 23, 2012 8.10.2 updating cr fields the floating-point compare instructions fcmpo and fcmpu specify a cr field that is updated with the compare results. Table 8-7 illustrates the bit encodings for a cr field c...
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User’s manual a2 processor version 1.3 october 23, 2012 timer facilities page 387 of 864 9. Timer facilities the a2 core provides five timer facilities: a time base, a decrementer (dec), a user decrementer (udec), a fixed interval timer (fit), and a watchdog timer. These facilities, which share the ...
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User’s manual a2 processor timer facilities page 388 of 864 version 1.3 october 23, 2012 9.1 time base the time base is a 64-bit register that increments once during each period of the source clock and provides a time reference. Access to the time base is via two special purpose registers (sprs). Th...
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User’s manual a2 processor version 1.3 october 23, 2012 timer facilities page 389 of 864 table 9-3. Timebase upper register (tbu) 9.1.1 reading the time base in 64-bit mode, the time base can be read with one instruction. Mfspr ry,tb # read tb into gpr ry. In 32-bit mode, the following code provides...
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User’s manual a2 processor timer facilities page 390 of 864 version 1.3 october 23, 2012 rupt enable or guest state fields of the machine state register (msr[ee] or msr[gs]; see section 7.5.2 machine state register (msr) on page 301). Section 7 cpu interrupts and exceptions on page 293 provides more...
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User’s manual a2 processor version 1.3 october 23, 2012 timer facilities page 391 of 864 using mtspr to force the dec to 0 does not cause a decrementer exception, and thus does not cause tsr[dis] to be set. However, if a time base clock causes a decrement from a dec value of 1 to occur simul- taneou...
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User’s manual a2 processor timer facilities page 392 of 864 version 1.3 october 23, 2012 using mtspr to force the udec to 0 does not cause a user decrementer exception, and thus does not cause tsr[udis] to be set. However, if a time base clock causes a decrement from a udec value of 1 to occur simul...
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User’s manual a2 processor version 1.3 october 23, 2012 timer facilities page 393 of 864 when a fixed interval timer exception occurs, the exception status is recorded by setting the fixed interval timer interrupt status (fis) field of the tsr to 1. A fixed interval timer interrupt occurs if it is e...
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User’s manual a2 processor timer facilities page 394 of 864 version 1.3 october 23, 2012 if tsr[enw,wis] is already 0b11 at the time of the next watchdog timer time-out, the action to take depends on the value of the watchdog reset control (wrc) field of the tcr. If tcr[wrc] is nonzero, then a core ...
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User’s manual a2 processor version 1.3 october 23, 2012 timer facilities page 395 of 864 9.6 timer control register (tcr) the tcr is a privileged spr that controls dec, udec, fit, and watchdog timer operation. The tcr is read into a gpr using mfspr and is written from a gpr using mtspr. The watchdog...
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User’s manual a2 processor timer facilities page 396 of 864 version 1.3 october 23, 2012 bits field name initial value description 32:33 wp 0b00 watchdog timer period specifies one of four bit locations of the time base used to signal a watchdog timer excep- tion on a transition from 0 to 1. 00 2 19...
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User’s manual a2 processor version 1.3 october 23, 2012 timer facilities page 397 of 864 9.7 timer status register (tsr) the tsr is a privileged spr that records the status of dec, udec, fit, and watchdog timer events. The fields of the tsr are generally set to 1 only by hardware and cleared to 0 on...
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User’s manual a2 processor timer facilities page 398 of 864 version 1.3 october 23, 2012 9.9 selection of the timer clock source the source clock of the timers is selected by the timer clock select (tcs) field of execution unit configura- tion register 0 (xucr0). When set to zero, xucr0[tcs] selects...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 399 of 864 10. Debug facilities the debug facilities of the a2 core include support for several debug modes for debugging during hardware and software development, as well as debug events that allow developers to control t...
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User’s manual a2 processor debug facilities page 400 of 864 version 1.3 october 23, 2012 the power isa specification deals only with internal debug mode and the relationship of debug interrupts to the rest of the interrupt architecture. Internal debug mode is the mode that involves debug software ru...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 401 of 864 the pccr0[dba] bits provide options for stopping a thread or all threads on the core. It also allows sending an error signal to external logic from the local fir. If chip clock controls are enabled to stop the c...
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User’s manual a2 processor debug facilities page 402 of 864 version 1.3 october 23, 2012 10.4 debug events there are several different kinds of debug events, each of which is enabled by a field in dbcr0 or dbcr3 (except for the unconditional debug event) and recorded in the dbsr. Debug modes on page...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 403 of 864 10.4.1.1 iac debug event fields several fields in dbcr0 and dbcr1 are used to specify the iac conditions, as follows: iac event enable field dbcr0[iac1, iac2, iac3, iac4] are the individual iac event enables for...
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User’s manual a2 processor debug facilities page 404 of 864 version 1.3 october 23, 2012 supervisor state (msr[pr] = 0). When this field is 0b11, the processor must be operating in user mode (msr[pr] = 1). The iac user/supervisor field value of 0b01 is reserved. If the iac is set to the address bit ...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 405 of 864 10.4.2 data address compare (dac) debug event dac debug events occur when execution is attempted of a load, store, or cache management instruction for which the data storage address and other parameters match th...
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User’s manual a2 processor debug facilities page 406 of 864 version 1.3 october 23, 2012 operating in 32-bit mode (msr[cm] = 0), the addresses are masked to compare only bits 32 through 63. This comparison mode is useful for detecting accesses to a particular byte address, when the accesses can be o...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 407 of 864 entire virtual address that is considered. The process id, which forms the final part of the virtual address, is not considered. Finally, the dac effective/real address field value of 0b01 is reserved, and corre...
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User’s manual a2 processor debug facilities page 408 of 864 version 1.3 october 23, 2012 10.4.2.4 dac debug events applied to various instruction types various special cases apply to the cache management instructions, the store word and doubleword condi- tional indexed (stwcx., stdcx.) instructions,...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 409 of 864 lswx, stswx dac debug events do not occur for lswx or stswx instructions with a length of 0 (xer[si] = 0), because these instructions do not actually access storage. 10.4.3 data value compare (dvc) debug event d...
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User’s manual a2 processor debug facilities page 410 of 864 version 1.3 october 23, 2012 • dac mode only (dbcr2[dvc1m, dvc2m] = 0b00) this mode enables dac1 and dac2 compare events providing the respective dbcr0 and dbcr2 dac settings result in a match condition. In this mode, the corresponding dbcr...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 411 of 864 10.4.3.4 dvc debug events applied to various instruction types various special cases apply to the cache management instructions, the store word and doubleword condi- tional indexed (stwcx., stdcx.) instruction, ...
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User’s manual a2 processor debug facilities page 412 of 864 version 1.3 october 23, 2012 10.4.5 branch taken (brt) debug event brt debug events occur when brt debug events are enabled (dbcr0[brt] = 1), debug interrupts are enabled (msr[de] = 1), and execution is attempted of a branch instruction for...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 413 of 864 when enabled, the occurrence of a ret debug event is recorded in dbsr[ret]. If debug interrupts are not enabled (msr[de] = 0), the imprecise debug event (dbsr[ide]) bit is also set. The resulting actions taken b...
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User’s manual a2 processor debug facilities page 414 of 864 version 1.3 october 23, 2012 10.4.9 unconditional debug event (ude) ude debug events occur when a debug tool asserts the unconditional debug event request via the scom- accessible thrctl[ude] bit. The ude debug event is the only event that ...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 415 of 864 10.4.11 debug event summary table 10-3 summarizes each of the debug event types, and the effect of the debug modes and msr[de] on their occurrence. 10.5 debug reset software can initiate an immediate reset opera...
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User’s manual a2 processor debug facilities page 416 of 864 version 1.3 october 23, 2012 that all preceding instructions use the old values of the registers, and that all succeeding instructions use the new values. In addition, when changing any of the debug facility register fields related to the d...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 417 of 864 41 iac2 0b0 instruction address compare 2 debug event enable 0 iac2 debug events cannot occur. 1 iac2 debug events can occur. 42 iac3 0b0 instruction address compare 3 debug event enable 0 iac3 debug events cann...
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User’s manual a2 processor debug facilities page 418 of 864 version 1.3 october 23, 2012 10.7.2 debug control register 1 (dbcr1) dbcr1 is an spr that is used to configure iac debug events. Dbcr1 can be written from a gpr using mtsp and can be read into a gpr using mfspr. Register short name: dbcr1 r...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 419 of 864 10.7.3 debug control register 2 (dbcr2) dbcr2 is an spr that is used to configure dac and dvc debug events. Dbcr2 can be written from a gpr using mtspr and can be read into a gpr using mfspr. 50:51 iac3er 0b00 i...
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User’s manual a2 processor debug facilities page 420 of 864 version 1.3 october 23, 2012 34:35 dac1er 0b00 data address compare 1 effective/real mode 00 effective: dac1 debug events are based on effective addresses. 01 not implemented. 10 effective ds0: dac1 debug events are based on effective addre...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 421 of 864 10.7.4 debug control register 3 (dbcr3) dbcr3 is an spr that is used to configure dac and dvc debug events and to enable ivc debug events. Dbcr3 can be written from a gpr using mtspr and can be read into a gpr u...
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User’s manual a2 processor debug facilities page 422 of 864 version 1.3 october 23, 2012 10.7.5 debug status register (dbsr) the dbsr contains the status of debug events and information about the type of the most recent reset. The status bits are set by the occurrence of debug events, while the rese...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 423 of 864 10.7.6 debug status register write register (dbsrwr) the dbsrwr is a write only register with the same format as the dbsr. It can be used to set the corre- sponding dbsr bit when running in the hypervisor state ...
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User’s manual a2 processor debug facilities page 424 of 864 version 1.3 october 23, 2012 33 ude 0b0 unconditional debug event sets corresponding dbsr bit. 34:35 mrr 0b00 most recent reset sets corresponding dbsr bit. 36 icmp 0b0 instruction complete debug event sets corresponding dbsr bit. 37 brt 0b...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 425 of 864 10.7.7 instruction address compare registers (iac1–iac4) the four iac registers specify the addresses upon which iac debug events should occur. Each of the iac registers can be written from a gpr using mtspr, an...
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User’s manual a2 processor debug facilities page 426 of 864 version 1.3 october 23, 2012 10.7.8 data address compare registers (dac1–dac2) the four dac registers specify the addresses upon which dac debug events, or dvc debug events, or both should occur. Each of the dac registers can be written fro...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 427 of 864 10.7.9 data value compare registers (dvc1–dvc2) the dvc registers specify the data values upon which dvc debug events should occur. Each of the dvc registers can be written from a gpr using mtspr and can be read...
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User’s manual a2 processor debug facilities page 428 of 864 version 1.3 october 23, 2012 10.7.10 instruction address register (iar) the iar indicates the address of the current instruction at the completion point, or of the last instruction that has passed the completion point. Initial value: 0x0000...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 429 of 864 10.7.11 instruction match mask registers (immr) the imr and immr registers are used together to specify bits compared against an instruction, to determine if an instruction value compare (ivc) debug event should...
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User’s manual a2 processor debug facilities page 430 of 864 version 1.3 october 23, 2012 the ramd register receives the results of any rammed instruction. The rami register specifies the 32-bit ram instruction field. The ramc register provides control and status over all ram activity. Ramc register ...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 431 of 864 can be disabled by setting pccr0, bit 36 active (see section 15.3.8 pc configuration register 0 (pccr0) on page 725). 9. Entering ram mode does not fence interrupts. If disabling interrupts is required, the user...
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User’s manual a2 processor debug facilities page 432 of 864 version 1.3 october 23, 2012 32 ram instruction tgt1 field extension 0 provides the highest order bit of the tgt1 field when using ucode rom scratch register as the instruction target. 33 ram instruction src1 field extension 0 provides the ...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 433 of 864 53 msr[de] override 0 along with msr override enable, determines if debug interrupts are enabled for the thread. It replaces the msr output, but does not alter the actual register bit. Note: ram operations must ...
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User’s manual a2 processor debug facilities page 434 of 864 version 1.3 october 23, 2012 10.8.3 example ram mode procedures 10.8.3.1 spr read/write using gpr as temporary storage this section shows the process for stopping a thread, enabling ram operations, and performing an spr access through ramme...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 435 of 864 4. Write msr with new value. • clear r1 [scom write ramc instr = “li r1, 0”]; verify ram status. • write new msr(32:47) to r1 [scom write ramic instr = “oris r1, r1, msr(32:47)”]; verify ram sta- tus. • write ne...
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User’s manual a2 processor debug facilities page 436 of 864 version 1.3 october 23, 2012 it is valid to set a ramc(32:35) bit active when the corresponding target or source register is not used in the rammed instruction. The unused target/source fields are ignored by the hardware. This allows settin...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 437 of 864 some examples of problem instructions while in ram mode are: • branches. Next instruction will not come from the branch target address. • return from interrupts. Next instruction will not come from the associate...
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User’s manual a2 processor debug facilities page 438 of 864 version 1.3 october 23, 2012 #recover xudbg1 data 10.9.2 instruction unit debug register 0 (iudbg0) scom write rami  xori rx, rx, 0 #xudbg1 on slowspr bus; requires second ram operation scom write ramc  0x000x0000 #set ram mode; ram threa...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 439 of 864 10.9.3 instruction unit debug register 1 (iudbg1) 10.9.4 instruction unit debug register 2 (iudbg2) register short name: iudbg1 read access: hypv decimal spr number: 889 write access: none initial value: 0x00000...
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User’s manual a2 processor debug facilities page 440 of 864 version 1.3 october 23, 2012 10.9.5 execution unit debug register 0 (xudbg0) 10.9.6 execution unit debug register 1 (xudbg1) register short name: xudbg0 read access: hypv decimal spr number: 885 write access: hypv initial value: 0x000000000...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 441 of 864 10.9.7 execution unit debug register 2 (xudbg2) 10.10 thread control and status the scom-accessible thread control and status register (thrctl) allows debug control of thread opera- tions such as start/stop, sin...
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User’s manual a2 processor debug facilities page 442 of 864 version 1.3 october 23, 2012 thread activity is indicated by the tx_run and tx_pm status bits. Tx_run indicates that the thread is active when set and indicates stopped when cleared. Tx_pm, when set, indicates that a thread has been stopped...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 443 of 864 10.10.1 using thrctl register to stop thread 0 1. Scom write to thrctl(32) to set the t0_stop bit. 2. Scom read to thrctl(40) to verify t0_run bit is ‘0’. 3. At this point, access to thread sprs and gprs is avai...
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User’s manual a2 processor debug facilities page 444 of 864 version 1.3 october 23, 2012 10.11 pc configuration register 0 (pccr0) the pc unit includes a register for miscellaneous configuration and control functions. The pc configuration register 0 (pccr0), is a scom-accessible register with read/w...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 445 of 864 10.12 trace and trigger bus an 88-bit debug bus is brought out of the core for use by a trace array or other debug functions implemented at the chip level. A 12-bit bus providing trace trigger information is als...
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User’s manual a2 processor debug facilities page 446 of 864 version 1.3 october 23, 2012 bit 32 of pc configuration register 0 provides an enable for the trace and trigger bus logic in all units and is connected to the act pin on the trace and trigger bus latches. In this way, they initialize to a n...
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User’s manual a2 processor version 1.3 october 23, 2012 debug facilities page 447 of 864 10.12.3 debug select registers each 32-bit scom accessible debug select register can control up to two debug multiplexer components. The debug multiplexer controls for core units are split up as follows: • abdsr...
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User’s manual a2 processor debug facilities page 448 of 864 version 1.3 october 23, 2012.
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User’s manual a2 processor version 1.3 october 23, 2012 performance events and event selection page 449 of 864 11. Performance events and event selection an 8-bit event bus is brought out of the core for use by an external performance monitor unit implemented at the chiplet level. Within the core, e...
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User’s manual a2 processor performance events and event selection page 450 of 864 version 1.3 october 23, 2012 11.2 a2 core event bus and pc unit controls this section describes the core event select register and core event multiplexer functions. The cesr contains various control bits that select di...
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User’s manual a2 processor version 1.3 october 23, 2012 performance events and event selection page 451 of 864 additionally, performance events from the lsu, iu, mmu, and fu are driven out of the core on separate inter- faces, thereby bypassing the core event multiplexer. In this way, the performanc...
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User’s manual a2 processor performance events and event selection page 452 of 864 version 1.3 october 23, 2012 11.2.4 core event select register (cesr) register short name: cesr read access: priv decimal spr number: 912 write access: priv initial value: 0x0000000000000000 duplicated for multithread:...
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User’s manual a2 processor version 1.3 october 23, 2012 performance events and event selection page 453 of 864 43:45 seleb1 0b000 select signal driven on ac_an_event_bus(1) 000 xu_pc_event_bits(1) 001 iu_pc_event_bits(1) 010 fu_pc_event_bits(1) 011 mm_pc_event_bits(1) 100 lsu_pc_event_bits(1) 101 xu...
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User’s manual a2 processor performance events and event selection page 454 of 864 version 1.3 october 23, 2012 11.3 unit level performance event selection 11.3.1 unit event multiplexer component each unit includes one or more event multiplexer components for selecting local performance events. The u...
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User’s manual a2 processor version 1.3 october 23, 2012 performance events and event selection page 455 of 864 in summary, each a2 unit implements the following performance event multiplexer components: see section 11.5.1 through section 11.5.5 for descriptions of each unit’s event select registers....
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User’s manual a2 processor performance events and event selection page 456 of 864 version 1.3 october 23, 2012 11.3.2 performance monitor event tags and count modes in the following sections, performance event tables for each unit are included that describe each event and how they are selected by th...
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User’s manual a2 processor version 1.3 october 23, 2012 performance events and event selection page 457 of 864 the event tags and count modes are summarized in table 11-2. Cycle counting refers to counting the number of cycles a performance monitor signal is active or inactive. Event counting refers...
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User’s manual a2 processor performance events and event selection page 458 of 864 version 1.3 october 23, 2012 11.4 unit performance event tables 11.4.1 fu performance events table 11.4.2 iu performance events table table 11-3. Fu performance events table (use aesr for corresponding multiplexer sele...
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User’s manual a2 processor version 1.3 october 23, 2012 performance events and event selection page 459 of 864 i-cache fetch (b) number of times i-cache read completes for instruction. • does not count if flushed before iu2. • counts whether cache hit or miss. • can only occur on one thread per cycl...
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User’s manual a2 processor performance events and event selection page 460 of 864 version 1.3 october 23, 2012 11.4.3 xu performance events table fxu issue priority loss (c) cycle count for fxu instruction that is valid in issue and another thread issues because it has priority (see is2 stall for co...
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User’s manual a2 processor version 1.3 october 23, 2012 performance events and event selection page 461 of 864 xu commit (c) number of xu instructions committed. Every instruction of the microcode sequence is counted. No any 10 ucode commit (s) number of microcode sequences committed. No any 11 any ...
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User’s manual a2 processor performance events and event selection page 462 of 864 version 1.3 october 23, 2012 11.4.4 lsu performance events table table 11-6. Lsu performance events table (sheet 1 of 3) (use xesr3 and xesr4 for corresponding multiplexer selects) note: see the unit performance events...
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User’s manual a2 processor version 1.3 october 23, 2012 performance events and event selection page 463 of 864 committed axu loads (v) number of completed axu loads. Axu refers to the unit attached on the axu interface (that is, a floating-point unit). • cacheable and cache-inhibited loads are count...
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User’s manual a2 processor performance events and event selection page 464 of 864 version 1.3 october 23, 2012 store queue full flush (v) number of flushes due to the store queue being full or a sync, mbar, or tlbsync instruction hits against an outstanding load for the issuing thread. • this is a s...
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User’s manual a2 processor version 1.3 october 23, 2012 performance events and event selection page 465 of 864 11.4.5 mmu performance events table table 11-7. Mmu performance events table (sheet 1 of 2) (use mesr1 and mesr2 for corresponding multiplexer selects) note: see the unit performance events...
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User’s manual a2 processor performance events and event selection page 466 of 864 version 1.3 october 23, 2012 11.5 unit event select registers 11.5.1 fu event select register (aesr) tlbivax_local_source_total(e) tlbivax invalidations sourced total (sourced tlbivax on this core total). Yes 3 13 tlbi...
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User’s manual a2 processor version 1.3 october 23, 2012 performance events and event selection page 467 of 864 41:43 muxseleb2 0b000 multiplexer event_bits[2] 2:1 multiplexer select determines which 2:1 multiplexer is gated for driving bit 2 of the event multiplexer (fu_pc_event_bits[2]). Decoded va...
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User’s manual a2 processor performance events and event selection page 468 of 864 version 1.3 october 23, 2012 11.5.2 iu event select registers register short name: iesr1 read access: priv decimal spr number: 914 write access: priv initial value: 0x0000000000000000 duplicated for multithread: n slow...
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User’s manual a2 processor version 1.3 october 23, 2012 performance events and event selection page 469 of 864 register short name: iesr2 read access: priv decimal spr number: 915 write access: priv initial value: 0x0000000000000000 duplicated for multithread: n slow spr: y notes: guest supervisor m...
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User’s manual a2 processor performance events and event selection page 470 of 864 version 1.3 october 23, 2012 11.5.3 xu event select registers register short name: xesr1 read access: priv decimal spr number: 918 write access: priv initial value: 0x0000000000000000 duplicated for multithread: n slow...
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User’s manual a2 processor version 1.3 october 23, 2012 performance events and event selection page 471 of 864 register short name: xesr2 read access: priv decimal spr number: 919 write access: priv initial value: 0x0000000000000000 duplicated for multithread: n slow spr: y notes: guest supervisor m...
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User’s manual a2 processor performance events and event selection page 472 of 864 version 1.3 october 23, 2012 11.5.4 lsu event select registers register short name: xesr3 read access: priv decimal spr number: 920 write access: priv initial value: 0x0000000000000000 duplicated for multithread: n slo...
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User’s manual a2 processor version 1.3 october 23, 2012 performance events and event selection page 473 of 864 register short name: xesr4 read access: priv decimal spr number: 921 write access: priv initial value: 0x0000000000000000 duplicated for multithread: n slow spr: y notes: guest supervisor m...
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User’s manual a2 processor performance events and event selection page 474 of 864 version 1.3 october 23, 2012 11.5.5 mmu event select registers register short name: mesr1 read access: priv decimal spr number: 916 write access: priv initial value: 0x0000000000000000 duplicated for multithread: n slo...
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User’s manual a2 processor version 1.3 october 23, 2012 performance events and event selection page 475 of 864 register short name: mesr2 read access: priv decimal spr number: 917 write access: priv initial value: 0x0000000000000000 duplicated for multithread: n slow spr: y notes: guest supervisor m...
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User’s manual a2 processor performance events and event selection page 476 of 864 version 1.3 october 23, 2012 11.6 a2 support for core instruction trace core instruction tracing allows chip level facilities to collect instruction address information over extended periods of time and store it out in...
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User’s manual a2 processor version 1.3 october 23, 2012 performance events and event selection page 477 of 864 11.6.3 instruction trace record formats and ordering the first instruction trace record includes the opcode field, a unique data pattern, and other control signals that enable the htm and p...
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User’s manual a2 processor performance events and event selection page 478 of 864 version 1.3 october 23, 2012 11.6.4 debug bus control when in instruction trace mode with each unit’s debug select registers in the pass-through state, the xu and axu can control placement of data and control signals o...
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User’s manual a2 processor version 1.3 october 23, 2012 performance events and event selection page 479 of 864 11.6.4.1 fu trace records • upon entering instruction trace mode, the fu continuously drives out on the debug bus the xabcde data pattern, and 0s for the encoded trace record type (the only...
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User’s manual a2 processor performance events and event selection page 480 of 864 version 1.3 october 23, 2012 at the chiplet level, the pmu logic writes the address data to per-thread siar registers. Upon a counter over- flow, the affected thread’s siar stops updating, thereby freezing the last add...
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User’s manual a2 processor version 1.3 october 23, 2012 implementation dependent instructions page 481 of 864 12. Implementation dependent instructions this chapter describes all the a2 core instructions implemented that are not part of power isa or that are implementation dependent. 12.1 miscellane...
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User’s manual a2 processor implementation dependent instructions page 482 of 864 version 1.3 october 23, 2012 12.2 tlb management instructions 12.2.1 tlb read entry (tlbre) software must use the tlbre instruction to read entries from the tlb or lrat. This instruction is embedded hypervisor privilege...
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User’s manual a2 processor version 1.3 october 23, 2012 implementation dependent instructions page 483 of 864 mas3 rpnl[44:51] 0 mas3 u0:u3 ux sx uw sw ur sr 0 0 0 0 0 0 0 mas7 rpnu rpn 22:31 mas8 tgs vf 0 0 mas8 tlpid  entry lpid mmucr3 x entry x mmucr3 r c ecl tid_nz class wlc resvattr ...
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User’s manual a2 processor implementation dependent instructions page 484 of 864 version 1.3 october 23, 2012 12.2.2 tlb write entry (tlbwe) software must use the tlbwe instruction to write entries into either the tlb or lrat. This instruction is super- visor privileged. Because this instruction rel...
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mas3 rpnl[32:43] entry lpid  mas8 tlpid entry x mmucr3 ...
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User’s manual a2 processor implementation dependent instructions page 486 of 864 version 1.3 october 23, 2012 12.2.3 tlb search indexed (tlbsx[.]) software must use the tlbsx[.] instruction to search entries in the tlb (searching the lrat is not supported in this implementation). This instruction is...
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User’s manual a2 processor version 1.3 october 23, 2012 implementation dependent instructions page 487 of 864 mas1 iprot tid ts tsize  entry iprot tid ts size mas1 ind  entry ind mas2 epn w i m g e  entry epn w i m g e if entry ind = 1 mas3 spsize0 spsize1 spsize2 spsize3 spsize4 und  entry spsi...
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User’s manual a2 processor implementation dependent instructions page 488 of 864 version 1.3 october 23, 2012 12.2.4 tlb search and reserve indexed (tlbsrx.) software can use the tlbsrx. Instruction to search for entries in the local tlb and, as a side-affect, sets a local tlb reservation for the as...
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User’s manual a2 processor implementation dependent instructions page 490 of 864 version 1.3 october 23, 2012 12.2.5 tlb invalidate virtual address indexed (tlbivax) software can use the tlbivax instruction to invalidate entries in the tlb (and associated copies in the erats). The tlbivax instructio...
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User’s manual a2 processor version 1.3 october 23, 2012 implementation dependent instructions page 491 of 864 (entry[ts] = ts) and (entry[tid] = tid) and (entry[size]) = size) and (entry[ind] = ind) and (entry[iprot] = 0) then entry[v] 0 for each erat entry n  64-log 2 (entry page size in bytes) if...
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User’s manual a2 processor implementation dependent instructions page 492 of 864 version 1.3 october 23, 2012 • the x value of the erat entry is 0, or epn n:51 is greater than the value of the entry epn n:51 , where n equals 64 - log 2 (entry page size in bytes). • the tgs value of the erat entry is...
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User’s manual a2 processor version 1.3 october 23, 2012 implementation dependent instructions page 493 of 864 12.2.6 tlb invalidate local indexed (tlbilx) software can use the tlbilx instruction to invalidate entries in the local tlb (and associated copies in the local erat structures). The “c” para...
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User’s manual a2 processor version 1.3 october 23, 2012 implementation dependent instructions page 495 of 864 • the tid_nz bit value of the erat entry (does not apply to tlb entries) matches the logical or of all bits of mas6 spid(0:13). • the ts value of the entry is equal to mas6 sas . • for tlb e...
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User’s manual a2 processor implementation dependent instructions page 496 of 864 version 1.3 october 23, 2012 12.3 erat management instructions 12.3.1 erat read entry (eratre) software must use the eratre instruction to read entries from either erat. The eratre instruction relies on the mmucr0[tlbse...
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User’s manual a2 processor version 1.3 october 23, 2012 implementation dependent instructions page 497 of 864 the contents of the selected erat entry is placed into register rt (and possibly into mmucr0[tgs, ts, tid, and ecl]). Mmucr0[tlbsel] is used as the source structure selection for this instru...
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User’s manual a2 processor implementation dependent instructions page 498 of 864 version 1.3 october 23, 2012 rt[60:61]  uw,sw rt[62:63]  ur,sr if ws = 3 (lru portion), mmucr0[tlbsel] = 2 or 3 (i-erat or d-erat selected), and mmucr1[irre] = 0 for i-erat or mmucr1[drre] = 0 for d-erat: rt[0:51]  “...
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User’s manual a2 processor version 1.3 october 23, 2012 implementation dependent instructions page 499 of 864 12.3.2 erat write entry (eratwe) software must use the eratwe instruction to write entries into either erat. The eratwe instruction relies on the mmucr0[tlbsel] to determine on which hardwar...
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User’s manual a2 processor implementation dependent instructions page 500 of 864 version 1.3 october 23, 2012 d-erat ws0 [(entry)].Thdid (mmucr0[tid 52:55 ]) when mmucr1[dttid] = 1 else (rs 60:63 ) d-erat ws0 [(entry)].Tgs (mmucr0[tgs]) d-erat ws0 [(entry)].Ts (mmucr0[ts]) d-erat ws0 [(entry)].Tid (...
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User’s manual a2 processor version 1.3 october 23, 2012 implementation dependent instructions page 501 of 864 tid[0:7]  mmucr0[tid 56:63 ] tid_nz  mmucr0[tid_nz] extclass  mmucr0[ecl] unused  rpnreg[0:7] wlc[0:1]  rpnreg[8:9] resvattr  rpnreg[10] unused  rpnreg[11] u[0:3]  rpnreg[12:15] r  ...
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User’s manual a2 processor implementation dependent instructions page 502 of 864 version 1.3 october 23, 2012 12.3.3 erat search indexed (eratsx[.]) software must use the eratsx[.] instruction to search the entries in either erat. The eratsx[.] instruction relies on the mmucr0[tlbsel] field to deter...
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User’s manual a2 processor version 1.3 october 23, 2012 implementation dependent instructions page 503 of 864 else if mmucr0[tlbsel] = 3 then if exactly one valid, matching entry with all of the following properties: 1. Entry[tgs] = mmucr0[tgs] 2. Entry[ts] = mmucr0[ts] 3. Entry[tid] = mmucr0[tid56:...
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User’s manual a2 processor implementation dependent instructions page 504 of 864 version 1.3 october 23, 2012 12.3.4 erat invalidate virtual address indexed (erativax) software must use the erativax instruction to globally invalidate entries in the erats while operating in erat-only mode (ccr2[notlb...
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User’s manual a2 processor version 1.3 october 23, 2012 implementation dependent instructions page 505 of 864 for each processor in the logical partition for each erat entry n  64-log 2 (entry page size in bytes) if {(is = “11”) and (entry[epn w:63-p ] = epn w:63-p ) and (entry[x] = 0 or epn n:51 >...
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User’s manual a2 processor implementation dependent instructions page 506 of 864 version 1.3 october 23, 2012 • the 3-bit size value of the erat entry is equal to the 3-bit interpretation of the 4-bit rs 60:63 . • the extclass value of the erat entry is 0. This implementation requires the direct tar...
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User’s manual a2 processor version 1.3 october 23, 2012 implementation dependent instructions page 507 of 864 12.3.5 erat invalidate local indexed (eratilx) software can use the eratilx instruction to invalidate entries in the local processor’s erat structures. The eratilx invalidations are not broa...
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User’s manual a2 processor implementation dependent instructions page 508 of 864 version 1.3 october 23, 2012 • the tid_nz value of the entry matches the logical or of all bits of mmucr0 tid(0:13) . • the extclass of the entry is 0. If t = 2, all erat entries that have all of the following propertie...
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User’s manual a2 processor version 1.3 october 23, 2012 implementation dependent instructions page 509 of 864 12.4 software transactional memory instructions support is provided for three problem-state instructions. The following notation assumes the existence of an extra bit per hardware thread per...
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xerso ea.Watchbit  1 el...
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User’s manual a2 processor version 1.3 october 23, 2012 implementation dependent instructions page 511 of 864 12.4.2 watch check all x-form (wchkall) wchkall bf this instruction probes the watch monitoring facility, which maintains a watchlost sticky bit, to check whether any watches have been lost,...
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User’s manual a2 processor implementation dependent instructions page 512 of 864 version 1.3 october 23, 2012 12.4.3 watch clear x-form (wclr) wclr l, ra, rb if ra = 0 then b  0 elseb  (ra) ea  b + (rb) if l[0] == 0 then reset all watches for thread to 0 watchlost  l[1] else watchbit(ea)  0 thi...
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User’s manual a2 processor version 1.3 october 23, 2012 implementation dependent instructions page 513 of 864 a ldawx by a processor p1 is performed with respect to any processor or mechanism p2 when the value and watchbit to be returned by the ldawx can no longer be changed by an operation by p2. A...
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User’s manual a2 processor implementation dependent instructions page 514 of 864 version 1.3 october 23, 2012 the instruction that initiates a coprocessor is normally a problem-state instruction. However, the definition also provides a higher-privileged instruction to assist a privileged-state or hy...
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User’s manual a2 processor version 1.3 october 23, 2012 implementation dependent instructions page 515 of 864 12.5.1 initiate coprocessor store word indexed (icswx[.]) initiation of a coprocessor is requested by issuing the initiate coprocessor store word indexed (icswx) instruction. Initiate coproc...
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User’s manual a2 processor implementation dependent instructions page 516 of 864 version 1.3 october 23, 2012 mem(ea,4)  ccw 0:31 ; signal coprocessor signal ( mem(b,64),crb 0:63 pid, lpid) ; set cr0 if necessary if (rc == 1) thenif setting cr0 if (available) then cr0  0b1000initiated or negative ...
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User’s manual a2 processor version 1.3 october 23, 2012 implementation dependent instructions page 517 of 864 ra and rb the address of a coprocessor-request block (crb) is located on a 128-byte boundary; otherwise, an align- ment interrupt is recognized. Before signaling a coprocessor, the icswx ins...
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User’s manual a2 processor implementation dependent instructions page 518 of 864 version 1.3 october 23, 2012 12.5.2 initiate coprocessor store word external process id indexed (icswepx[.]) initiation of a coprocessor is requested by issuing the initiate coprocessor store word external process id in...
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User’s manual a2 processor version 1.3 october 23, 2012 implementation dependent instructions page 519 of 864 after successfully initiated (cr0 bit 0 is 1), execution of a function completes asynchronously. See the copro- cessor architecture for details. Programming note: the icswx instruction is tr...
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User’s manual a2 processor implementation dependent instructions page 520 of 864 version 1.3 october 23, 2012 12.5.4 coprocessor-request block a coprocessor-request block (crb) must be located on a 128-byte boundary; otherwise, the icswx instruc- tion specifying such an unaligned crb recognizes an a...
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User’s manual a2 processor version 1.3 october 23, 2012 implementation dependent instructions page 521 of 864 1. When any bit for a specific coprocessor type (ct) is set to 1, the bit position for the full-broadcast ct must also be set to 1 to also enable the broadcast coprocessor type; otherwise, a...
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User’s manual a2 processor implementation dependent instructions page 522 of 864 version 1.3 october 23, 2012 programming notes: 1. When any bit for a regular coprocessor type (ct) is set to 1, the bit position for the broadcast ct must also be set to 1 to enable the broadcast coprocessor type; othe...
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User’s manual a2 processor version 1.3 october 23, 2012 implementation dependent instructions page 523 of 864 12.6 data cache block flush the a2 supports data cache block flush with l = 0,1 or 3. 12.6.1 data cache block flush (dcbf) data cache block flush x-form dcbf ra,rb,l let the ea be the sum (r...
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User’s manual a2 processor implementation dependent instructions page 524 of 864 version 1.3 october 23, 2012 extended mnemonics: extended mnemonics are provided for the data cache block flush instruction so that it can be coded with the l value as part of the mnemonic rather than as a numeric opera...
Page 525
User’s manual a2 processor version 1.3 october 23, 2012 power management methods page 525 of 864 13. Power management methods 13.1 chip power management controls power management logic and clock controls external to the core can force a thread to a stopped state, or bring about deeper levels of powe...
Page 526
User’s manual a2 processor power management methods page 526 of 864 version 1.3 october 23, 2012 3. Pm_rvw state • ccr0[pme] = pm_rvw_enable and all four threads have set their respective ccr0[we] bits. • the a2 activates run tholds to stop clocks for power savings. Requests from the a2/l2 interface...
Page 527
User’s manual a2 processor version 1.3 october 23, 2012 power management methods page 527 of 864 5. After the ac_an_rvwinkle_mode signal has been asserted, the l2 can take additional actions in prepara- tion for chip power down. Further power-savings actions can be taken by stopping all core clocks ...
Page 528
User’s manual a2 processor power management methods page 528 of 864 version 1.3 october 23, 2012.
Page 529
User’s manual a2 processor version 1.3 october 23, 2012 register summary page 529 of 864 14. Register summary this chapter provides an alphabetical listing of and bit definitions for the registers contained in the a2 core. The five types of registers are grouped into several functional categories ac...
Page 530
User’s manual a2 processor register summary page 530 of 864 version 1.3 october 23, 2012 table 14-1. Register summary (sheet 1 of 5) r egister mn emonic spr n u mber minim u m mt s p r acces s minim u m mf s p r acces s access mapped to register mu ltithrea ded slo w spr scan ring fu ll n a me bef o...
Page 531
User’s manual a2 processor version 1.3 october 23, 2012 register summary page 531 of 864 epcr 307 hypv hypv n y n func embedded processor control register none csi none none hm eplc 947 priv priv n y y func external process id load context none csi none none hm epsc 948 priv priv n y y func external...
Page 532
User’s manual a2 processor register summary page 532 of 864 version 1.3 october 23, 2012 iucr2 884 hypv hypv n y y ccfg instruction unit configuration register 2 none csi none none iudbg0 888 hypv hypv n n y func instruction unit debug register 0 qui- esce none none none iudbg1 889 none hypv n n y f...
Page 533
User’s manual a2 processor version 1.3 october 23, 2012 register summary page 533 of 864 mcsrr1 571 hypv hypv n y n func machine check save/restore register 1 none none none none am mesr1 916 priv priv n n y func mmu event select register 1 sr sr sr sr mesr2 917 priv priv n n y func mmu event select...
Page 534
User’s manual a2 processor register summary page 534 of 864 version 1.3 october 23, 2012 tbl 284 hypv none n n n func timebase lower none none none none tbu 285/269 hypv/none none/any n n n func timebase upper none none none none tcr 340 hypv hypv n y n func timer control register none none none non...
Page 535
User’s manual a2 processor version 1.3 october 23, 2012 register summary page 535 of 864 1. Dbsr, mcsr, and tsr have read/clear access. These three registers are status registers, and as such behave differently than other sprs when written. The term “read/clear” does not mean that these regis- ters ...
Page 536
User’s manual a2 processor register summary page 536 of 864 version 1.3 october 23, 2012.
Page 537
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 537 of 897 14.5 alphabetical register listing the following pages list the registers available in the a2 core. For each register, the following information is supplied: • register mnemonic and name • register ...
Page 538
User’s manual a2 processor alphabetical register listing page 538 of 897 version 1.3 october 23, 2012 14.5.1 acop - available coprocessor register short name: acop read access: priv decimal spr number: 31 write access: priv initial value: 0x0000000000000000 duplicated for multithread: y slow spr: n ...
Page 539
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 539 of 897 14.5.2 aesr - axu event select register register short name: aesr read access: priv decimal spr number: 913 write access: priv initial value: 0x0000000000000000 duplicated for multithread: n slow sp...
Page 540
User’s manual a2 processor alphabetical register listing page 540 of 897 version 1.3 october 23, 2012 49:51 muxseleb4 0b000 multiplexer event_bits[4] 2:1 multiplexer select determines which 2:1 multiplexer is gated for driving bit 4 of the event multiplexer (fu_pc_event_bits[4]). Decoded values sele...
Page 541
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 541 of 897 14.5.3 ccr0 - core configuration register 0 register short name: ccr0 read access: hypv decimal spr number: 1008 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: n sl...
Page 542
User’s manual a2 processor alphabetical register listing page 542 of 897 version 1.3 october 23, 2012 14.5.4 ccr1 - core configuration register 1 register short name: ccr1 read access: hypv decimal spr number: 1009 write access: hypv initial value: 0x000000000f0f0f0f duplicated for multithread: n sl...
Page 543
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 543 of 897 14.5.5 ccr2 - core configuration register 2 register short name: ccr2 read access: hypv decimal spr number: 1010 write access: hypv initial value: 0x0000000000000001 duplicated for multithread: n sl...
Page 544
User’s manual a2 processor alphabetical register listing page 544 of 897 version 1.3 october 23, 2012 55 ucode_dis 0b0 microcode disable 0 enable microcode (normal operation). 1 disable microcode. (all microcoded instructions cause an unimplemented opera- tion type of program interrupt.) 56:59 ap 0b...
Page 545
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 545 of 897 14.5.6 ccr3 - core configuration register 3 register short name: ccr3 read access: hypv decimal spr number: 1013 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: y sl...
Page 546
User’s manual a2 processor alphabetical register listing page 546 of 897 version 1.3 october 23, 2012 14.5.7 cesr - core event select register register short name: cesr read access: priv decimal spr number: 912 write access: priv initial value: 0x0000000000000000 duplicated for multithread: n slow s...
Page 547
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 547 of 897 43:45 seleb1 0b000 select signal driven on ac_an_event_bus(1) 000 xu_pc_event_bits(1) 001 iu_pc_event_bits(1) 010 fu_pc_event_bits(1) 011 mm_pc_event_bits(1) 100 lsu_pc_event_bits(1) 101 xu_pc_event...
Page 548
User’s manual a2 processor alphabetical register listing page 548 of 897 version 1.3 october 23, 2012 58:60 seleb6 0b000 select signal driven on ac_an_event_bus(6) 000 xu_pc_event_bits(6) 001 iu_pc_event_bits(6) 010 fu_pc_event_bits(6) 011 mm_pc_event_bits(6) 100 lsu_pc_event_bits(6) 101 xu_pc_event...
Page 549
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 549 of 897 14.5.8 cr - condition register register short name: cr read access: any decimal spr number: n/a write access: any initial value: 0x0000000000000000 duplicated for multithread: y slow spr: n notes: g...
Page 550
User’s manual a2 processor alphabetical register listing page 550 of 897 version 1.3 october 23, 2012 14.5.9 csrr0 - critical save/restore register 0 register short name: csrr0 read access: hypv decimal spr number: 58 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: y...
Page 551
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 551 of 897 14.5.10 csrr1 - critical save/restore register 1 register short name: csrr1 read access: hypv decimal spr number: 59 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: ...
Page 552
User’s manual a2 processor alphabetical register listing page 552 of 897 version 1.3 october 23, 2012 51 me 0b0 machine check enable 0 machine check interrupts are disabled. 1 machine check interrupts are enabled. 52 fe0 0b0 floating-point exception mode 0 sets floating-point exception mode. 53 /// ...
Page 553
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 553 of 897 14.5.11 ctr - count register register short name: ctr read access: any decimal spr number: 9 write access: any initial value: 0x0000000000000000 duplicated for multithread: y slow spr: n notes: gues...
Page 554
User’s manual a2 processor alphabetical register listing page 554 of 897 version 1.3 october 23, 2012 14.5.12 dac1 - data address compare 1 register short name: dac1 read access: hypv decimal spr number: 316 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: n slow spr:...
Page 555
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 555 of 897 14.5.13 dac2 - data address compare 2 register short name: dac2 read access: hypv decimal spr number: 317 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: n slow spr:...
Page 556
User’s manual a2 processor alphabetical register listing page 556 of 897 version 1.3 october 23, 2012 14.5.14 dac3 - data address compare 3 register short name: dac3 read access: hypv decimal spr number: 849 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: n slow spr:...
Page 557
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 557 of 897 14.5.15 dac4 - data address compare 4 register short name: dac4 read access: hypv decimal spr number: 850 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: n slow spr:...
Page 558
User’s manual a2 processor alphabetical register listing page 558 of 897 version 1.3 october 23, 2012 14.5.16 dbcr0 - debug control register 0 register short name: dbcr0 read access: hypv decimal spr number: 308 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: y slow ...
Page 559
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 559 of 897 44:45 dac1 0b00 data address compare 1 debug event enable 00 disabled: dac1 debug events cannot occur. 01 store only: dac1 debug events can occur only if a store-type data storage access. 10 load on...
Page 560
User’s manual a2 processor alphabetical register listing page 560 of 897 version 1.3 october 23, 2012 14.5.17 dbcr1 - debug control register 1 register short name: dbcr1 read access: hypv decimal spr number: 309 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: y slow ...
Page 561
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 561 of 897 52:53 iac4us 0b00 instruction address compare 4 user/supervisor mode 00 enabled: iac4 debug events can occur. 01 reserved. 10 enabled pr0: iac4 debug events can occur only if msr[pr] = 0. 11 enabled...
Page 562
User’s manual a2 processor alphabetical register listing page 562 of 897 version 1.3 october 23, 2012 14.5.18 dbcr2 - debug control register 2 register short name: dbcr2 read access: hypv decimal spr number: 310 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: y slow ...
Page 563
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 563 of 897 46:47 dvc2m 0b00 data value compare 2 mode 00 dvc disabled: dac2 debug events can occur. 01 dvc all: dac2 debug events can occur only when all bytes specified by dvc2be in the data value of the data...
Page 564
User’s manual a2 processor alphabetical register listing page 564 of 897 version 1.3 october 23, 2012 14.5.19 dbcr3 - debug control register 3 register short name: dbcr3 read access: hypv decimal spr number: 848 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: y slow ...
Page 565
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 565 of 897 14.5.20 dbsr - debug status register register short name: dbsr read access: hypv decimal spr number: 304 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: y slow spr: ...
Page 566
User’s manual a2 processor alphabetical register listing page 566 of 897 version 1.3 october 23, 2012 47 dac2w 0b0 data address compare 2 write debug event set to 1 if a write-type dac2 debug event occurred and dbcr0[dac2] = 0b01 or dbcr0[dac2] = 0b11. 48 ret 0b0 return debug event set to 1 if a ret...
Page 567
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 567 of 897 14.5.21 dbsrwr - debug status register write register register short name: dbsrwr read access: none decimal spr number: 306 write access: hypv initial value: 0x0000000000000000 duplicated for multit...
Page 568
User’s manual a2 processor alphabetical register listing page 568 of 897 version 1.3 october 23, 2012 60 dac3w 0b0 data address compare 3 write debug event sets corresponding dbsr bit. 61 dac4r 0b0 data address compare 4 read debug event sets corresponding dbsr bit. 62 dac4w 0b0 data address compare...
Page 569
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 569 of 897 14.5.22 dear - data exception address register register short name: dear read access: priv decimal spr number: 61 write access: priv initial value: 0x0000000000000000 duplicated for multithread: y s...
Page 570
User’s manual a2 processor alphabetical register listing page 570 of 897 version 1.3 october 23, 2012 14.5.23 dec - decrementer register short name: dec read access: hypv decimal spr number: 22 write access: hypv initial value: 0x000000007fffffff duplicated for multithread: y slow spr: n notes: gues...
Page 571
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 571 of 897 14.5.24 decar - decrementer auto-reload register short name: decar read access: hypv decimal spr number: 54 write access: hypv initial value: 0x000000007fffffff duplicated for multithread: y slow sp...
Page 572
User’s manual a2 processor alphabetical register listing page 572 of 897 version 1.3 october 23, 2012 14.5.25 dvc1 - data value compare 1 register short name: dvc1 read access: hypv decimal spr number: 318 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: n slow spr: y...
Page 573
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 573 of 897 14.5.26 dvc2 - data value compare 2 register short name: dvc2 read access: hypv decimal spr number: 319 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: n slow spr: y...
Page 574
User’s manual a2 processor alphabetical register listing page 574 of 897 version 1.3 october 23, 2012 14.5.27 epcr - embedded processor control register register short name: epcr read access: hypv decimal spr number: 307 write access: hypv initial value: 0x0000000000000000 duplicated for multithread...
Page 575
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 575 of 897 38 icm 0b0 interrupt computation mode controls the computational mode of the processor when an interrupt occurs that is directed to the hypervisor state. At interrupt time, ehcsr[icm] is copied into...
Page 576
User’s manual a2 processor alphabetical register listing page 576 of 897 version 1.3 october 23, 2012 14.5.28 eplc - external process id load context register short name: eplc read access: priv decimal spr number: 947 write access: priv initial value: 0x0000000000000000 duplicated for multithread: y...
Page 577
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 577 of 897 14.5.29 epsc - external process id store context register short name: epsc read access: priv decimal spr number: 948 write access: priv initial value: 0x0000000000000000 duplicated for multithread: ...
Page 578
User’s manual a2 processor alphabetical register listing page 578 of 897 version 1.3 october 23, 2012 14.5.30 eptcfg - embedded page table configuration register register short name: eptcfg read access: hypv decimal spr number: 350 write access: none initial value: 0x0000000000091942 duplicated for ...
Page 579
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 579 of 897 14.5.31 esr - exception syndrome register register short name: esr read access: priv decimal spr number: 62 write access: priv initial value: 0x0000000000000000 duplicated for multithread: y slow sp...
Page 580
User’s manual a2 processor alphabetical register listing page 580 of 897 version 1.3 october 23, 2012 54 tlbi 0b0 tlb ineligible 1 indicates a tlb ineligible exception occurred during a page table translation for the instruction causing the interrupt. 55 pt 0b0 page table 1 indicates a page table fa...
Page 581
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 581 of 897 14.5.32 gdear - guest data exception address register register short name: gdear read access: priv decimal spr number: 381 write access: priv initial value: 0x0000000000000000 duplicated for multith...
Page 582
User’s manual a2 processor alphabetical register listing page 582 of 897 version 1.3 october 23, 2012 14.5.33 gesr - guest exception syndrome register register short name: gesr read access: priv decimal spr number: 383 write access: priv initial value: 0x0000000000000000 duplicated for multithread: ...
Page 583
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 583 of 897 55 pt 0b0 page table 1 indicates a that page table fault or read or write access control exception occurred during a page table translation for the instruction causing the interrupt. 56 spv 0b0 vect...
Page 584
User’s manual a2 processor alphabetical register listing page 584 of 897 version 1.3 october 23, 2012 14.5.34 givpr - guest interrupt vector prefix register register short name: givpr read access: priv decimal spr number: 447 write access: hypv initial value: 0x0000000000000000 duplicated for multit...
Page 585
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 585 of 897 14.5.35 gpir - guest processor id register register short name: gpir read access: priv decimal spr number: 382 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: y slow...
Page 586
User’s manual a2 processor alphabetical register listing page 586 of 897 version 1.3 october 23, 2012 14.5.36 gsprg0 - guest software special purpose register 0 register short name: gsprg0 read access: priv decimal spr number: 368 write access: priv initial value: 0x0000000000000000 duplicated for m...
Page 587
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 587 of 897 14.5.37 gsprg1 - guest software special purpose register 1 register short name: gsprg1 read access: priv decimal spr number: 369 write access: priv initial value: 0x0000000000000000 duplicated for m...
Page 588
User’s manual a2 processor alphabetical register listing page 588 of 897 version 1.3 october 23, 2012 14.5.38 gsprg2 - guest software special purpose register 2 register short name: gsprg2 read access: priv decimal spr number: 370 write access: priv initial value: 0x0000000000000000 duplicated for m...
Page 589
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 589 of 897 14.5.39 gsprg3 - guest software special purpose register 3 register short name: gsprg3 read access: priv decimal spr number: 371 write access: priv initial value: 0x0000000000000000 duplicated for m...
Page 590
User’s manual a2 processor alphabetical register listing page 590 of 897 version 1.3 october 23, 2012 14.5.40 gsrr0 - guest save/restore register 0 register short name: gsrr0 read access: priv decimal spr number: 378 write access: priv initial value: 0x0000000000000000 duplicated for multithread: y ...
Page 591
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 591 of 897 14.5.41 gsrr1 - guest save/restore register 1 register short name: gsrr1 read access: priv decimal spr number: 379 write access: priv initial value: 0x0000000000000000 duplicated for multithread: y ...
Page 592
User’s manual a2 processor alphabetical register listing page 592 of 897 version 1.3 october 23, 2012 50 fp 0b0 floating-point available 0 the processor cannot execute any floating-point instructions, including floating- point loads, stores, and moves. 1 the processor can execute floating-point inst...
Page 593
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 593 of 897 14.5.42 hacop - hypvervisor available coprocessor register short name: hacop read access: priv decimal spr number: 351 write access: hypv initial value: 0x0000000000000000 duplicated for multithread...
Page 594
User’s manual a2 processor alphabetical register listing page 594 of 897 version 1.3 october 23, 2012 14.5.43 iac1 - instruction address compare 1 register short name: iac1 read access: hypv decimal spr number: 312 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: n sl...
Page 595
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 595 of 897 14.5.44 iac2 - instruction address compare 2 register short name: iac2 read access: hypv decimal spr number: 313 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: n sl...
Page 596
User’s manual a2 processor alphabetical register listing page 596 of 897 version 1.3 october 23, 2012 14.5.45 iac3 - instruction address compare 3 register short name: iac3 read access: hypv decimal spr number: 314 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: n sl...
Page 597
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 597 of 897 14.5.46 iac4 - instruction address compare 4 register short name: iac4 read access: hypv decimal spr number: 315 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: n sl...
Page 598
User’s manual a2 processor alphabetical register listing page 598 of 897 version 1.3 october 23, 2012 14.5.47 iar - instruction address register register short name: iar read access: hypv decimal spr number: 882 write access: hypv initial value: 0xfffffffffffffffc duplicated for multithread: y slow ...
Page 599
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 599 of 897 14.5.48 iesr1 - iu event select register 1 register short name: iesr1 read access: priv decimal spr number: 914 write access: priv initial value: 0x0000000000000000 duplicated for multithread: n slo...
Page 600
User’s manual a2 processor alphabetical register listing page 600 of 897 version 1.3 october 23, 2012 14.5.49 iesr2 - iu event select register 2 register short name: iesr2 read access: priv decimal spr number: 915 write access: priv initial value: 0x0000000000000000 duplicated for multithread: n slo...
Page 601
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 601 of 897 14.5.50 immr - instruction match mask register register short name: immr read access: hypv decimal spr number: 881 write access: hypv initial value: 0x00000000ffffffff duplicated for multithread: n ...
Page 602
User’s manual a2 processor alphabetical register listing page 602 of 897 version 1.3 october 23, 2012 14.5.51 impdep0 - implementation dependent region 0 register short name: impdep0 read access: hypv decimal spr number: 976 - 991 write access: hypv initial value: 0x0000000000000000 duplicated for m...
Page 603
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 603 of 897 14.5.52 impdep1 - implementation dependent region 1 register short name: impdep1 read access: priv decimal spr number: 912 - 927 write access: priv initial value: 0x0000000000000000 duplicated for m...
Page 604
User’s manual a2 processor alphabetical register listing page 604 of 897 version 1.3 october 23, 2012 14.5.53 imr - instruction match register register short name: imr read access: hypv decimal spr number: 880 write access: hypv initial value: 0x00000000ffffffff duplicated for multithread: n slow sp...
Page 605
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 605 of 897 14.5.54 iucr0 - instruction unit configuration register 0 register short name: iucr0 read access: hypv decimal spr number: 1011 write access: hypv initial value: 0x00000000000010fa duplicated for mu...
Page 606
User’s manual a2 processor alphabetical register listing page 606 of 897 version 1.3 october 23, 2012 14.5.55 iucr1 - instruction unit configuration register 1 register short name: iucr1 read access: hypv decimal spr number: 883 write access: hypv initial value: 0x0000000000001000 duplicated for mul...
Page 607
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 607 of 897 14.5.56 iucr2 - instruction unit configuration register 2 register short name: iucr2 read access: hypv decimal spr number: 884 write access: hypv initial value: 0x0000000000000000 duplicated for mul...
Page 608
User’s manual a2 processor alphabetical register listing page 608 of 897 version 1.3 october 23, 2012 14.5.57 iudbg0 - instruction unit debug register 0 register short name: iudbg0 read access: hypv decimal spr number: 888 write access: hypv initial value: 0x0000000000000000 duplicated for multithre...
Page 609
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 609 of 897 14.5.58 iudbg1 - instruction unit debug register 1 register short name: iudbg1 read access: hypv decimal spr number: 889 write access: none initial value: 0x0000000000000000 duplicated for multithre...
Page 610
User’s manual a2 processor alphabetical register listing page 610 of 897 version 1.3 october 23, 2012 14.5.59 iudbg2 - instruction unit debug register 2 register short name: iudbg2 read access: hypv decimal spr number: 890 write access: none initial value: 0x0000000000000000 duplicated for multithre...
Page 611
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 611 of 897 14.5.60 iulfsr - instruction unit lfsr register short name: iulfsr read access: hypv decimal spr number: 891 write access: hypv initial value: 0x000000000000001a duplicated for multithread: n slow s...
Page 612
User’s manual a2 processor alphabetical register listing page 612 of 897 version 1.3 october 23, 2012 14.5.61 iullcr - instruction unit live lock control register register short name: iullcr read access: hypv decimal spr number: 892 write access: hypv initial value: 0x0000000000020040 duplicated for...
Page 613
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 613 of 897 14.5.62 ivpr - interrupt vector prefix register register short name: ivpr read access: hypv decimal spr number: 63 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: n ...
Page 614
User’s manual a2 processor alphabetical register listing page 614 of 897 version 1.3 october 23, 2012 14.5.63 lper - logical page exception register register short name: lper read access: hypv decimal spr number: 56 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: y s...
Page 615
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 615 of 897 14.5.64 lperu - logical page exception register (upper) register short name: lperu read access: hypv decimal spr number: 57 write access: hypv initial value: 0x0000000000000000 duplicated for multit...
Page 616
User’s manual a2 processor alphabetical register listing page 616 of 897 version 1.3 october 23, 2012 14.5.65 lpidr - logical partition id register register short name: lpidr read access: hypv decimal spr number: 338 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: n ...
Page 617
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 617 of 897 14.5.66 lr - link register register short name: lr read access: any decimal spr number: 8 write access: any initial value: 0x0000000000000000 duplicated for multithread: y slow spr: n notes: guest s...
Page 618
User’s manual a2 processor alphabetical register listing page 618 of 897 version 1.3 october 23, 2012 14.5.67 lratcfg - lrat configuration register register short name: lratcfg read access: hypv decimal spr number: 342 write access: none initial value: 0x0000000000542008 duplicated for multithread: ...
Page 619
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 619 of 897 14.5.68 lratps - lrat page size register register short name: lratps read access: hypv decimal spr number: 343 write access: none initial value: 0x0000000051544400 duplicated for multithread: n slow...
Page 620
User’s manual a2 processor alphabetical register listing page 620 of 897 version 1.3 october 23, 2012 14.5.69 mas0 - mmu assist register 0 register short name: mas0 read access: priv decimal spr number: 624 write access: priv initial value: 0x0000000000000000 duplicated for multithread: y slow spr: ...
Page 621
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 621 of 897 14.5.70 mas0_mas1 - mmu assist registers 0 and 1 register short name: mas0_mas1 read access: priv decimal spr number: 373 write access: priv initial value: 0x0000000000000000 duplicated for multithr...
Page 622
User’s manual a2 processor alphabetical register listing page 622 of 897 version 1.3 october 23, 2012 14.5.71 mas1 - mmu assist register 1 register short name: mas1 read access: priv decimal spr number: 625 write access: priv initial value: 0x0000000000000000 duplicated for multithread: y slow spr: ...
Page 623
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 623 of 897 52:55 tsize 0b0000 translation size the selected tlb entry (when mas0.Atsel = 0) or lrat entry (when mas0.Atsel = 1) page size value. This implementation supports five page sizes for direct tlb entr...
Page 624
User’s manual a2 processor alphabetical register listing page 624 of 897 version 1.3 october 23, 2012 14.5.72 mas2 - mmu assist register 2 register short name: mas2 read access: priv decimal spr number: 626 write access: priv initial value: 0x0000000000000000 duplicated for multithread: y slow spr: ...
Page 625
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 625 of 897 14.5.73 mas2u - mmu assist register 2 (upper) register short name: mas2u read access: priv decimal spr number: 631 write access: priv initial value: 0x0000000000000000 duplicated for multithread: y ...
Page 626
User’s manual a2 processor alphabetical register listing page 626 of 897 version 1.3 october 23, 2012 14.5.74 mas3 - mmu assist register 3 register short name: mas3 read access: priv decimal spr number: 627 write access: priv initial value: 0x0000000000000000 duplicated for multithread: y slow spr: ...
Page 627
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 627 of 897 60 uw/spsize2 0b0 user mode execute enable (ind = 0) / spsize2 (ind = 1) for direct tlb (ind = 0) entries, specifies user mode (msr.Pr = 1) write access permis- sion. See section 6.4 access control ...
Page 628
User’s manual a2 processor alphabetical register listing page 628 of 897 version 1.3 october 23, 2012 14.5.75 mas4 - mmu assist register 4 register short name: mas4 read access: priv decimal spr number: 628 write access: priv initial value: 0x0000000000000100 duplicated for multithread: y slow spr: ...
Page 629
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 629 of 897 14.5.76 mas5 - mmu assist register 5 register short name: mas5 read access: hypv decimal spr number: 339 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: y slow spr: ...
Page 630
User’s manual a2 processor alphabetical register listing page 630 of 897 version 1.3 october 23, 2012 14.5.77 mas5_mas6 - mmu assist registers 5 and 6 register short name: mas5_mas6 read access: hypv decimal spr number: 348 write access: hypv initial value: 0x0000000000000000 duplicated for multithr...
Page 631
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 631 of 897 14.5.78 mas6 - mmu assist register 6 register short name: mas6 read access: priv decimal spr number: 630 write access: priv initial value: 0x0000000000000000 duplicated for multithread: y slow spr: ...
Page 632
User’s manual a2 processor alphabetical register listing page 632 of 897 version 1.3 october 23, 2012 14.5.79 mas7 - mmu assist register 7 register short name: mas7 read access: priv decimal spr number: 944 write access: priv initial value: 0x0000000000000000 duplicated for multithread: y slow spr: ...
Page 633
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 633 of 897 14.5.80 mas7_mas3 - mmu assist registers 7 and 3 register short name: mas7_mas3 read access: priv decimal spr number: 372 write access: priv initial value: 0x0000000000000000 duplicated for multithr...
Page 634
User’s manual a2 processor alphabetical register listing page 634 of 897 version 1.3 october 23, 2012 14.5.81 mas8 - mmu assist register 8 register short name: mas8 read access: hypv decimal spr number: 341 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: y slow spr: ...
Page 635
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 635 of 897 14.5.82 mas8_mas1 - mmu assist registers 8 and 1 register short name: mas8_mas1 read access: hypv decimal spr number: 349 write access: hypv initial value: 0x0000000000000000 duplicated for multithr...
Page 636
User’s manual a2 processor alphabetical register listing page 636 of 897 version 1.3 october 23, 2012 14.5.83 mcsr - machine check syndrome register register short name: mcsr read access: hypv decimal spr number: 572 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: y ...
Page 637
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 637 of 897 61 depe 0b0 d-erat parity error 1 indicates a parity error detected for a d-erat eratre, eratsx, or compare. 62 tlbpe 0b0 tlb parity error 1 indicates a parity error detected for a tlb tlbre, tlbsx,...
Page 638
User’s manual a2 processor alphabetical register listing page 638 of 897 version 1.3 october 23, 2012 14.5.84 mcsrr0 - machine check save/restore register 0 register short name: mcsrr0 read access: hypv decimal spr number: 570 write access: hypv initial value: 0x0000000000000000 duplicated for multi...
Page 639
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 639 of 897 14.5.85 mcsrr1 - machine check save/restore register 1 register short name: mcsrr1 read access: hypv decimal spr number: 571 write access: hypv initial value: 0x0000000000000000 duplicated for multi...
Page 640
User’s manual a2 processor alphabetical register listing page 640 of 897 version 1.3 october 23, 2012 51 me 0b0 machine check enable 0 machine check interrupts are disabled. 1 machine check interrupts are enabled. 52 fe0 0b0 floating-point exception mode 0 sets floating-point exception mode. 53 /// ...
Page 641
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 641 of 897 14.5.86 mesr1 - mmu event select register 1 register short name: mesr1 read access: priv decimal spr number: 916 write access: priv initial value: 0x0000000000000000 duplicated for multithread: n sl...
Page 642
User’s manual a2 processor alphabetical register listing page 642 of 897 version 1.3 october 23, 2012 14.5.87 mesr2 - mmu event select register 2 register short name: mesr2 read access: priv decimal spr number: 917 write access: priv initial value: 0x0000000000000000 duplicated for multithread: n sl...
Page 643
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 643 of 897 14.5.88 mmucfg - mmu configuration register register short name: mmucfg read access: hypv decimal spr number: 1015 write access: none initial value: 0x0000000008558341 duplicated for multithread: n ...
Page 644
User’s manual a2 processor alphabetical register listing page 644 of 897 version 1.3 october 23, 2012 14.5.89 mmucr0 - memory management unit control register 0 register short name: mmucr0 read access: hypv decimal spr number: 1020 write access: hypv initial value: 0x0000000000000000 duplicated for ...
Page 645
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 645 of 897 14.5.90 mmucr1 - memory management unit control register 1 register short name: mmucr1 read access: hypv decimal spr number: 1021 write access: hypv initial value: 0x000000000c000000 duplicated for ...
Page 646
User’s manual a2 processor alphabetical register listing page 646 of 897 version 1.3 october 23, 2012 45 ittid 0b0 i-erat thdid translation id enable 0 i-erat thdid field operates as a thread id. 1 i-erat thdid field operates as tid[2:5] bits (of tid[0:13] total value). 46 dctid 0b0 d-erat class tra...
Page 647
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 647 of 897 14.5.91 mmucr2 - memory management unit control register 2 register short name: mmucr2 read access: hypv decimal spr number: 1022 write access: hypv initial value: 0x00000000000a7531 duplicated for ...
Page 648
User’s manual a2 processor alphabetical register listing page 648 of 897 version 1.3 october 23, 2012 56:59 ps1 0b0011 tlb page size 1 select 0000 disabled (do not apply the hash for this page size). 0001 page size = 4 kb. 0011 page size = 64 kb. 0101 page size = 1 mb. 0111 page size = 16 mb. 1010 p...
Page 649
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 649 of 897 14.5.92 mmucr3 - memory management unit control register 3 register short name: mmucr3 read access: priv decimal spr number: 1023 write access: priv initial value: 0x000000000000000f duplicated for ...
Page 650
User’s manual a2 processor alphabetical register listing page 650 of 897 version 1.3 october 23, 2012 14.5.93 mmucsr0 - mmu control and status register 0 register short name: mmucsr0 read access: hypv decimal spr number: 1012 write access: hypv initial value: 0x0000000000000000 duplicated for multit...
Page 651
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 651 of 897 14.5.94 msr - machine state register register short name: msr read access: priv decimal spr number: n/a write access: priv initial value: 0x0000000000000000 duplicated for multithread: y slow spr: n...
Page 652
User’s manual a2 processor alphabetical register listing page 652 of 897 version 1.3 october 23, 2012 50 fp 0b0 floating-point available 0 the processor cannot execute any floating-point instructions, including floating- point loads, stores, and moves. 1 the processor can execute floating-point inst...
Page 653
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 653 of 897 14.5.95 msrp - machine state register protect register short name: msrp read access: hypv decimal spr number: 311 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: y s...
Page 654
User’s manual a2 processor alphabetical register listing page 654 of 897 version 1.3 october 23, 2012 14.5.96 pid - process id register short name: pid read access: priv decimal spr number: 48 write access: priv initial value: 0x0000000000000000 duplicated for multithread: y slow spr: y notes: guest...
Page 655
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 655 of 897 14.5.97 pir - processor id register register short name: pir read access: priv decimal spr number: 286 write access: none initial value: 0x0000000000000000 duplicated for multithread: n slow spr: n ...
Page 656
User’s manual a2 processor alphabetical register listing page 656 of 897 version 1.3 october 23, 2012 14.5.98 ppr32 - program priority register register short name: ppr32 read access: any decimal spr number: 898 write access: any initial value: 0x00000000000c0000 duplicated for multithread: y slow s...
Page 657
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 657 of 897 14.5.99 pvr - processor version register register short name: pvr read access: priv decimal spr number: 287 write access: none initial value: 0x0000000000490001 duplicated for multithread: n slow sp...
Page 658
User’s manual a2 processor alphabetical register listing page 658 of 897 version 1.3 october 23, 2012 14.5.100 sprg0 - software special purpose register 0 register short name: sprg0 read access: priv decimal spr number: 272 write access: priv initial value: 0x0000000000000000 duplicated for multithr...
Page 659
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 659 of 897 14.5.101 sprg1 - software special purpose register 1 register short name: sprg1 read access: priv decimal spr number: 273 write access: priv initial value: 0x0000000000000000 duplicated for multithr...
Page 660
User’s manual a2 processor alphabetical register listing page 660 of 897 version 1.3 october 23, 2012 14.5.102 sprg2 - software special purpose register 2 register short name: sprg2 read access: priv decimal spr number: 274 write access: priv initial value: 0x0000000000000000 duplicated for multithr...
Page 661
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 661 of 897 14.5.103 sprg3 - software special purpose register 3 register short name: sprg3 read access: priv/any decimal spr number: 275/259 write access: priv/none initial value: 0x0000000000000000 duplicated...
Page 662
User’s manual a2 processor alphabetical register listing page 662 of 897 version 1.3 october 23, 2012 14.5.104 sprg4 - software special purpose register 4 register short name: sprg4 read access: priv/any decimal spr number: 276/260 write access: priv/none initial value: 0x0000000000000000 duplicated...
Page 663
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 663 of 897 14.5.105 sprg5 - software special purpose register 5 register short name: sprg5 read access: priv/any decimal spr number: 277/261 write access: priv/none initial value: 0x0000000000000000 duplicated...
Page 664
User’s manual a2 processor alphabetical register listing page 664 of 897 version 1.3 october 23, 2012 14.5.106 sprg6 - software special purpose register 6 register short name: sprg6 read access: priv/any decimal spr number: 278/262 write access: priv/none initial value: 0x0000000000000000 duplicated...
Page 665
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 665 of 897 14.5.107 sprg7 - software special purpose register 7 register short name: sprg7 read access: priv/any decimal spr number: 279/263 write access: priv/none initial value: 0x0000000000000000 duplicated...
Page 666
User’s manual a2 processor alphabetical register listing page 666 of 897 version 1.3 october 23, 2012 14.5.108 sprg8 - software special purpose register 8 register short name: sprg8 read access: hypv decimal spr number: 604 write access: hypv initial value: 0x0000000000000000 duplicated for multithr...
Page 667
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 667 of 897 14.5.109 srr0 - save/restore register 0 register short name: srr0 read access: priv decimal spr number: 26 write access: priv initial value: 0x0000000000000000 duplicated for multithread: y slow spr...
Page 668
User’s manual a2 processor alphabetical register listing page 668 of 897 version 1.3 october 23, 2012 14.5.110 srr1 - save/restore register 1 register short name: srr1 read access: priv decimal spr number: 27 write access: priv initial value: 0x0000000000000000 duplicated for multithread: y slow spr...
Page 669
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 669 of 897 50 fp 0b0 floating-point available 0 the processor cannot execute any floating-point instructions, including floating- point loads, stores, and moves. 1 the processor can execute floating-point inst...
Page 670
User’s manual a2 processor alphabetical register listing page 670 of 897 version 1.3 october 23, 2012 14.5.111 tb - timebase register short name: tb read access: any decimal spr number: 268 write access: none initial value: 0x0000000000000000 duplicated for multithread: n slow spr: n notes: guest su...
Page 671
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 671 of 897 14.5.112 tbl - timebase lower register short name: tbl read access: none decimal spr number: 284 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: n slow spr: n notes:...
Page 672
User’s manual a2 processor alphabetical register listing page 672 of 897 version 1.3 october 23, 2012 14.5.113 tbu - timebase upper register short name: tbu read access: none/any decimal spr number: 285/269 write access: hypv/none initial value: 0x0000000000000000 duplicated for multithread: n slow ...
Page 673
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 673 of 897 14.5.114 tcr - timer control register register short name: tcr read access: hypv decimal spr number: 340 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: y slow spr: ...
Page 674
User’s manual a2 processor alphabetical register listing page 674 of 897 version 1.3 october 23, 2012 43:50 /// 0x0 reserved 51 ud 0b0 user decrementer available 0 mtspr or mfspr to the udec register causes an illegal instruction exception. 1 mtspr or mfspr to the udec register succeeds. Note: chang...
Page 675
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 675 of 897 14.5.115 tenc - thread enable clear register register short name: tenc read access: hypv decimal spr number: 439 write access: hypv initial value: 0x0000000000000001 duplicated for multithread: n sl...
Page 676
User’s manual a2 processor alphabetical register listing page 676 of 897 version 1.3 october 23, 2012 14.5.116 tens - thread enable set register register short name: tens read access: hypv decimal spr number: 438 write access: hypv initial value: 0x0000000000000001 duplicated for multithread: n slow...
Page 677
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 677 of 897 14.5.117 tensr - thread enable status register register short name: tensr read access: hypv decimal spr number: 437 write access: none initial value: 0x0000000000000000 duplicated for multithread: n...
Page 678
User’s manual a2 processor alphabetical register listing page 678 of 897 version 1.3 october 23, 2012 14.5.118 tir - thread identification register register short name: tir read access: hypv decimal spr number: 446 write access: none initial value: 0x0000000000000000 duplicated for multithread: n sl...
Page 679
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 679 of 897 14.5.119 tlb0cfg - tlb 0 configuration register register short name: tlb0cfg read access: hypv decimal spr number: 688 write access: none initial value: 0x000000000407a200 duplicated for multithread...
Page 680
User’s manual a2 processor alphabetical register listing page 680 of 897 version 1.3 october 23, 2012 14.5.120 tlb0ps - tlb 0 page size register register short name: tlb0ps read access: hypv decimal spr number: 344 write access: none initial value: 0x0000000000104444 duplicated for multithread: n sl...
Page 681
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 681 of 897 14.5.121 trace - hardware trace macro control register register short name: trace read access: none decimal spr number: 1006 write access: any initial value: 0x0000000000000000 duplicated for multit...
Page 682
User’s manual a2 processor alphabetical register listing page 682 of 897 version 1.3 october 23, 2012 14.5.122 tsr - timer status register register short name: tsr read access: hypv decimal spr number: 336 write access: hypv initial value: 0x0000000000000000 duplicated for multithread: y slow spr: n...
Page 683
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 683 of 897 14.5.123 udec - user decrementer register short name: udec read access: any decimal spr number: 550 write access: any initial value: 0x000000007fffffff duplicated for multithread: y slow spr: n note...
Page 684
User’s manual a2 processor alphabetical register listing page 684 of 897 version 1.3 october 23, 2012 14.5.124 vrsave - vector register save register short name: vrsave read access: any decimal spr number: 256 write access: any initial value: 0x0000000000000000 duplicated for multithread: y slow spr...
Page 685
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 685 of 897 14.5.125 xer - fixed point exception register register short name: xer read access: any decimal spr number: 1 write access: any initial value: 0x0000000000000000 duplicated for multithread: y slow s...
Page 686
User’s manual a2 processor alphabetical register listing page 686 of 897 version 1.3 october 23, 2012 14.5.126 xesr1 - xu event select register 1 register short name: xesr1 read access: priv decimal spr number: 918 write access: priv initial value: 0x0000000000000000 duplicated for multithread: n sl...
Page 687
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 687 of 897 14.5.127 xesr2 - xu event select register 2 register short name: xesr2 read access: priv decimal spr number: 919 write access: priv initial value: 0x0000000000000000 duplicated for multithread: n sl...
Page 688
User’s manual a2 processor alphabetical register listing page 688 of 897 version 1.3 october 23, 2012 14.5.128 xesr3 - xu event select register 3 register short name: xesr3 read access: priv decimal spr number: 920 write access: priv initial value: 0x0000000000000000 duplicated for multithread: n sl...
Page 689
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 689 of 897 14.5.129 xesr4 - xu event select register 4 register short name: xesr4 read access: priv decimal spr number: 921 write access: priv initial value: 0x0000000000000000 duplicated for multithread: n sl...
Page 690
User’s manual a2 processor alphabetical register listing page 690 of 897 version 1.3 october 23, 2012 14.5.130 xucr0 - execution unit configuration register 0 register short name: xucr0 read access: hypv decimal spr number: 1014 write access: hypv initial value: 0x00000000000708c0 duplicated for mul...
Page 691
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 691 of 897 52 rel ro 0b1 l2 reload control ro 0 critical quadword first and data every other cycle. 1 critical quadword first and data in back-to-back cycles. Note: this field is read only and can only be set ...
Page 692
User’s manual a2 processor alphabetical register listing page 692 of 897 version 1.3 october 23, 2012 63 clfc np 0b0 cache lock bits flash clear np writing a 1 during a flash clear operation causes an undefined operation. Writing a 0 during a flash clear operation is ignored. Clearing occurs regardl...
Page 693
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 693 of 897 14.5.131 xucr1 - execution unit configuration register 1 register short name: xucr1 read access: hypv decimal spr number: 851 write access: hypv initial value: 0x0000000000000000 duplicated for mult...
Page 694
User’s manual a2 processor alphabetical register listing page 694 of 897 version 1.3 october 23, 2012 14.5.132 xucr2 - execution unit configuration register 2 register short name: xucr2 read access: hypv decimal spr number: 1016 write access: hypv initial value: 0x00000000ffffffff duplicated for mul...
Page 695
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 695 of 897 14.5.133 xucr3 - execution unit configuration register 3 register short name: xucr3 read access: hypv decimal spr number: 852 write access: hypv initial value: 0x0000000002401441 duplicated for mult...
Page 696
User’s manual a2 processor alphabetical register listing page 696 of 897 version 1.3 october 23, 2012 14.5.134 xucr4 - execution unit configuration register 4 register short name: xucr4 read access: hypv decimal spr number: 853 write access: hypv initial value: 0x0000000000000500 duplicated for mult...
Page 697
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 697 of 897 14.5.135 xudbg0 - execution unit debug register 0 register short name: xudbg0 read access: hypv decimal spr number: 885 write access: hypv initial value: 0x0000000000000000 duplicated for multithrea...
Page 698
User’s manual a2 processor alphabetical register listing page 698 of 897 version 1.3 october 23, 2012 14.5.136 xudbg1 - execution unit debug register 1 register short name: xudbg1 read access: hypv decimal spr number: 886 write access: none initial value: 0x0000000000000000 duplicated for multithrea...
Page 699
User’s manual a2 processor version 1.3 october 23, 2012 alphabetical register listing page 699 of 897 14.5.137 xudbg2 - execution unit debug register 2 register short name: xudbg2 read access: hypv decimal spr number: 887 write access: none initial value: 0x0000000000000000 duplicated for multithrea...
Page 700
User’s manual a2 processor alphabetical register listing page 700 of 897 version 1.3 october 23, 2012.
Page 701
User’s manual a2 processor version 1.3 october 23, 2012 scom accessible registers page 701 of 864 15. Scom accessible registers the serial communications (scom) interface provides access to registers used for pervasive operations. A scom satellite within the pc unit provides the external connections...
Page 702
User’s manual a2 processor scom accessible registers page 702 of 864 version 1.3 october 23, 2012 figure 15-1. Chip level infrastructure example to access scom registers in the a2 core figure 15-2. Principle timing of information carried on cch and dch chiplet pscom le kernel kernel kernel sat. 0 sa...
Page 703
User’s manual a2 processor version 1.3 october 23, 2012 scom accessible registers page 703 of 864 15.2 scom register summary 15.2.1 read and write access methods besides basic read and write access, some scom register addresses provide a reset with and mask or set with or mask capability. This secti...
Page 704
User’s manual a2 processor scom accessible registers page 704 of 864 version 1.3 october 23, 2012 x’09’ 9 error injection register (errinj) rw x’0a’ 10 fault isolation register 1 (fir1) rw x’0b’ 11 fault isolation register 1 (reset with and mask) wo x’0c’ 12 fault isolation register 1 (set with or m...
Page 705
User’s manual a2 processor version 1.3 october 23, 2012 scom accessible registers page 705 of 864 15.3 alphabetical register listing 15.3.1 axu debug select register (abdsr) x’36’ 54 special attention register (spattn) rw x’37’ 55 special attention register (reset with and mask) wo x’38’ 56 special ...
Page 706
User’s manual a2 processor scom accessible registers page 706 of 864 version 1.3 october 23, 2012 15.3.2 error injection register (errinj) note: although bits of the error injection register can be set at any time through scom writes, the error inject signals are gated by an error inject enable bit ...
Page 707
User’s manual a2 processor version 1.3 october 23, 2012 scom accessible registers page 707 of 864 15.3.3 fault isolation register 0 and associated registers the firs are implemented as a group of interrelated registers. This section contains register definitions for fir0: • fault isolation register ...
Page 708
User’s manual a2 processor scom accessible registers page 708 of 864 version 1.3 october 23, 2012 bits in the mask, action0, and action1 registers have a 1-to-1 correspondence to the fir, and together deter- mine how an unmasked error is reported. The following table describes the function of the ma...
Page 709
User’s manual a2 processor version 1.3 october 23, 2012 scom accessible registers page 709 of 864 44 fu_pc_err_regfile_parity, t0 0 an fu register file parity error was detected by thread 0. Hardware error recovery will correct the data and update the array. 45 fu_pc_err_regfile_parity, t1 0 an fu r...
Page 710
User’s manual a2 processor scom accessible registers page 710 of 864 version 1.3 october 23, 2012 bits function initial value description 0:31 reserved 0 32 iu_pc_err_icache_parity 1 i-cache recoverable error. 33 iu_pc_err_icachedir_parity 1 i-cache directory recoverable error. 34 xu_pc_err_dcache_p...
Page 711
User’s manual a2 processor version 1.3 october 23, 2012 scom accessible registers page 711 of 864 15.3.4 fault isolation register 1 and associated registers the firs are implemented as a group of interrelated registers. This section contains register definitions for fir1: • fault isolation register ...
Page 712
User’s manual a2 processor scom accessible registers page 712 of 864 version 1.3 october 23, 2012 bits function initial value description 0:31 reserved 0 32 max_recov_err_cntr_value 0 the recoverable error counter has incremented to its maximum value of b‘1111’. Additional unmasked recoverable error...
Page 713
User’s manual a2 processor version 1.3 october 23, 2012 scom accessible registers page 713 of 864 54 xu_pc_err_debug_event, t2 0 a debug compare event on thread 2 occurred and was enabled to set a bit in the fir. The default action is to cause a checkstop. 55 xu_pc_err_debug_event, t3 0 a debug comp...
Page 714
User’s manual a2 processor scom accessible registers page 714 of 864 version 1.3 october 23, 2012 61 reserved 0 reserved 62 xu_pc_err_invld_reld 1 load-store unit checkstop error. 63 fir_regs_parity_err 1 fir related register (action0, action1, or mask) checkstop error. Table 15-9. Fir1 action1 regi...
Page 715
User’s manual a2 processor version 1.3 october 23, 2012 scom accessible registers page 715 of 864 33 xu_pc_err_l2intrf_ecc 1 l2 interface recoverable error. 34 xu_pc_err_l2intrf_ue 1 l2 interface checkstop error. 35 xu_pc_err_l2credit_overrun 1 store or load queue credit overrun checkstop error. 36:...
Page 716
User’s manual a2 processor scom accessible registers page 716 of 864 version 1.3 october 23, 2012 15.3.5 fault isolation register 2 and associated registers the firs are implemented as a group of interrelated registers. This section contains register definitions for fir2: • fault isolation register ...
Page 717
User’s manual a2 processor version 1.3 october 23, 2012 scom accessible registers page 717 of 864 41 xu_pc_err_derat_multihit 0 a multiple entry hit error was detected by the d-erat compare logic by one or more threads. 42 xu_pc_err_tlb_multihit 0 a multiple entry hit error was detected by the tlb c...
Page 718
User’s manual a2 processor scom accessible registers page 718 of 864 version 1.3 october 23, 2012 42 xu_pc_err_tlb_multihit 0 tlb multihit recoverable error. 43 xu_pc_err_ext_mchk 0 external machine check interrupt. 44 xu_pc_err_local_snoop_reject 0 local back-invalidate snoop rejected. Should be se...
Page 719
User’s manual a2 processor version 1.3 october 23, 2012 scom accessible registers page 719 of 864 46 xu_pc_err_mchk_disabled 0 a machine check interrupt occurred while machine checks were not enabled. This error can be reported as a checkstop. Note: activation of the external machine check interrupt...
Page 720
User’s manual a2 processor scom accessible registers page 720 of 864 version 1.3 october 23, 2012 15.3.6 iu debug select register (idsr) table 15-14. Fir2 mask register (fir2m) register short name: fir2m access: rw, wo_and, wo_or register address: x‘1a’ rw x‘1b’ wo with and mask x‘1c’ wo with or mas...
Page 721
User’s manual a2 processor version 1.3 october 23, 2012 scom accessible registers page 721 of 864 iu debug mux1 controls (8:1 debug multiplexer) 32:34 debug group multiplexer select 0 selects which debug group is driven to the debug multiplexer output: 000 debug group 0. 001 debug group 1. 010 debug...
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User’s manual a2 processor scom accessible registers page 722 of 864 version 1.3 october 23, 2012 iu debug mux2 controls (16:1 debug multiplexer) 48:51 debug group multiplexer select 0 selects which debug group is driven to the debug multiplexer output: 0000 debug group 0. 0001 debug group 1. 0010 d...
Page 723
User’s manual a2 processor version 1.3 october 23, 2012 scom accessible registers page 723 of 864 15.3.7 mmu/pc debug select register (mpdsr) register short name: mpdsr access: rw register address: x‘3d’ rw scan ring: dcfg initial value: 0x0000000000000000 bits function initial value description 0:3...
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User’s manual a2 processor scom accessible registers page 724 of 864 version 1.3 october 23, 2012 46 trigger group output select [0:5] 0 determines which signal group is put on trigger data out [0:5]. 0 trigger data in [0:5] is routed onto the trigger bus. 1 trigger group rotate output [0:5] is plac...
Page 725
User’s manual a2 processor version 1.3 october 23, 2012 scom accessible registers page 725 of 864 15.3.8 pc configuration register 0 (pccr0) 62 trigger group output select [0:5] 0 determines which signal group is put on trigger data out [0:5]. 0 trigger data in [0:5] is routed onto the trigger bus. ...
Page 726
User’s manual a2 processor scom accessible registers page 726 of 864 version 1.3 october 23, 2012 15.3.9 ram data registers (ramd, ramdh, ramdl) 48:51 recoverable error counter 0 this 4-bit counter increments whenever an unmasked recoverable error occurs. When the count value reaches 15, an error bi...
Page 727
User’s manual a2 processor version 1.3 october 23, 2012 scom accessible registers page 727 of 864 15.3.10 ram instruction and command registers (ramc, rami, ramic) note: although bits of the ram command register can be set at any time through scom writes, the ram mode function and control signals ar...
Page 728
User’s manual a2 processor scom accessible registers page 728 of 864 version 1.3 october 23, 2012 47 execute 0 when set, the ram instruction is forced into the processor pipeline for the selected thread. This bit is nonpersistent; it is pulsed for one cycle and reset. Note: ram operations must be en...
Page 729
User’s manual a2 processor version 1.3 october 23, 2012 scom accessible registers page 729 of 864 15.3.11 special attention register (spattn) the special attention register (spattn) is a 32-bit scom accessible register used to control reporting of special attentions outside of the core. Functionally...
Page 730
User’s manual a2 processor scom accessible registers page 730 of 864 version 1.3 october 23, 2012 15.3.12 thread control and status register (thrctl) bits function initial value description 0:31 reserved 0 32 attention instruction, t0 0 execution of an attention (attn) instruction by a thread sets t...
Page 731
User’s manual a2 processor version 1.3 october 23, 2012 scom accessible registers page 731 of 864 15.3.13 xu debug select register1 (xdsr1) 36 t0_step 0 writing a ‘1’ to this location causes one instruction for this thread to be issued. This bit is reset upon completion of the stepped instruction. N...
Page 732
User’s manual a2 processor scom accessible registers page 732 of 864 version 1.3 october 23, 2012 bits function initial value description 0:31 reserved 0 xu debug mux1 controls (16:1 debug multiplexer) 32:35 debug group multiplexer select 0 selects which debug group is driven to the debug multiplexe...
Page 733
User’s manual a2 processor version 1.3 october 23, 2012 scom accessible registers page 733 of 864 xu debug mux2 controls (32:1 debug multiplexer) 48:52 debug group multiplexer select 0 selects which debug group is driven to the debug multiplexer output: 00000 debug group 0. 00001 debug group 1. 0001...
Page 734
User’s manual a2 processor scom accessible registers page 734 of 864 version 1.3 october 23, 2012 15.3.14 xu debug select register2 (xdsr2) register short name: xdsr2 access: rw register address: x‘3f’ rw scan ring: dcfg initial value: 0x0000000000000000 bits function initial value description 0:31 ...
Page 735
User’s manual a2 processor version 1.3 october 23, 2012 scom accessible registers page 735 of 864 46 trigger group output select [0:5] 0 determines which signal group is put on trigger data out [0:5]. 0 trigger data in [0:5] is routed onto the trigger bus. 1 trigger group rotate output [0:5] is plac...
Page 736
User’s manual a2 processor scom accessible registers page 736 of 864 version 1.3 october 23, 2012 63 trigger group output select [6:11] 0 determines which signal group is put on trigger data out [6:11]. 0 trigger data in [6:11] is routed onto the trigger bus. 1 trigger group rotate output [6:11] is ...
Page 737
User’s manual a2 processor version 1.3 october 23, 2012 processor instruction summary page 737 of 864 appendix a. Processor instruction summary this appendix lists all of the a2 core instructions, summarized alphabetically by mnemonic. Extended mnemonics are not included in the opcode list. Reserved...
Page 738
User’s manual a2 processor processor instruction summary page 738 of 864 version 1.3 october 23, 2012 table a-1. A2 core instructions by mnemonic (sheet 1 of 18) pr im ar y extended fo rm mn emonic c a tegor y im plemen ted microcoded t a rge t 1 bits sou rce 1 bi ts sou rce 2 bi ts sou rce 3 bi ts ...
Page 739
User’s manual a2 processor version 1.3 october 23, 2012 processor instruction summary page 739 of 864 29 d andis. B y 11:15 6:10 1 and immediate shifted and record 0 256 tag attn sp y n/a attention 18 i b b y 1 branch 18 i ba b y 1 branch absolute 16 b bc b y branch conditional 16 b bca b y 1 branch...
Page 740
User’s manual a2 processor processor instruction summary page 740 of 864 version 1.3 october 23, 2012 19 33 xl crnor b y 1 condition register nor 19 449 xl cror b y 1 condition register or 19 417 xl crorc b y 1 condition register or with comple- ment 19 193 xl crxor b y 1 condition register xor 31 7...
Page 741
User’s manual a2 processor version 1.3 october 23, 2012 processor instruction summary page 741 of 864 31 393 xo divdeu. 64 y 6:10 11:15 16:20 divide doubleword extended and record 31 393 xo divdeuo 64 y 6:10 11:15 16:20 divide doubleword extended with overflow 31 393 xo divdeuo. 64 y 6:10 11:15 16:2...
Page 742
User’s manual a2 processor processor instruction summary page 742 of 864 version 1.3 october 23, 2012 19 198 xfx dnh e.Ed n debugger notify halt 19 402 xl doze s n doze dss n data stream stop dst n data stream touch dstst n data stream touch for store 31 310 x eciwx ec n 6:10 11:15 16:20 external co...
Page 743
User’s manual a2 processor version 1.3 october 23, 2012 processor instruction summary page 743 of 864 31 998 x icread e.Cd n 11:15 16:20 instruction cache read 31 950 x icswepx cop y 11:15 16:20 6:10 1 initiate coprocessor store word exter- nal pid indexed 31 950 x icswepx. Cop y 11:15 16:20 6:10 sy...
Page 744
User’s manual a2 processor processor instruction summary page 744 of 864 version 1.3 october 23, 2012 31 311 x lhzux b y y 6:10 11:15 16:20 load halfword and zero with update indexed 31 279 x lhzx b y 6:10 11:15 16:20 6 load halfword and zero indexed 46 d lmw b y y 6:10 11:15 uc load multiple word 5...
Page 745
User’s manual a2 processor version 1.3 october 23, 2012 processor instruction summary page 745 of 864 4 204 xo macchwsu. Lma n 6:10 11:15 16:20 multiply accumulate cross halfword to word saturate unsigned and record 4 204 xo macchwsuo lma n 6:10 11:15 16:20 multiply accumulate cross halfword to word...
Page 746
User’s manual a2 processor processor instruction summary page 746 of 864 version 1.3 october 23, 2012 4 12 xo machhwu. Lma n 6:10 11:15 16:20 multiply accumulate high halfword to word modulo unsigned and record 4 12 xo machhwuo lma n 6:10 11:15 16:20 multiply accumulate high halfword to word modulo ...
Page 747
User’s manual a2 processor version 1.3 october 23, 2012 processor instruction summary page 747 of 864 31 512 x mcrxr b y y move to condition register from xer 31 19 xfx mfcr b y 6:10 5 move from condition register 31 323 xfx mfdcr e y 6:10 sys move from device control register 31 291 x mfdcrux e y 6...
Page 748
User’s manual a2 processor processor instruction summary page 748 of 864 version 1.3 october 23, 2012 4 136 x mulchwu. Lma n 6:10 11:15 16:20 multiply cross halfword to word unsigned and record 31 73 xo mulhd 64 y 6:10 11:15 16:20 multiply high doubleword 31 73 xo mulhd. 64 y 6:10 11:15 16:20 multip...
Page 749
User’s manual a2 processor version 1.3 october 23, 2012 processor instruction summary page 749 of 864 19 434 xl nap s n nap 31 104 xo neg b y 6:10 11:15 1 negate 31 104 xo neg. B y 6:10 11:15 1 negate and record 31 104 xo nego b y 6:10 11:15 1 negate with overflow 31 104 xo nego. B y 6:10 11:15 1 ne...
Page 750
User’s manual a2 processor processor instruction summary page 750 of 864 version 1.3 october 23, 2012 4 110 xo nmachhwso. Lma n 6:10 11:15 16:20 negative multiply accumulate high halfword to word saturate signed with record and overflow 4 430 xo nmaclhw lma n 6:10 11:15 16:20 negative multiply accum...
Page 751
User’s manual a2 processor version 1.3 october 23, 2012 processor instruction summary page 751 of 864 31 626 x reserved b y 1 reserved nop 31 658 x reserved b y 1 reserved nop 31 690 x reserved b y 1 reserved nop 31 722 x reserved b y 1 reserved nop 31 754 x reserved b y 1 reserved nop 19 51 xl rfci...
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User’s manual a2 processor processor instruction summary page 752 of 864 version 1.3 october 23, 2012 21 m rlwinm. B y 11:15 6:10 2 rotate left word immediate then and with mask and record 23 m rlwnm b y 11:15 6:10 16:20 2 rotate left word then and with mask 23 m rlwnm. B y 11:15 6:10 16:20 2 rotate...
Page 753
User’s manual a2 processor version 1.3 october 23, 2012 processor instruction summary page 753 of 864 31 247 x stbux b y 11:15 11:15 16:20 6:10 2 store byte with update indexed 31 215 x stbx b y 11:15 16:20 6:10 1 store byte indexed 62 0 ds std 64 y 11:15 6:10 1 store doubleword 31 660 x stdbrx 64 y...
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User’s manual a2 processor processor instruction summary page 754 of 864 version 1.3 october 23, 2012 31 8 xo subfco. B y 6:10 11:15 16:20 2 subtract from carrying with overflow and record 31 136 xo subfe b y 6:10 11:15 16:20 2 subtract from extended 31 136 xo subfe. B y 6:10 11:15 16:20 2 subtract ...
Page 755
User’s manual a2 processor version 1.3 october 23, 2012 processor instruction summary page 755 of 864 31 978 x tlbwe e.Mf y tlb write entry 31 4 x tw b y 11:15 16:20 2 trap word 3 d twi b y 11:15 2 trap word immediate 31 62 x wait wt y 1* wait 31 902 x wchkall y 6 watch check all 31 934 x wclr y 11:...
Page 756
User’s manual a2 processor fu instruction summary page 756 of 864 version 1.3 october 23, 2012 appendix b. Fu instruction summary this appendix contains floating-point unit instructions summarized alphabetically and by opcode. Fu instructions sorted by opcode lists all a2 processor instructions, sor...
Page 757
User’s manual a2 processor version 1.3 october 23, 2012 fu instruction summary page 757 of 864 63 814 x fctid 6 floating convert to integer doubleword 63 814 x fctid. 6:4 floating convert to integer doubleword and record cr1 63 942 x fctidu 6 floating convert to integer doubleword unsigned 63 942 x ...
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User’s manual a2 processor fu instruction summary page 758 of 864 version 1.3 october 23, 2012 63 136 x fnabs 6 floating negative absolute 63 136 x fnabs. 6:4 floating negative absolute value and record cr1 63 40 x fneg 6 floating negate 63 40 x fneg. 6:4 floating negate and record cr1 63 31 a fnmad...
Page 759
User’s manual a2 processor version 1.3 october 23, 2012 fu instruction summary page 759 of 864 59 22 a fsqrts. Y 68:68 floating square root single and record cr1 63 20 a fsub 6 floating subtract 63 20 a fsub. 6:4 floating subtract and record cr1 59 20 a fsubs 6 floating subtract single 59 20 a fsubs...
Page 760
User’s manual a2 processor fu instruction summary page 760 of 864 version 1.3 october 23, 2012 52 d stfs 1 store floating-point single 53 d stfsu 1 store floating-point single with update 31 695 x stfsux 1 store floating-point single with update indexed 31 663 x stfsx 1 store floating-point single i...
Page 761
User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 761 of 864 appendix c. Debug and trigger groups c.1 unit debug multiplexer component figure c-1. Is included for reference in setting up the debug select registers for the individual units. See section 10.12 trace ...
Page 762
User’s manual a2 processor debug and trigger groups page 762 of 864 version 1.3 october 23, 2012 data is implemented on each debug multiplexer output, and on the input of the mmu’s debug multiplexer. The following table also shows the cycles of delay of each debug multiplexer component’s output, rel...
Page 763
User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 763 of 864 • abdsr(39:42) = 0011; axu debug data(44:87) is driven on debug multiplexer outputs (see note). • abdsr(43:44) = 10; selects trigger group 2. • abdsr(45) = 1; rotate bits 0 to 5 of trigger group to bits ...
Page 764
User’s manual a2 processor debug and trigger groups page 764 of 864 version 1.3 october 23, 2012 40 debug group output select [22:43] 0 determines which signal group is put on trace data out [22:43]. 0 trace data in [22:43] is routed onto the trace bus. 1 debug group rotate output [22:43] is placed ...
Page 765
User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 765 of 864 2 dbg_group2 (0 to 31) dbg_group2 (32 to 35) dbg_group2 (36 to 39) dbg_group2 (40 to 43) dbg_group2 (44 to 47) dbg_group2 (48 to 52) dbg_group2 (53 to 55) dbg_group2 (56 to 61) dbg_group2 (62 to 65) dbg_...
Page 766
User’s manual a2 processor debug and trigger groups page 766 of 864 version 1.3 october 23, 2012 c.5 iu debug select register and debug group tables table c-3. Iu debug select register (idsr) register short name: idsr access: rw register address: x‘3c’ rw scan ring: dcfg initial value: 0x00000000000...
Page 767
User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 767 of 864 46 trigger group output select [0:5] 0 determines which signal group is put on trigger data out [0:5]. 0 trigger data in [0:5] is routed onto the trigger bus. 1 trigger group rotate output [0:5] is place...
Page 768
User’s manual a2 processor debug and trigger groups page 768 of 864 version 1.3 october 23, 2012 62 trigger group output select [0:5] 0 determines which signal group is put on trigger data out [0:5]. 0 trigger data in [0:5] is routed onto the trigger bus. 1 trigger group rotate output [0:5] is place...
Page 769
User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 769 of 864 2 (0:3) (4) ibuf0.Rm_ib_iu4_val; (5) ibuf0.Uc_ib_iu4_val; (6) ibuf0.Redirect_l2; (7) ibuf0.Ib_ic_below_water; (8) ibuf0.Stall_l2(0); (9:11) (12:15) (16:19) (20) ibuf1.Rm_ib_iu4_val; (21) ibuf1.Uc_ib_iu4_...
Page 770
User’s manual a2 processor debug and trigger groups page 770 of 864 version 1.3 october 23, 2012 3 (0) iuq_slice0.Iu_fxu_dep0.Barrier_l2; (1) iuq_slice0.Iu_fxu_dep0.Is2_instr_is_barrier; (2) iuq_slice0.Iu_fxu_dep0.Is2_mult_hole_barrier; (3) iuq_slice0.Iu_fxu_dep0.Xu_barrier_l2; (4) iuq_slice0.Iu_fxu...
Page 771
User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 771 of 864 5 (0) iuq_slice0.Dec0.Is1_instr_v (1) iuq_slice0.Dec0.Is1_frt_v (2) iuq_slice0.Dec0.Is1_fra_v (3) iuq_slice0.Dec0.Is1_frb_v (4) iuq_slice0.Dec0.Is1_frc_v (5) iuq_slice0.Dec0.Is1_ldst (6) iuq_slice0.Dec0....
Page 772
User’s manual a2 processor debug and trigger groups page 772 of 864 version 1.3 october 23, 2012 6 (0) iuq_slice2.Dec0.Is1_instr_v (1) iuq_slice2.Dec0.Is1_frt_v (2) iuq_slice2.Dec0.Is1_fra_v (3) iuq_slice2.Dec0.Is1_frb_v (4) iuq_slice2.Dec0.Is1_frc_v (5) iuq_slice2.Dec0.Is1_ldst (6) iuq_slice2.Dec0....
Page 773
User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 773 of 864 trigger group signal list 0 (0) ibuf0.Bp_ib_iu4_val(0); (1) ibuf0.Rm_ib_iu4_val; (2) ibuf0.Uc_ib_iu4_val; (3) ibuf1.Bp_ib_iu4_val(0); (4) ibuf1.Rm_ib_iu4_val; (5) ibuf1.Uc_ib_iu4_val; (6) ibuf2.Bp_ib_iu4...
Page 774
User’s manual a2 processor debug and trigger groups page 774 of 864 version 1.3 october 23, 2012 table c-5. Iu debug mux2 debug and trigger groups (sheet 1 of 5) debug group signal list 0 --group 0 -iuq_ic_select (0) xu_iu_flush_l2(0) (1) uc_flush_tid(0) (2) ib_ic_iu5_redirect_tid(0) (3) bp_ic_iu5_r...
Page 775
User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 775 of 864 1 --group 1 - iuq_ic_dir (0:10) (11:21) (22) dbg_dir_write_l2 (23) data_write (24:31) (32:35) (36) dbg_dir_rd_act_l2 (37) icm_icd_dir_write_endian (38:43) (44:47) (48:51) (52:55) (56:59) (60:63) (64:67) ...
Page 776
User’s manual a2 processor debug and trigger groups page 776 of 864 version 1.3 october 23, 2012 5 --group 5 - iuq_ic_miss (0:11) (12:23) (24) miss_tid2_sm_l2(0) (25) miss_tid3_sm_l2(0) (26:35) (36:39) (40:43) (44:47) (48:59) (60:63) dropped] (64:67) (68:71) (72:75) (76:79) (80:83) (84:87) 6 --group...
Page 777
User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 777 of 864 9 --group 9 - iuq_ic_ierat (0:67) (68) ex3_eratsx_data_q(1) --cam_hit delayed (69) iu2_debug_q(16)[iu1_multihit] (70:74) (75) (76) iu2_debug_q(1)[comp_invalidate] (77) enabled (78) iu2_debug_q(3)[’0’] (7...
Page 778
User’s manual a2 processor debug and trigger groups page 778 of 864 version 1.3 october 23, 2012 c.6 mmu and pc debug select register and debug group tables table c-6. Mmu and pc debug select register (mpdsr) trigger group signal list 0 (0) iuq_ic_select0.Xu_icbi_buffer_val(0) (1) iuq_ic_select0.Bac...
Page 779
User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 779 of 864 39 debug group output select [0:21] 0 determines which signal group is put on trace data out [0:21]. 0 trace data in [0:21] is routed onto the trace bus. 1 debug group rotate output [0:21] is placed onto...
Page 780
User’s manual a2 processor debug and trigger groups page 780 of 864 version 1.3 october 23, 2012 55 debug group output select [0:21] 0 determines which signal group is put on trace data out [0:21]. 0 trace data in [0:21] is routed onto the trace bus. 1 debug group rotate output [0:21] is placed onto...
Page 781
User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 781 of 864 table c-7. Mmu debug multiplexer debug and trigger groups (sheet 1 of 16) debug group signal list 0 dbg_group0(0) dbg_group0(1) dbg_group0(2 to 3) dbg_group0(4 to 13) dbg_group0(14) dbg_group0(15) dbg_gr...
Page 782
User’s manual a2 processor debug and trigger groups page 782 of 864 version 1.3 october 23, 2012 1 --group1 (invalidate, local generation) dbg_group1(0 to 4) dbg_group1(5) dbg_group1(6 to 7) dbg_group1(8 to 9) dbg_group1(10) dbg_group1(11) dbg_group1(12) dbg_group1(13) dbg_group1(14) dbg_group1(15) ...
Page 783
User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 783 of 864 4 --group4 (sequencers, the big picture) dbg_group4(0 to 5) dbg_group4(6 to 7) dbg_group4(8 to 10) dbg_group4(11) dbg_group4(12 to 15) dbg_group4(16 to 19) dbg_group4(20 to 23) dbg_group4(24 to 27) dbg_g...
Page 784
User’s manual a2 processor debug and trigger groups page 784 of 864 version 1.3 october 23, 2012 5 --group5 (tlb_req) dbg_group5(0) dbg_group5(1 to 2) dbg_group5(3 to 6) dbg_group5(7) dbg_group5(8 to 9) dbg_group5(10 to 11) dbg_group5(12 to 15) dbg_group5(16 to 19) dbg_group5(20 to 27) dbg_group5(28...
Page 785
User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 785 of 864 7 --group7 (detailed compare/match) dbg_group7(0) dbg_group7(1 to 2) dbg_group7(3 to 5) dbg_group7(6 to 7) dbg_group7(8 to 9) dbg_group7(10 to 12) dbg_group7(13 to 19) dbg_group7(20 to 23) debug_d(24 to ...
Page 786
User’s manual a2 processor debug and trigger groups page 786 of 864 version 1.3 october 23, 2012 7 (continued) debug_d(78) tlb_cmp_dbg_way3_addr_match; debug_d(79) tlb_cmp_dbg_way3_pgsize_match; debug_d(80) tlb_cmp_dbg_way3_class_match; debug_d(81) tlb_cmp_dbg_way3_extclass_match; debug_d(82) tlb_cm...
Page 787
User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 787 of 864 9 --group9 (tlbwe, ptereload write control) dbg_group9(0) dbg_group9(1 to 2) dbg_group9(3 to 5) dbg_group9(6) dbg_group9(7) dbg_group9(8) dbg_group9(9) dbg_group9(10 to 11) dbg_group9(12) dbg_group9(13 t...
Page 788
User’s manual a2 processor debug and trigger groups page 788 of 864 version 1.3 october 23, 2012 10 --group10 (erat reload bus, epn) --------> can multiplex tlb_datain(0:83) epn for tlbwe/ptereload operations dbg_group10a(0) dbg_group10a(1 to 2) dbg_group10a(3 to 5) dbg_group10a(6 to 7) dbg_group10a...
Page 789
User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 789 of 864 11 --group11 (erat reload bus, rpn) --------> can multiplex tlb_datain(84:167) rpn for tlbwe/ptereload operations dbg_group11a(0) dbg_group11a(1 to 2) dbg_group11a(3 to 5) dbg_group11a(6 to 7) dbg_group1...
Page 790
User’s manual a2 processor debug and trigger groups page 790 of 864 version 1.3 october 23, 2012 12 --group12 (reservations) dbg_group12a(0) dbg_group12a(1 to 2) dbg_group12a(3 to 5) dbg_group12a(6 to 7) dbg_group12a(8 to 11) dbg_group12a(12 to 15) dbg_group12a(16 to 19) debug_d(group12_offset+20) d...
Page 791
User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 791 of 864 12 (continued) dbg_group12a(60 to 63) dbg_group12a(64 to 67) tlbilx, tlbwe, ptereload dbg_group12a(68 to 71) dbg_group12a(72 to 75) dbg_group12a(76 to 79) dbg_group12a(80 to 83) tlbilx, tlbwe, ptereload ...
Page 792
User’s manual a2 processor debug and trigger groups page 792 of 864 version 1.3 october 23, 2012 13 --group13 (lrat match logic) dbg_group13a(0) dbg_group13a(1) dbg_group13a(2 to 3) dbg_group13a(4 to 5) and tlb_ctl_dbg_tag1_type(2)); -- tlbsx,tlbre,tlbwe,ptereload dbg_group13a(6) dbg_group13a(7) dbg...
Page 793
User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 793 of 864 13 (continued) dbg_group13b(0 to 83) dbg_group13b(84) (tlb_cmp_dbg_tag5_lru_dataout(0) and tlb_cmp_dbg_tag5_wayhit(0)) or (tlb_cmp_dbg_tag5_lru_dataout(1) and tlb_cmp_dbg_tag5_wayhit(1)) or (tlb_cmp_dbg_...
Page 794
User’s manual a2 processor debug and trigger groups page 794 of 864 version 1.3 october 23, 2012 14 --group14 (htw control) dbg_group14a(0 to 1) dbg_group14a(2 to 3) dbg_group14a(4) dbg_group14a(5 to 6) dbg_group14a(7) dbg_group14a(8 to 9) dbg_group14a(10 to 51) dbg_group14a(52 to 54) dbg_group14a(5...
Page 795
User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 795 of 864 15 --group15 (ptereload pte) dbg_group15a(0 to 1) dbg_group15a(2 to 4) dbg_group15a(5 to 7) dbg_group15a(8) dbg_group15a(9 to 21) dbg_group15a(22) dbg_group15a(23) dbg_group15a(24 to 87) dbg_group15b(0 t...
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User’s manual a2 processor debug and trigger groups page 796 of 864 version 1.3 october 23, 2012 3 trg_group3a(0) spr_dbg_slowspr_val_int; trg_group3a(1) spr_dbg_slowspr_rw_int; trg_group3a(2 to 3) trg_group3a(4) spr_dbg_match_64b; trg_group3a(5) trg_group3a(6) spr_dbg_match_any_mas; trg_group3a(7) ...
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User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 797 of 864 3 dbg_group3 (0:3) dbg_group3 (4:5) dbg_group3 (6:7) dbg_group3 (8:23) dbg_group3 (24:25) dbg_group3 (26:33) dbg_group3 (34:41) dbg_group3 (42:46) dbg_group3 (47:53) dbg_group3 (54:87) 4 dbg_group4 (0:1)...
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User’s manual a2 processor debug and trigger groups page 798 of 864 version 1.3 october 23, 2012 c.7 xu debug select register1 and debug group tables table c-9. Xu debug select register1 (xdsr1) register short name: xdsr1 access: rw register address: x‘3e’ rw scan ring: dcfg initial value: 0x0000000...
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User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 799 of 864 46 trigger group output select [0:5] 0 determines which signal group is put on trigger data out [0:5] 0 trigger data in [0:5] is routed onto the trigger bus. 1 trigger group rotate output [0:5] is placed...
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User’s manual a2 processor debug and trigger groups page 800 of 864 version 1.3 october 23, 2012 63 trigger group output select [6:11] 0 determines which signal group is put on trigger data out [6:11]. 0 trigger data in [6:11] is routed onto the trigger bus. 1 trigger group rotate output [6:11] is p...
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User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 801 of 864 2 0:63 ex7_rt_q 64:67 dec_ex2_tid 68:68 ex1_is_mfocrf_q(0) 69:69 ex1_log_sel_q 70:70 ex2_rt_sel_q(0) 71:71 ex3_div_done_q(0) 72:72 ex4_spr_sel_q(0) 73:73 ex5_dtlb_sel_q(0) 74:74 ex5_itlb_sel_q(0) 75:75 e...
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User’s manual a2 processor debug and trigger groups page 802 of 864 version 1.3 october 23, 2012 6 0:3 ex6_val_dbg_q 4:7 ex5_fu_cr_val_q 8:11 ex5_fu_cr_noflush_q 12:13 ex1_cr_so_update_q(0 to 1) 14:14 ex1_is_mcrf_q 15:15 ex2_alu_cmp_q 16:16 ex3_div_done_q 17:17 ex5_watch_we_q 18:18 ex5_dp_instr_q 19...
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User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 803 of 864 7 0:3 ex6_val_dbg_q 4:7 ex5_fu_cr_val_q 8:11 ex5_fu_cr_noflush_q 12:13 ex1_cr_so_update_q(0 to 1) 14:14 ex1_is_mcrf_q 15:15 ex2_alu_cmp_q 16:16 ex3_div_done_q 17:17 ex5_watch_we_q 18:18 ex5_dp_instr_q 19...
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User’s manual a2 processor debug and trigger groups page 804 of 864 version 1.3 october 23, 2012 8 0:21 (0:21=>'0') 22:25 ex5_val 26:26 dec_byp_rf1_ov_used 27:27 dec_byp_rf1_ca_used 28:32 rf1_byp_ov_pri(2 to 6) 33:37 rf1_byp_ca_pri(2 to 6) 38:41 ex2_xer(0 to 3) 42:45 ex3_xer(0 to 3) 46:49 ex4_xer(0 ...
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User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 805 of 864 10 0:3 rf1_ucode_val_q 4:7 rf1_val_q 8:39 rf1_instr_q 40:40 rf1_cache_acc 41:41 rf1_axu_ld_or_st_q 42:42 rf1_is_any_load_axu 43:43 rf1_is_any_store_axu 44:44 rf1_derat_is_load 45:45 rf1_derat_is_store 46...
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User’s manual a2 processor debug and trigger groups page 806 of 864 version 1.3 october 23, 2012 13 0:0 dcarr_wren_q 1:1 rel_ci_dly_q 2:2 ex4_saxu_instr_q 3:3 ex4_stgpr_instr_q 4:4 ex3_fu_st_val_q 5:5 ex4_le_mode_q 6:10 ex3_st_rot_sel_q 11:21 ex4_p_addr_q 22:22 ex3_store_instr_q 23:23 rel_data_val_s...
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User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 807 of 864 table c-11. Xu debug mux2 debug and trigger groups (sheet 1 of 11) debug group signal list 0 0:0 ex5_xu_val_q(0) 1:1 ex5_axu_val_dbg_q(0) 2:2 ex5_instr_cpl_dbg_q(0) 3:3 ex5_ucode_val_dbg_q(0) 4:4 ex5_uco...
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User’s manual a2 processor debug and trigger groups page 808 of 864 version 1.3 october 23, 2012 4 0:0 ex5_xu_val_dbg_opc(0) 1:1 ex5_axu_val_dbg_opc(0) 2:2 ex5_instr_cpl_dbg_q(0) 3:3 ex5_ucode_val_dbg_q(0) 4:4 ex5_ucode_end_dbg_q(0) 5:5 ex5_xu_val_dbg_opc(1) 6:6 ex5_axu_val_dbg_opc(1) 7:7 ex5_instr_...
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User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 809 of 864 9 0:0 ex5_xu_val_q(0) 1:1 ex5_axu_val_dbg_q(0) 2:2 ex5_instr_cpl_dbg_q(0) 3:3 ex5_ucode_val_dbg_q(0) 4:4 ex5_ucode_end_dbg_q(0) 5:5 ex5_in_ucode_q(0) 6:11 ex5_flush_pri_enc_dbg(0) 12:12 ex2_br_flush(0) 1...
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User’s manual a2 processor debug and trigger groups page 810 of 864 version 1.3 october 23, 2012 10 0:0 ex5_xu_val_q(0) 1:1 ex5_axu_val_dbg_q(0) 2:2 ex5_instr_cpl_dbg_q(0) 3:3 ex5_ucode_val_dbg_q(0) 4:4 ex5_ucode_end_dbg_q(0) 5:5 ex5_in_ucode_q(0) 6:11 ex5_flush_pri_enc_dbg(0) 12:12 ex2_br_flush(0) ...
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User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 811 of 864 11 0:0 ex5_xu_val_q(0) 1:1 ex5_axu_val_dbg_q(0) 2:2 ex5_instr_cpl_dbg_q(0) 3:3 ex5_ucode_val_dbg_q(0) 4:4 ex5_ucode_end_dbg_q(0) 5:5 ex5_in_ucode_q(0) 6:11 ex5_flush_pri_enc_dbg(0) 12:12 ex2_br_flush(0) ...
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User’s manual a2 processor debug and trigger groups page 812 of 864 version 1.3 october 23, 2012 12 0:0 ex5_xu_val_q(0) 1:1 ex5_axu_val_dbg_q(0) 2:2 ex5_instr_cpl_dbg_q(0) 3:3 ex5_ucode_val_dbg_q(0) 4:4 ex5_ucode_end_dbg_q(0) 5:5 ex5_in_ucode_q(0) 6:11 ex5_flush_pri_enc_dbg(0) 12:12 ex2_br_flush(0) ...
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User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 813 of 864 13 0:61 ex5_siar_q 62:62 ex5_siar_gs_q 63:63 ex5_siar_pr_q 64:67 siar_cm 68:68 ex5_siar_issued_q 69:69 ex5_siar_cpl_q 70:71 ex5_siar_tid_q 72:75 ex4_xu_issued_q 76:79 ex4_axu_issued_q 80:83 ex5_instr_cpl...
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User’s manual a2 processor debug and trigger groups page 814 of 864 version 1.3 october 23, 2012 15 0:31 ex1_instr(0:31) 32:32 ex5_xu_val_q(0) 33:33 ex5_axu_val_dbg_q(0) 34:34 ex5_instr_cpl_dbg_q(0) 35:35 ex5_ucode_val_dbg_q(0) 36:36 ex5_ucode_end_dbg_q(0) 37:37 ex5_in_ucode_q(0) 38:43 ex5_flush_pri...
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User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 815 of 864 28 0:3 rf0_val_q 4:9 rf0_instr_q(0:5) 10:19 rf0_instr_q(21:30) 20:25 hold_instr_q(0:5) 26:35 hold_instr_q(21:30) 36:36 rf0_ta_vld_q 37:37 rf0_s1_vld_q 38:38 rf0_s2_vld_q 39:39 rf0_s3_vld_q 40:43 xu_rf0_f...
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User’s manual a2 processor debug and trigger groups page 816 of 864 version 1.3 october 23, 2012 29 0:3 rf0_val_q 4:35 rf0_instr_q 36:41 rf0_ta_q 42:44 rf0_error_q 45:45 rf0_match_q 46:46 rf0_is_ucode_q 47:47 rf0_s1_vld_q 48:48 rf0_s2_vld_q 49:49 rf0_s3_vld_q 50:50 rf0_axu_ld_or_st_q 51:51 rf0_axu_s...
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User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 817 of 864 c.8 xu debug select register2 and debug group tables table c-12. Xu debug select register2 (xdsr2) 0 0 ex5_xu_val_q(0) 1 ex5_axu_val_dbg_q(0) 2 ex5_instr_cpl_dbg_q(0) 3 ex5_ucode_val_dbg_q(0) 4 ex5_ucode...
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User’s manual a2 processor debug and trigger groups page 818 of 864 version 1.3 october 23, 2012 41 debug group output select [44:65] 0 determines which signal group is put on trace data out [44:65]. 0 trace data in [44:65] is routed onto the trace bus. 1 debug group rotate output [44:65] is placed ...
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User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 819 of 864 58 debug group output select [66:87] 0 determines which signal group is put on trace data out [66:87]. 0 trace data in [66:87] is routed onto the trace bus. 1 debug group rotate output [66:87] is placed ...
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User’s manual a2 processor debug and trigger groups page 820 of 864 version 1.3 october 23, 2012 1 0:7 ex4_way_hit_q 8:12 ex4_congr_cl_q ex4_p_addr_q(53:57) 13:13 binv4_ex4_xuop_upd_q 14:17 ex4_dir_access_op 18:21 ex4_p_addr(58:61) 22:22 ldq_rel_back_invalidated 23:23 ldq_rel_ci 24:31 ld_rel_val_l2...
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User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 821 of 864 3 same as group2 except for way b, w=1 4 same as group2 except for way c, w=2 5 same as group2 except for way d, w=3 6 same as group2 except for way e, w=4 7 same as group2 except for way f, w=5 8 same a...
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User’s manual a2 processor debug and trigger groups page 822 of 864 version 1.3 october 23, 2012 11 0:0 ldq_rel1_val 1:1 ldq_rel_mid_val 2:2 ldq_rel3_val 3:3 ldq_rel_retry_val 4:4 ldq_recirc_rel_val 5:7 ldq_rel_tag 8:8 ldq_rel_set_val 9:9 ldq_rel_ci 10:10 ldq_rel_back_invalidated 11:12 ldq_rel_ta_gp...
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User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 823 of 864 13 0:0 ex9_ld_par_err_q 1:1 rel_in_progress 2:3 dcpar_err_ind_sel 4:5 dcpar_err_cntr_q 6:6 dcpar_err_push_queue 7:14 dcpar_err_way_q 15:15 dcpar_err_stg2_q 16:16 ldq_rel1_val 17:17 ldq_rel_mid_val 18:18 ...
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User’s manual a2 processor debug and trigger groups page 824 of 864 version 1.3 october 23, 2012 15 0:0 l2req_l2 1:6 l2req_ttype_l2 7:7 l2req_wimg_l2(1) 8:8 l2req_wimg_l2(3) 9:9 l2req_endian_l2 10:13 l2req_st_byte_enbl_l2(0:3) 14:21 l2req_ra_l2(22:29) 22:43 l2req_ra_l2(30:51) 44:55 l2req_ra_l2(52:63...
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User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 825 of 864 19 0:0 l2req_l2 1:4 l2req_ld_core_tag_l2(1:4) 5:10 l2req_ttype_l2 11:11 l2req_wimg_l2(1) 12:12 anaclat_data_coming 13:13 anaclat_data_val 14:14 an_ac_reld_crit_qw 15:15 reserved. This bit is set to 0 at ...
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User’s manual a2 processor debug and trigger groups page 826 of 864 version 1.3 october 23, 2012 22 0:7 l_m_rel_hit_beat0_l2 8:15 l_m_rel_hit_beat1_l2 16:23 l_m_rel_hit_beat2_l2 24:31 l_m_rel_hit_beat3_l2 32:39 l_m_rel_val_c_i_dly 40:47 lmq_back_invalidated_l2(0:lmq_entries-1) 48:55 complete_qentry(...
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User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 827 of 864 24 0 i1_g1_flush 1 ld_queue_full 2 ex4_drop_ld_req 3 ex5_flush_l2 4 ex5_stg_flush 5:10 cmd_type_ld(0:5) 11:18 ex4_loadmiss_qentry(0:lmq_entries-1) 19:26 ld_entry_val_l2(0:lmq_entries-1) 27:34 ld_rel_val_...
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User’s manual a2 processor debug and trigger groups page 828 of 864 version 1.3 october 23, 2012 26 0 ifetch_req_l2 1:38 ifetch_ra_l2 39:42 ifetch_thread_l2 43 i_f_q0_val_l2 44 i_f_q1_val_l2 45 i_f_q2_val_l2 46 i_f_q3_val_l2 47 send_if_req_l2 48 send_ld_req_l2 49 send_mm_req_l2 50 iu_sent_val 51 l2r...
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User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 829 of 864 29 0:3 dir_wr_enable_int 4:11 dir_wr_way_int 12:16 dir_arr_wr_addr_int 17:17 recirc_rel_val_q 18:21 dir_arr_wr_data_int(31:34) 22:22 ex1_dir_acc_val 23:23 ex1_l2_inv_val 24:24 binv1_ex1_stg_act 25:29 lwr...
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User’s manual a2 processor debug and trigger groups page 830 of 864 version 1.3 october 23, 2012 table c-14. Xu debug mux4 debug and trigger groups (sheet 1 of 2) debug group signal list 0 0:3 ex6_valid_q(0:3) 4:35 ex1_instr_q(0:31) 36:36 ex3_hypv_spr_q 37:37 ex3_illeg_spr_q 38:38 ex3_priv_spr_q 39:...
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User’s manual a2 processor version 1.3 october 23, 2012 debug and trigger groups page 831 of 864 1 0:0 lsu_xu_dbell_val_q 1:5 lsu_xu_dbell_type_q 6:6 lsu_xu_dbell_lpid_match_q 7:7 lsu_xu_dbell_brdcast_q 8:21 lsu_xu_dbell_pirtag_q 22:25 spr_ccr0_we_rev 26:29 quiesced_q 30:33 iu_quiesce_q 34:37 lsu_qu...
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User’s manual a2 processor debug and trigger groups page 832 of 864 version 1.3 october 23, 2012.
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User’s manual a2 processor version 1.3 october 23, 2012 instruction execution performance and code optimizations page 833 of 864 appendix d. Instruction execution performance and code optimizations the instruction timing information and code optimization guidelines provided in this appendix can help...
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User’s manual a2 processor instruction execution performance and code optimizations page 834 of 864 version 1.3 october 23, 2012 as illustrated in figure d-1, the front end of the pipeline consists of seven stages, iu0 through iu6. The front end is responsible for fetching instructions, predicting b...
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User’s manual a2 processor version 1.3 october 23, 2012 instruction execution performance and code optimizations page 835 of 864 d.1.2 stall stages the iu5 and iu6 stages are the major stall points in the pipeline. Instructions stall in iu5 primarily for register dependencies. Instructions stall in ...
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User’s manual a2 processor instruction execution performance and code optimizations page 836 of 864 version 1.3 october 23, 2012 each cycle, iu0 can begin fetching a fetch group for one thread. A fetch group consists of a 16-byte-aligned group of 16 bytes containing four instructions. If the instruc...
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User’s manual a2 processor version 1.3 october 23, 2012 instruction execution performance and code optimizations page 837 of 864 d.2.1 fetch arbitration each cycle, any or all of the threads might or might not be available to perform a fetch. The iu0 stage selects one thread for fetch in each cycle,...
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User’s manual a2 processor instruction execution performance and code optimizations page 838 of 864 version 1.3 october 23, 2012 d.2.5 i-erat misses i-erat misses are similar to instruction cache misses. If no mmu is present, the miss proceeds like an instruction through the pipeline and generate an...
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User’s manual a2 processor version 1.3 october 23, 2012 instruction execution performance and code optimizations page 839 of 864 figure d-3. Branch prediction.
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User’s manual a2 processor instruction execution performance and code optimizations page 840 of 864 version 1.3 october 23, 2012 d.2.7.1 branch direction prediction and the branch history table (bht) conditional branches are predicted using a gshare-like dynamic branch prediction mechanism that reme...
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User’s manual a2 processor version 1.3 october 23, 2012 instruction execution performance and code optimizations page 841 of 864 no mechanism exists to predict the target of branch-to-ctr instructions. To prevent interthread interference from instructions that are unlikely to be correct, the taken-b...
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User’s manual a2 processor instruction execution performance and code optimizations page 842 of 864 version 1.3 october 23, 2012 for instance, an integer load that hits in the data cache has a latency of five cycles. A dependent instruction issues a minimum of five cycles after the load issues. Most...
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User’s manual a2 processor version 1.3 october 23, 2012 instruction execution performance and code optimizations page 843 of 864 d.4.4 move to condition register fields (mtcrf) instruction dependency due to the nature of the mtcrf instruction, which can update any combination of the eight 4-bit cr f...
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User’s manual a2 processor instruction execution performance and code optimizations page 844 of 864 version 1.3 october 23, 2012 all other multiply instructions recirculate in the pipeline, and thus have a variable latency, block all other instructions from the same thread, and block multiplies and ...
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User’s manual a2 processor version 1.3 october 23, 2012 instruction execution performance and code optimizations page 845 of 864 d.4.11 tlb management instruction dependencies in addition to the potential slow spr dependency between an mtspr that targets the mmucr0 or mmucr1 and a subsequent mfspr i...
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User’s manual a2 processor instruction execution performance and code optimizations page 846 of 864 version 1.3 october 23, 2012 • wrtee • wrteei • isync • rfi • rfci • rfmci each of these instructions requires that the instruction stream be flushed and refetched immediately after the instruction’s ...
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User’s manual a2 processor version 1.3 october 23, 2012 instruction execution performance and code optimizations page 847 of 864 d.4.16 storage synchronization operations a sync instruction travels down the pipe and waits in ex4 for all load resources for that thread to become empty before confirmin...
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User’s manual a2 processor instruction execution performance and code optimizations page 848 of 864 version 1.3 october 23, 2012 d.5.2 loads load instructions proceed through ex1 to ex3 as described. If the load hits in the data cache, the data array is accessed in ex4. The load result is produced a...
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User’s manual a2 processor version 1.3 october 23, 2012 instruction execution performance and code optimizations page 849 of 864 d.5.4 load miss queue the load miss queue (lmq) is an 8-entry in-order queue of load misses and noncacheable loads. This queue holds load misses while they are outstanding...
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User’s manual a2 processor instruction execution performance and code optimizations page 850 of 864 version 1.3 october 23, 2012 d.6 interrupt effects in the a2 design, the process of “taking an interrupt” spans two cycles called irptcyclea and irptcycleb. This is necessitated by the need to allow a...
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User’s manual a2 processor version 1.3 october 23, 2012 instruction execution performance and code optimizations page 851 of 864 figure d-4. Fu dataflow.
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User’s manual a2 processor instruction execution performance and code optimizations page 852 of 864 version 1.3 october 23, 2012 d.7.1 general fpr operand dependency the general fpr operand dependency applies to floating-point math instructions that are not microcoded and do not have cr or fpscr dep...
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User’s manual a2 processor version 1.3 october 23, 2012 instruction execution performance and code optimizations page 853 of 864 the additional two cycles of latency applies to floating-point store instructions in all other cases as well, such as stores dependent on floating-point record forms or fl...
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User’s manual a2 processor instruction execution performance and code optimizations page 854 of 864 version 1.3 october 23, 2012 d.7.11 move to fpscr fields and fpscr dependencies it is important that an operation that is dependent on the fpscr not flush if it immediately following an oper- ation th...
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User’s manual a2 processor version 1.3 october 23, 2012 instruction execution performance and code optimizations page 855 of 864 machine check tlb parity error precise ex4 n 0x000 d-erat parity error precise i-erat parity error precise tlb multi-hit error precise tlb lru parity error precise d-erat ...
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User’s manual a2 processor instruction execution performance and code optimizations page 856 of 864 version 1.3 october 23, 2012 alignment any xu unaligned load or store with xucr0[flsta] = 1 precise ex4 n 0x0c0 any axu unaligned load or store with (xucr0[aflsta] = 1 or iu_xu_is2_axu_ldst_forceexcep...
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User’s manual a2 processor version 1.3 october 23, 2012 instruction execution performance and code optimizations page 857 of 864 decrementer decrementer async ex4 np1 0x160 fit fixed interval timer tick async ex4 np1 0x180 wdog watchdog timeout async ex4 n 0x1a0 dtlb d-erat miss and ccr2[notlb] = 1 ...
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User’s manual a2 processor instruction execution performance and code optimizations page 858 of 864 version 1.3 october 23, 2012 d.9 flush conditions table d-5 lists all the flush conditions for the a2 core. Hypv system call sc instruction lev = 1 precise ex4 np1 0x300 user decrementer user decremen...
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User’s manual a2 processor version 1.3 october 23, 2012 instruction execution performance and code optimizations page 859 of 864 ici precise ex4 np1 nia yes axu np1-flush precise 2 ex4 np1 nia no mtiar precise ex4 np1 rs no wait 0 precise ex4 np1 nia no wait 1 and reservation exists precise ex4 np1 ...
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User’s manual a2 processor instruction execution performance and code optimizations page 860 of 864 version 1.3 october 23, 2012 cache inhibited axu reload and axu load in ex2 precise ex4 n cia no load in ex2 with no store credits and xucr0[flh2l2] = 1 precise ex4 n cia no reload targeting axu colli...
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User’s manual a2 processor version 1.3 october 23, 2012 programming examples page 861 of 864 appendix e. Programming examples this appendix provides example code for floating-point conversions and floating-point selection, along with programming notes. E.1 wait instruction with fast wakeup for power...
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User’s manual a2 processor programming examples page 862 of 864 version 1.3 october 23, 2012 e.2.2 conversion from floating-point number to unsigned integer word the full convert to unsigned integer word function can be implemented using the following sequence, assuming that the floating-point value...
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User’s manual a2 processor version 1.3 october 23, 2012 programming examples page 863 of 864 e.3.1 comparison to zero e.3.2 minimum and maximum e.3.3 simple if-then-else constructions e.4 notes the following notes apply to the preceding examples and to the corresponding cases using the other three a...
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User’s manual a2 processor programming examples page 864 of 864 version 1.3 october 23, 2012 4. The optimized program gives the incorrect result if a and b are infinities of the same sign. (here it is assumed that invalid operation exceptions are disabled, in which case the result of the subtraction...