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Lattice Semiconductor LatticeEC User Manual

Summary of LatticeEC

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    April 2007 eb11_02.4 latticeec™ advanced evaluation board – revision c user’s guide.

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    2 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide introduction the latticeec advanced evaluation board provides a convenient platform to evaluate, test, and debug designs with the support of latticeec advanced interface capabilities. The board provides easy access...

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    3 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide additional resources additional resources related to this board can be downloaded from the web at www.Latticesemi.Com/boards. Click on the appropriate evaluation board, then see the blue “resources” box on the righ...

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    4 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide power setup for stand-alone board operation (i.E. Outside of a pci backplane), the evaluation board may be supplied with a sin- gle 5v dc power supply. On-board regulators will provide the supply voltages necessary...

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    5 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide table 5. V ccio selection jumper depending on the optional devices installed, some sysio banks may have restrictions. Table 6. Sysio bank considerations the following tables detail the various standards supported b...

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    6 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide table 8. Sysio standards supported per bank description top side banks 0-1 right side banks 2-3 bottom side banks 4-5 left side banks 6-7 types of i/o buffers single-ended single-ended and differential single-ended...

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    7 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide pci the latticeec evaluation board is designed to interface directly to pci 2.2 compatible systems using the pci edge connector. All necessary signals required for 32-bit pci operation are provided to the connector...

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    8 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide table 10. Pci connections – component side j6 description latticeec pin sysio bank 7 pci_intb_n aa12 5 8 pci_intd_n af13 5 9 pci_prsnt1_n ae13 5 11 pci_prsnt2_n ad13 5 16 pci_clk w1 6 18 pci_req_n aa13 4 20 pci_ad3...

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    9 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide spi 4.2 provided for spi 4.2 interfaces are two 6x10 backplane connectors. Connector j15 includes necessary data pairs and control signals for transmit data, while j14 has been configured for receive data. Standard...

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    10 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide table 12. Spi4.2 receive connections j14 description latticeec pin sysio bank notes a1 spi4_rdat_p14 l21 2 100-ohm lvds termination a2 spi4_rdat_p12 l24 2 100-ohm lvds termination a3 spi4_rdat_p10 k22 2 100-ohm lv...

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    11 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide ddr sdram the included 200-pin sodimm socket provides a built-in 16-bit interface to standard 2.5v ddr sdram memory modules. The required v ref and v tt voltages, as well as termination of each signal to v tt, are...

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    12 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide fcram included with the evaluation board is a 256mb (8mb x 4 x 8-bit) fcram device. All necessary voltages and signal terminations are supplied. Table 14. Fcram connections 119 sodimm_we_n b22 1 120 sodimm_cas_n a...

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    13 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide proto area for general purpose i/os, numerous test points are provided for direct access. The test points are labeled accord- ing to the associated i/o pin location and are listed in table 15. Table 15. Latticeec ...

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    14 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide sw3 is a momentary switch that, when pressed, forces the fpga to start its programming cycle. Sw4, when in position 1 (up), connects the download cable to the spi flash so that the user can program the flash. When...

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    15 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide miscellaneous ten sma connectors are provided for clocks or general purpose, user-definable signals. The center pin is wired to an i/o pin and the outer case is soldered to ground. Table 19 details to which i/o pi...

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    16 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide important note: the board must be un-powered when connecting, disconnecting, or reconnecting the isp- download cable. Always connect the ispdownload cable's gnd pin (black wire), before connecting any other jtag p...

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    17 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide figure 3. Device information dialog 6. Click the green ‘go’ button. This will begin the download process into the device. 7. Upon successful download, the device will be operational. Spi flash download for non-vol...

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    18 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide 7. Insert a new device into the chain (edit->add device). 8. In the resulting device information dialog, shown in figure 4, press the ‘select’ button. Figure 4. Device selector dialog 9. Use the pull-down menu to ...

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    19 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide figure 6. Spi device selection 12. Choose the ‘configuration data setup’ page, as shown in figure 14. Figure 7. Configuration data setup page 13. Click the ‘browse’ button near the top of the window. Browse to the...

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    20 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide spi flash download via jtag the latticeec device is capable of programming the spi flash device from its jtag port. 1. Install a jumper on jp7. This provides the cclk to gpio connection, as described in lattice te...

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    21 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide figure 9. Setting the device access options note: selection of the ‘advanced spi flash programming’ option allows the user to specify a data file other than the ispvm system default. This is necessary for the latt...

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    22 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide figure 11. Fpga device setup 9. Click the ‘browse’ button to select an alternate application specific data file. Choose the ‘ec20_adv_revc_spi_loader.Bit’ file. Note: this file is available in the design files sec...

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    23 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide figure 13. Spi device selection 14. Press ok to exit the fpga loader setup. 15. Click the green ‘go’ button. This will begin the download process into the flash device. 16. Remove the jumper at jp7. 17. Cycle the ...

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    24 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide appendix a. Schematics figure 14. Evaluation board block diagram 5 5 4 4 3 3 2 2 1 1 d d c c b b a a elt i t v e r r e b m u n t n e m u c o d e zi s t e e h s : et a d f o c a g b pf 2 7 6 dr a o b n oit a ul a v...

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    25 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide figure 15. 32-bit pci interface 5 5 4 4 3 3 2 2 1 1 d d c c b b a a pci_ ad 4 pci_ ad 6 pci_ ad 9 pc i_ ad 11 pc i_ ad 13 pc i_ ad 18 pc i_ ad 20 pc i_ ad 22 pc i_ ad 24 pc i_ ad 26 pc i_ ad 28 pc i_ ad 30 pc i_ a...

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    26 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide figure 16. Ddr sdram and fcram 5 5 4 4 3 3 2 2 1 1 d d c c b b a a 1 q d _ m a r c f 0 q d _ m a r c f 3 q d _ m a r c f 2 q d _ m a r c f 6 q d _ m a r c f 7 q d _ m a r c f 4 q d _ m a r c f 5 q d _ m a r c f 4 ...

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    27 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide figure 17. Spi 4.2 5 5 4 4 3 3 2 2 1 1 d d c c b b a a 8 n _ t a d r _ 4i p s 3 1 n _ t a d r _ 4i p s i p si s 0 1 p _ t a d r _ 4i p s 1 t a t s r _ 4i p s 4 p _ t a d r _ 4i p s 3 1 p _ t a d r _ 4i p s ni p s ...

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    28 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide figure 18. Jtag and fpga programming 5 5 4 4 3 3 2 2 1 1 d d c c b b a a n ti ni c _ h s a l f s 1 _ q _ h s a l f s s m t o d t _i c p j c c v s m t _i c p s m t k c t i d t _i c p i d t o d t k c t _i c p v 3. 3...

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    29 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide figure 19. Prototyping support 5 5 4 4 3 3 2 2 1 1 d d c c b b a a 6 w _ a m s 2 n _ a m s 2 w _ p t 1 n _ a m s 1 b _ p t 4 ni p _ 5 4 j r 3 ni p _ 5 4 j r 2 ni p _ 5 4 j r 1 ni p _ 5 4 j r 1 ni p _ 5 4 j r 6 ni ...

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    30 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide figure 20. Power 5 5 4 4 3 3 2 2 1 1 d d c c b b a a p w r _3. 3 v gat e _1. 2 p w r_ 1 .2 v v c c _1. 2 v v ccio _ 0 v ccio _ 1 v ccio _ 2 v ccio _ 3 v ccio _ 4 v ccio _ 5 v ccio _ 6 v ccio _ 7 v ccio _ 0 v ccio ...

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    31 latticeec advanced evaluation board – lattice semiconductor revision c user’s guide figure 21. Mechanical drawing 5 5 4 4 3 3 2 2 1 1 d d c c b b a a elt i t v e r r e b m u n t n e m u c o d e zi s t e e h s : et a d f o c g ni w ar d l a ci n a h c e m c 8 8 5 0 0 2 , 1 2 yr a u n a j , y a di ...

  • Page 32: Mouser Electronics

    Mouser electronics authorized distributor click to view pricing, inventory, delivery & lifecycle information: lattice : lfecp20e-h-ev.