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NEC PD789488 User Manual

Manual is about: PD789489 Subseries 8-Bit Single-Chip Microcontrollers

Summary of PD789488

  • Page 1

    User’s manual µ pd789488 µ pd789489 µ pd78f9488 µ pd78f9489 µ pd789489 subseries 8-bit single-chip microcontrollers printed in japan document no. U15331ej4v1ud00 (4th edition) date published july 2005 ns cp(k) ©.

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    2 user’s manual u15331ej4v1ud [memo].

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    User’s manual u15331ej4v1ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. Take c...

  • Page 4

    4 user’s manual u15331ej4v1ud eeprom and fip are trademarks of nec electronics corporation. Windows and windows nt are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. Pc/at is a trademark of international business machines corporation....

  • Page 5

    User’s manual u15331ej4v1ud 5 the information in this document is current as of july, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec el...

  • Page 6: Regional Information

    6 user’s manual u15331ej4v1ud regional information • device availability • ordering information • product release schedule • availability of related technical literature • development environment specifications (for example, specifications for third-party tools and components, host computers, power ...

  • Page 7

    User’s manual u15331ej4v1ud 7 major revisions in this edition page description throughout change of descriptions of µ pd789489, 78f9489 • change of status from under development to development completed • change of the subseries name to “ µ pd789489 subseries” pp.31 to 33 update of 1.5 78k/0s series...

  • Page 8

    8 user’s manual u15331ej4v1ud introduction target readers this manual is intended for user engineers who wish to understand the functions of the µ pd789489 subseries and design and develop application systems and programs for these devices. Target products: • µ pd789489 subseries: µ pd789488, 789489...

  • Page 9

    User’s manual u15331ej4v1ud 9 conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (overscore over pin or signal name) note: footnote for item marked with note in the text caution: information requiring particular attention remark: sup...

  • Page 10

    10 user’s manual u15331ej4v1ud documents related to flash memory writing document name document no. Pg-fp3 flash memory programmer user’s manual u13502e pg-fp4 flash memory programmer user’s manual u15260e other related documents document name document no. Semiconductor selection guide - products an...

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    User’s manual u15331ej4v1ud 11 contents chapter 1 general ..........................................................................................................................26 1.1 features ...........................................................................................................

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    12 user’s manual u15331ej4v1ud 3.1.4 data memory addressing .............................................................................................................. 54 3.2 processor registers .........................................................................................................

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    User’s manual u15331ej4v1ud 13 5.4.5 when subsystem clock is not used ............................................................................................. 104 5.4.6 subsystem clock ×4 multiplication circuit .......................................................................................

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    14 user’s manual u15331ej4v1ud 9.4.1 operation as watchdog timer ...................................................................................................... 171 9.4.2 operation as interval timer .................................................................................................

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    User’s manual u15331ej4v1ud 15 14.1 multiplier function...................................................................................................................267 14.2 multiplier configuration ...................................................................................................

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    16 user’s manual u15331ej4v1ud chapter 20 mask options ...........................................................................................................331 chapter 21 instruction set ......................................................................................................332 2...

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    User’s manual u15331ej4v1ud 17 list of figures (1/6) figure no. Title page 2-1 i/o circuit types ..........................................................................................................................................46 3-1 memory map ( µ pd789488).....................................

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    18 user’s manual u15331ej4v1ud list of figures (2/6) figure no. Title page 5-5 format of subclock control register............................................................................................................99 5-6 subclock selection register format .......................................

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    User’s manual u15331ej4v1ud 19 list of figures (3/6) figure no. Title page 7-21 timing of square-wave output with 16-bit resolution ..............................................................................149 7-22 timing of carrier generator operation (when cr60 = n, crh60 = m (m > n))............

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    20 user’s manual u15331ej4v1ud list of figures (4/6) figure no. Title page 11-4 format of asynchronous serial interface mode register 20 ......................................................................191 11-5 format of asynchronous serial interface status register 20.............................

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    User’s manual u15331ej4v1ud 21 list of figures (5/6) figure no. Title page 13-12 four-time-slice lcd display pattern and electrode connections ............................................................263 13-13 example of connecting four-time-slice lcd panel ..........................................

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    22 user’s manual u15331ej4v1ud list of figures (6/6) figure no. Title page 17-3 releasing halt mode by reset input.....................................................................................................311 17-4 releasing stop mode by interrupt...............................................

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    User’s manual u15331ej4v1ud 23 list of tables (1/3) table no. Title page 2-1 types of pin i/o circuits ..............................................................................................................................45 3-1 internal rom capacity..............................................

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    24 user’s manual u15331ej4v1ud list of tables (2/3) table no. Title page 10-1 configuration of 10-bit a/d converter ........................................................................................................173 11-1 configuration of serial interface 20 .....................................

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    User’s manual u15331ej4v1ud 25 list of tables (3/3) table no. Title page 21-1 operand identifiers and description methods ............................................................................................332 25-1 surface mounting type soldering conditions .....................................

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    26 user’s manual u15331ej4v1ud chapter 1 general 1.1 features • rom and ram capacities item data memory part number program memory (rom) internal ram lcd display ram µ pd789488 mask rom µ pd78f9488 flash memory 32 kb 1024 bytes 28 × 4 bits µ pd789489 mask rom 1536 bytes µ pd78f9489 flash memory 48 k...

  • Page 27

    Chapter 1 general user’s manual u15331ej4v1ud 27 1.3 ordering information part number package internal rom µ pd789488gc- ×××-8bt 80-pin plastic qfp (14 × 14) mask rom µ pd789488gk- ×××-9eu 80-pin plastic tqfp (fine pitch) (12 × 12) mask rom µ pd78f9488gc-8bt 80-pin plastic qfp (14 × 14) flash memory...

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    Chapter 1 general 28 user’s manual u15331ej4v1ud 1.4 pin configuration (top view) (1) µ pd789488, 78f9488 80-pin plastic qfp (14 × 14) µ pd789488gc- ×××-8bt µ pd78f9488gc-8bt µ pd789488gc- ×××-8bt-a µ pd78f9488gc-8bt-a 80-pin plastic tqfp (fine pitch) (12 × 12) µ pd789488gk- ×××-9eu µ pd78f9488gk-9e...

  • Page 29

    Chapter 1 general user’s manual u15331ej4v1ud 29 cautions 1. Connect the ic (internally connected) pin directly to v ss . 2. Connect the av dd pin to v dd . 3. Connect the av ss pin to v ss . Remark the parenthesized values apply to the µ pd78f9488 (2) µ pd789489, 78f9489 80-pin plastic qfp (14 × 14...

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    Chapter 1 general 30 user’s manual u15331ej4v1ud notes 1. Whether to use these pins as input port pins (p70 to p73) or segment outputs (s16 to s19) can be selected in 1-bit units by means of a mask option or port function register (refer to 4.3 (3) port function registers and chapter 20 mask options...

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    Chapter 1 general user’s manual u15331ej4v1ud 31 1.5 78k/0s series lineup the products in the 78k/0s series are listed below. The names enclosed in boxes are subseries names. 80-pin sio, 8-bit a/d converter, and resistance division type lcd (28 × 4) 52-pin 52-pin sio and resistance division type lcd...

  • Page 32

    Chapter 1 general 32 user’s manual u15331ej4v1ud the major functional differences between the subseries are listed below. Series for general-purpose applications and lcd drive timer v dd function subseries name rom capacity 8-bit 16-bit watc h wdt 8-bit a/d 10-bit a/d serial interface i/o min. Value...

  • Page 33

    Chapter 1 general user’s manual u15331ej4v1ud 33 series for assp timer v dd function subseries name rom capacity 8-bit 16-bit watc h wdt 8-bit a/d 10-bit a/d serial interface i/o min. Value remarks usb µ pd789800 8 kb 2 ch − − 1 ch − − 2 ch (usb: 1 ch) 31 4.0 v − inverter control µ pd789842 8 kb to ...

  • Page 34

    Chapter 1 general 34 user’s manual u15331ej4v1ud 1.6 block diagram 78k/0s cpu core rom (flash memory) ram v dd v ss ic0 (v pp ) cpt20/to20/p33 8-bit timer/ event counter 60 p00 to p07 port 0 p10 to p11 port 1 p20 to p25 port 2 p30 to p34 port 3 p50 to p53 port 5 p60 to p67 port 6 p70 to p73 note 1 p...

  • Page 35

    Chapter 1 general user’s manual u15331ej4v1ud 35 1.7 overview of functions (1/2) item µ pd789488 µ pd78f9488 µ pd789489 µ pd78f9489 rom 32 kb 32 kb (flash memory) 48 kb 48 kb (flash memory) high-speed ram 1024 bytes low-speed ram − 512 bytes internal memory lcd display ram 28 bytes main system clock...

  • Page 36

    Chapter 1 general 36 user’s manual u15331ej4v1ud (2/2) item µ pd789488 µ pd78f9488 µ pd789489 µ pd78f9489 supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = −40 to +85°c package • 80-pin plastic qfp (14 × 14) • 80-pin plastic tqfp (fine pitch) (12 × 12) an outline of the timer is...

  • Page 37

    User’s manual u15331ej4v1ud 37 chapter 2 pin functions 2.1 list of pin functions (1) port pins (1/2) pin name i/o function after reset alternate function p00 to p07 i/o port 0. 8-bit i/o port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can b...

  • Page 38

    Chapter 2 pin functions user’s manual u15331ej4v1ud 38 (1) port pins (2/2) pin name i/o function after reset alternate function p70 to p73 note 1 input port 7. 4-bit input port. (only when input port is selected by mask option or port function register) input − p80 to p87 note 2 i/o port 8. 8-bit i/...

  • Page 39

    Chapter 2 pin functions user’s manual u15331ej4v1ud 39 (2) non-port pins (2/2) pin name i/o function after reset alternate function s0 to s15 lcd controller/driver segment signal outputs low-level output – s16 to s19 note 1 only when segment output is selected by mask option – s20 to s27 note 2 outp...

  • Page 40

    Chapter 2 pin functions user’s manual u15331ej4v1ud 40 2.2 description of pin functions 2.2.1 p00 to p07 (port 0) these pins constitute an 8-bit i/o port. In addition, these pins enable key return signal detection. Port 0 can be specified in the following operation modes in 1-bit units. (1) port mod...

  • Page 41

    Chapter 2 pin functions user’s manual u15331ej4v1ud 41 2.2.4 p30 to p34 (port 3) these pins constitute a 5-bit i/o port. In addition, they also function as timer i/o, external interrupt input, and remote control receive data input note . Port 3 can be specified in the following operation modes in 1-...

  • Page 42

    Chapter 2 pin functions user’s manual u15331ej4v1ud 42 2.2.6 p60 to p67 (port 6) this is an 8-bit input-only port. In addition to a general-purpose input port function, it has a/d converter input and key return signal detection note functions. (1) port mode in this mode, p60 to p67 function as an 8-...

  • Page 43

    Chapter 2 pin functions user’s manual u15331ej4v1ud 43 2.2.13 reset this pin inputs an active-low system reset signal. 2.2.14 x1, x2 these pins are used to connect a crystal resonator for main system clock oscillation. To supply an external clock, input the clock to x1 and input the inverted signal ...

  • Page 44

    Chapter 2 pin functions user’s manual u15331ej4v1ud 44 2.2.21 ic0 (mask rom version only) the ic0 (internally connected) pin is used to set the µ pd789489 subseries in the test mode before shipment. In the normal operation mode, directly connect this pin to the v ss pin with as short a wiring length...

  • Page 45

    Chapter 2 pin functions user’s manual u15331ej4v1ud 45 2.3 pin i/o circuits and recommended connection of unused pins the i/o circuit type of each pin and recommended connection of unused pins are shown in table 2-1. For the i/o circuit configuration of each type, see figure 2-1. Table 2-1. Types of...

  • Page 46

    Chapter 2 pin functions user’s manual u15331ej4v1ud 46 table 2-1. Types of pin i/o circuits (2/2) pin name i/o circuit type i/o recommended connection of unused pins xt1 input connect to v ss . Xt2 – – leave open. Reset 2 input – ic0 connect directly to v ss . V pp – – independently connect a 10 k Ω...

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    Chapter 2 pin functions user’s manual u15331ej4v1ud 47 figure 2-1. I/o circuit types (2/2) type 13-w type 13-v data output disable input enable in/out n-ch v ss mask option v dd middle-voltage input buffer data output disable input enable in/out n-ch v ss middle-voltage input buffer type 17 type 18 ...

  • Page 48

    48 user’s manual u15331ej4v1ud chapter 3 cpu architecture 3.1 memory space the µ pd789489 subseries can access 64 kb of memory space. Figures 3-1 to 3-4 show the memory maps. Figure 3-1. Memory map ( µ pd789488) 8 0 0 0 h 7 f f f h special function registers 256 × 8 bits internal high-speed ram 1024...

  • Page 49

    Chapter 3 cpu architecture user’s manual u15331ej4v1ud 49 figure 3-2. Memory map ( µ pd78f9488) 8 0 0 0 h 7 f f f h special function registers 256 × 8 bits internal high-speed ram 1024 × 8 bits lcd display ram 28 × 4 bits f f f f h f f 0 0 h f e f f h f b 0 0 h f a f f h 0 0 0 0 h program memory spa...

  • Page 50

    Chapter 3 cpu architecture 50 user’s manual u15331ej4v1ud figure 3-3. Memory map ( µ pd789489) b f f f h 0 0 0 0 h 0 0 8 0 h 0 0 7 f h 0 0 4 0 h 0 0 3 f h 0 0 3 0 h 0 0 2 f h program area program area callt table area vector table area special function registers 256 × 8 bits internal high-speed ram ...

  • Page 51

    Chapter 3 cpu architecture user’s manual u15331ej4v1ud 51 figure 3-4. Memory map ( µ pd78f9489) b f f f h 0 0 0 0 h 0 0 8 0 h 0 0 7 f h 0 0 4 0 h 0 0 3 f h 0 0 3 0 h 0 0 2 f h f f f f h f f 0 0 h f e f f h f b 0 0 h f a f f h 0 0 0 0 h f a 1 c h f a 1 b h f a 0 0 h f 9 f f h f 7 0 0 h f 6 f f h c 0 ...

  • Page 52

    Chapter 3 cpu architecture 52 user’s manual u15331ej4v1ud 3.1.1 internal program memory space the internal program memory space stores programs and table data. This space is usually addressed by the program counter (pc). The µ pd789489 subseries provide internal rom (or flash memory) with the follow...

  • Page 53

    Chapter 3 cpu architecture user’s manual u15331ej4v1ud 53 3.1.2 internal data memory space (1) internal high-speed ram and internal low-speed ram the µ pd789489 subseries products incorporate the internal high-speed ram and internal low-speed ram of the following capacity for each product. The inter...

  • Page 54

    Chapter 3 cpu architecture 54 user’s manual u15331ej4v1ud 3.1.4 data memory addressing the µ pd789489 subseries is provided with a variety of addressing modes to make memory manipulation as efficient as possible. At the addresses corresponding to data memory area (fb00h to ffffh) especially, specifi...

  • Page 55

    Chapter 3 cpu architecture user’s manual u15331ej4v1ud 55 figure 3-6. Data memory addressing ( µ pd78f9488) special function registers 256 × 8 bits internal high-speed ram 1024 × 8 bits lcd display ram 28 × 4 bits f f f f h 8 0 0 0 h 7 f f f h 0 0 0 0 h direct addressing register indirect addressing...

  • Page 56

    Chapter 3 cpu architecture 56 user’s manual u15331ej4v1ud figure 3-7. Data memory addressing ( µ pd789489) direct addressing register indirect addressing based addressing sfr addressing short direct addressing f f f f h 0 0 0 0 h f f 0 0 h f e f f h f f 2 0 h f f 1 f h f e 2 0 h f e 1 f h f b 0 0 h ...

  • Page 57

    Chapter 3 cpu architecture user’s manual u15331ej4v1ud 57 figure 3-8. Data memory addressing ( µ pd78f9489) direct addressing register indirect addressing based addressing sfr addressing short direct addressing f f f f h c 0 0 0 h b f f f h 0 0 0 0 h f f 0 0 h f e f f h f f 2 0 h f f 1 f h f e 2 0 h...

  • Page 58

    Chapter 3 cpu architecture 58 user’s manual u15331ej4v1ud 3.2 processor registers the µ pd789489 subseries is provided with the following on-chip processor registers. 3.2.1 control registers the control registers contain special functions to control the program sequence status and stack memory. The ...

  • Page 59

    Chapter 3 cpu architecture user’s manual u15331ej4v1ud 59 (a) interrupt enable flag (ie) this flag controls interrupt request acknowledgement operations of the cpu. When 0, ie is set to the interrupt disabled status (di), and interrupt requests other than non-maskable interrupts are all disabled. Wh...

  • Page 60

    Chapter 3 cpu architecture 60 user’s manual u15331ej4v1ud (3) stack pointer (sp) this is a 16-bit register that holds the start address of the memory stack area. Only the internal high-speed ram area can be set as the stack area. Figure 3-11. Stack pointer configuration 0 15 sp14 sp15 sp sp13 sp12 s...

  • Page 61

    Chapter 3 cpu architecture user’s manual u15331ej4v1ud 61 3.2.2 general-purpose registers the general-purpose registers consist of eight 8-bit registers (x, a, c, b, e, d, l, and h). Each register can be used as an 8-bit register, or two 8-bit registers in pairs can be used as a 16-bit register (ax,...

  • Page 62

    Chapter 3 cpu architecture 62 user’s manual u15331ej4v1ud 3.2.3 special function registers (sfrs) unlike a general-purpose register, each special function register has a special function. The special function registers are allocated in the 256-byte area of ff00h to ffffh. Special function registers ...

  • Page 63

    Chapter 3 cpu architecture user’s manual u15331ej4v1ud 63 table 3-4. Special function registers (1/3) bit unit for manipulation address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff00h port 0 p0 √ √ − ff01h port 1 p1 √ √ − ff02h port 2 p2 √ √ − ff03h port 3 p3 √...

  • Page 64

    Chapter 3 cpu architecture 64 user’s manual u15331ej4v1ud table 3-4. Special function registers (2/3) bit unit for manipulation address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff40h 8-bit h width compare register 61 crh61 w − √ − undefined ff41h 8-bit timer m...

  • Page 65

    Chapter 3 cpu architecture user’s manual u15331ej4v1ud 65 table 3-4. Special function registers (3/3) bit unit for manipulation address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff80h a/d converter mode register 0 adml0 √ √ − ff84h analog input channel specific...

  • Page 66

    Chapter 3 cpu architecture 66 user’s manual u15331ej4v1ud 3.3 instruction address addressing an instruction address is determined by the program counter (pc) contents. The pc contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be f...

  • Page 67

    Chapter 3 cpu architecture user’s manual u15331ej4v1ud 67 3.3.2 immediate addressing [function] immediate data in the instruction word is transferred to the program counter (pc) and branched. This function is carried out when the call !Addr16 or br !Addr16 instruction is executed. Call !Addr16 and b...

  • Page 68

    Chapter 3 cpu architecture 68 user’s manual u15331ej4v1ud 3.3.3 table indirect addressing [function] table contents (branch destination address) of the particular location to be addressed by the lower 5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program coun...

  • Page 69

    Chapter 3 cpu architecture user’s manual u15331ej4v1ud 69 3.4 operand address addressing the following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 direct addressing [function] the memory indicated with i...

  • Page 70

    Chapter 3 cpu architecture 70 user’s manual u15331ej4v1ud 3.4.2 short direct addressing [function] the memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space is the 256-byte space fe20h to ff1fh where the addressing is applied. Inter...

  • Page 71

    Chapter 3 cpu architecture user’s manual u15331ej4v1ud 71 3.4.3 special function register (sfr) addressing [function] the memory-mapped special function registers (sfrs) are addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space ff00h to ffffh. H...

  • Page 72

    Chapter 3 cpu architecture 72 user’s manual u15331ej4v1ud 3.4.4 register addressing [function] in the register addressing mode, general-purpose registers are accessed as operands. The general-purpose register to be accessed is specified by a register specification code or functional name in the inst...

  • Page 73

    Chapter 3 cpu architecture user’s manual u15331ej4v1ud 73 3.4.5 register indirect addressing [function] in the register indirect addressing mode, memory is manipulated according to the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register ...

  • Page 74

    Chapter 3 cpu architecture 74 user’s manual u15331ej4v1ud 3.4.6 based addressing [function] 8-bit immediate data is added to the contents of the base register, that is, the hl register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive n...

  • Page 75

    User’s manual u15331ej4v1ud 75 chapter 4 port functions 4.1 port functions the µ pd789489 subseries provides the ports shown in figure 4-1, enabling various methods of control. The functions of each port are shown in table 4-1. Numerous other functions are provided that can be used in addition to th...

  • Page 76

    Chapter 4 port functions 76 user’s manual u15331ej4v1ud table 4-1. Port functions port name pin name function port 0 p00 to p07 i/o port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option r...

  • Page 77

    Chapter 4 port functions user’s manual u15331ej4v1ud 77 4.2.1 port 0 this is an 8-bit i/o port with an output latch. Port 0 can be specified in the input or output mode in 1-bit units by using port mode register 0 (pm0). When the p00 to p07 pins are used as input port pins, on-chip pull-up resistors...

  • Page 78

    Chapter 4 port functions 78 user’s manual u15331ej4v1ud 4.2.2 port 1 this is a 2-bit i/o port with an output latch. Port 1 can be specified in the input or output mode in 1-bit units by using port mode register 1 (pm1). When using the p10 and p11 pins as input port pins, on-chip pull-up resistors ca...

  • Page 79

    Chapter 4 port functions user’s manual u15331ej4v1ud 79 4.2.3 port 2 this is a 6-bit i/o port with an output latch. Port 2 can be specified in the input or output mode in 1-bit units by using port mode register 2 (pm2). When using the p20 to p25 pins as input port pins, on-chip pull-up resistors can...

  • Page 80

    Chapter 4 port functions 80 user’s manual u15331ej4v1ud figure 4-5. Block diagram of p21 internal bus v dd p21/so20/txd20 wr pub2 rd wr port wr pm pub21 alternate function output latch (p21) pm21 selector p-ch pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr...

  • Page 81

    Chapter 4 port functions user’s manual u15331ej4v1ud 81 figure 4-6. Block diagram of p22 and p25 p22/si20/ rxd20, p25/si10 wr pub2 rd wr port wr pm pub22, pub25 alternate function output latch (p22, p25) pm22, pm25 v dd p-ch internal bus selector pub2: pull-up resistor option register b2 pm: port mo...

  • Page 82

    Chapter 4 port functions 82 user’s manual u15331ej4v1ud figure 4-7. Block diagram of p23 internal bus v dd p-ch p23/sck10 wr pub2 rd wr port wr pm pub23 alternate function output latch (p23) pm23 alternate function selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 ...

  • Page 83

    Chapter 4 port functions user’s manual u15331ej4v1ud 83 figure 4-8. Block diagram of p24 internal bus v dd p24/so10 wr pub2 rd wr port wr pm pub24 alternate function output latch (p24) pm24 selector p-ch pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port...

  • Page 84

    Chapter 4 port functions 84 user’s manual u15331ej4v1ud 4.2.4 port 3 this is a 5-bit i/o port with an output latch. Port 3 can be specified in the input or output mode in 1-bit units by using port mode register 3 (pm3). When using the p30 to p34 pins as input port pins, on-chip pull-up resistors can...

  • Page 85

    Chapter 4 port functions user’s manual u15331ej4v1ud 85 figure 4-10. Block diagram of p34 (a) when µ pd789488, 78f9488 is used p34 wr pub3 rd wr port wr pm pub34 pm34 v dd p-ch internal bus selector output latch (p34) (b) when µ pd789489, 78f9489 is used p34/rin wr pub3 rd wr port wr pm pub34 pm34 v...

  • Page 86

    Chapter 4 port functions 86 user’s manual u15331ej4v1ud 4.2.5 port 5 this is a 4-bit n-ch open-drain i/o port with an output latch. Port 5 can be specified in the input or output mode in 1-bit units by using port mode register 5 (pm5). For a mask rom version, use of an on-chip pull-up resistor can b...

  • Page 87

    Chapter 4 port functions user’s manual u15331ej4v1ud 87 4.2.6 port 6 this is an 8-bit input-only port. This port is also used for the analog input of an a/d converter and key return signal input note . Figure 4-12 shows a block diagram of port 6. Note µ pd789489 and 78f9489 only. Figure 4-12. Block ...

  • Page 88

    Chapter 4 port functions 88 user’s manual u15331ej4v1ud figure 4-12. Block diagram of p60 to p67 (2/2) (b) when µ pd789489, 78f9489 is used v ref rd alternate function p60/ani0/kr10 to p67/ani7/kr17 + − krm010, krm014 to krm017 wr krm01 a/d converter internal bus krm01: key return mode register 01 r...

  • Page 89

    Chapter 4 port functions user’s manual u15331ej4v1ud 89 4.2.7 port 7 this is a 4-bit input-only port. Only the bits for which the port function is selected can be used, by using a mask option in the µ pd789488 and 789489 or port function register 7 (pf7) in the µ pd78f9488 and 78f9489. Figure 4-13 s...

  • Page 90

    Chapter 4 port functions 90 user’s manual u15331ej4v1ud 4.2.8 port 8 this is an 8-bit i/o port with an output latch. Only the bits for which the port function is selected can be used, by using a mask option in the µ pd789488 and 789489 or port function register 8 (pf8) in the µ pd78f9488 and 78f9489...

  • Page 91

    Chapter 4 port functions user’s manual u15331ej4v1ud 91 4.3 registers controlling port function the ports are controlled by the following three types of registers. • port mode registers (pm0 to pm3, pm5, pm8) • pull-up resistor option registers (pub0 to pub3) • port function registers (pf7, pf8) ( µ...

  • Page 92

    Chapter 4 port functions 92 user’s manual u15331ej4v1ud table 4-3. Port mode registers and output latch settings when using alternate functions alternate function pin name name i/o pm ×× p ×× p00 to p07 kr0 to kr7 or kr00 to kr07 input 1 × intp0 input 1 × to50 output 0 0 p30 tmi60 input 1 × intp1 in...

  • Page 93

    Chapter 4 port functions user’s manual u15331ej4v1ud 93 (2) pull-up resistor option registers (pub0 to pub3) these registers set whether to use on-chip pull-up resistors for pins p00 to p07, p10, p11, p20 to p25, and p30 to p34. An on-chip pull-up resistor can be used only for those bits set to the ...

  • Page 94

    Chapter 4 port functions 94 user’s manual u15331ej4v1ud 4.4 port function operation the operation of a port differs depending on whether the port is set in the input or output mode, as described below. 4.4.1 writing to i/o port (1) in output mode a value can be written to the output latch of a port ...

  • Page 95

    User’s manual u15331ej4v1ud 95 chapter 5 clock generator 5.1 clock generator functions the clock generator generates the clock to be supplied to the cpu and peripheral hardware. The following two types of system clock oscillators are used. • main system clock oscillator this circuit oscillates at 1....

  • Page 96

    Chapter 5 clock generator 96 user’s manual u15331ej4v1ud figure 5-1. Clock generator block diagram ( µ pd789488, 789489) f xt 8f xt f xtt x1 x2 xt1 xt2 f x f x 2 2 f xtt 2 1/2 prescaler standby controller wait controller mask option stop mcc pcc1 cls internal bus css0 frc scc internal bus timer 50 w...

  • Page 97

    Chapter 5 clock generator user’s manual u15331ej4v1ud 97 figure 5-2. Clock generator block diagram ( µ pd78f9488, 78f9489) subsystem clock oscillator f xt x1 x2 xt1 xt2 main system clock oscillator f x f x 2 2 f xtt 2 1/2 prescaler clock to peripheral hardware timer 50 watch timer lcd controller/dri...

  • Page 98

    Chapter 5 clock generator 98 user’s manual u15331ej4v1ud 5.3 registers controlling clock generator the clock generator is controlled by the following four registers. • processor clock control register (pcc) • subclock oscillation mode register (sckm) • subclock control register (css) • subclock sele...

  • Page 99

    Chapter 5 clock generator user’s manual u15331ej4v1ud 99 (2) subclock oscillation mode register (sckm) sckm selects a feedback resistor for the subsystem clock, and controls the oscillation of the clock. Sckm is set with a 1-bit or 8-bit memory manipulation instruction. Reset input sets sckm to 00h....

  • Page 100

    Chapter 5 clock generator 100 user’s manual u15331ej4v1ud (4) subclock selection register (ssck) ( µ pd78f9488, 78f9489 only) this register is used to control the operation of the ×4 subsystem clock multiplication circuit. Ssck is set via a 1-bit or 8-bit memory manipulation instruction. Reset input...

  • Page 101

    Chapter 5 clock generator user’s manual u15331ej4v1ud 101 5.4 system clock oscillators 5.4.1 main system clock oscillator the main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 mhz typ.) connected across the x1 and x2 pins. An external clock can also be input to the ...

  • Page 102

    Chapter 5 clock generator 102 user’s manual u15331ej4v1ud 5.4.2 subsystem clock oscillator the subsystem clock oscillator is oscillated by the crystal resonator (32.768 khz typ.) connected across the xt1 and xt2 pins. An external clock can also be input to the circuit. In this case, input the clock ...

  • Page 103

    Chapter 5 clock generator user’s manual u15331ej4v1ud 103 5.4.3 example of incorrect resonator connection figure 5-9 shows examples of incorrect resonator connection. Figure 5-9. Examples of incorrect resonator connection (1/2) (a) too long wiring (b) crossed signal line v ss x1 x2 v ss x1 x2 portn ...

  • Page 104

    Chapter 5 clock generator 104 user’s manual u15331ej4v1ud figure 5-9. Examples of incorrect resonator connection (2/2) (e) signal is fetched v ss x1 x2 remark when using the subsystem clock, read x1 and x2 as xt1 and xt2, respectively, and connect a resistor to xt2 in series. 5.4.4 divider circuit t...

  • Page 105

    Chapter 5 clock generator user’s manual u15331ej4v1ud 105 5.5 clock generator operation the clock generator generates the following clocks and controls the operation modes of the cpu, such as the standby mode. • main system clock f x • subsystem clock f xt • cpu clock f cpu • clock to peripheral har...

  • Page 106

    Chapter 5 clock generator 106 user’s manual u15331ej4v1ud 5.6 changing setting of system clock and cpu clock 5.6.1 time required for switching between system clock and cpu clock the cpu clock can be selected by using bit 1 (pcc1) of the processor clock control register (pcc) and bit 4 (css0) of the ...

  • Page 107

    Chapter 5 clock generator user’s manual u15331ej4v1ud 107 5.6.2 switching between system clock and cpu clock the following figure illustrates how the cpu clock and system clock switch. Figure 5-10. Switching between system clock and cpu clock system clock cpu clock interrupt request signal reset v d...

  • Page 108

    108 user’s manual u15331ej4v1ud chapter 6 16-bit timer 20 6.1 16-bit timer 20 functions 16-bit timer 20 has the following functions. • timer interrupt • timer output • count value capture (1) timer interrupt an interrupt is generated when a count value and compare value match. (2) timer output timer...

  • Page 109

    Chapter 6 16-bit timer 20 user’s manual u15331ej4v1ud 109 figure 6-1. Block diagram of 16-bit timer 20 cpt20/to20 /intp3/p33 internal bus internal bus 16-bit timer mode control register 20 (tmc20) 16-bit timer mode control register 20 tof20 cpt201 cpt200 toc20 tcl201 tcl200 toe20 f x f x /2 2 edge d...

  • Page 110

    Chapter 6 16-bit timer 20 110 user’s manual u15331ej4v1ud (4) 16-bit counter read buffer 20 this buffer is used to latch and hold the count value for tm20. 6.3 registers controlling 16-bit timer 20 16-bit timer 20 is controlled by the following three registers. • 16-bit timer mode control register 2...

  • Page 111

    Chapter 6 16-bit timer 20 user’s manual u15331ej4v1ud 111 figure 6-2. Format of 16-bit timer mode control register 20 symbol 5 4 3 2 1 address after reset r/w tmc20 tod20 tof20 cpt201 cpt200 toc20 tcl201 tcl200 toe20 ff48h 00h r/w note 1 tod20 timer output data 0 timer output is “0” 1 timer output i...

  • Page 112

    Chapter 6 16-bit timer 20 112 user’s manual u15331ej4v1ud (2) port mode register 3 (pm3) this register is used to set the i/o mode of port 3 in 1-bit units. When using the p33/intp3/cpt20/to20 pin as a capture input (cpt20), set pm33 to 1. When using the above pin as a timer output (to20), set the p...

  • Page 113

    Chapter 6 16-bit timer 20 user’s manual u15331ej4v1ud 113 6.4 16-bit timer 20 operation 6.4.1 operation as timer interrupt 16-bit timer 20 can generate interrupts repeatedly each time the free-running counter value reaches the value set to cr20. Since this counter is not cleared and holds the count ...

  • Page 114

    Chapter 6 16-bit timer 20 114 user’s manual u15331ej4v1ud figure 6-5. Timing of timer interrupt operation cr20 inttm20 to20 tof20 n n n n n t 0000h n ffffh n 0000h 0001h 0001h count clock tm20 count value interrupt acknowledgement interrupt acknowledgement overflow flag set remark n = 0000h to ffffh.

  • Page 115

    Chapter 6 16-bit timer 20 user’s manual u15331ej4v1ud 115 6.4.2 operation as timer output 16-bit timer 20 can invert the timer output repeatedly each time the free-running counter value reaches the value set to cr20. Since this counter is not cleared and holds the count even after the timer output i...

  • Page 116

    Chapter 6 16-bit timer 20 116 user’s manual u15331ej4v1ud 6.4.3 capture operation the capture operation consists of latching the count value of 16-bit timer counter 20 (tm20) into a capture register in synchronization with a capture trigger, and retaining the count value. Set tmc20 as shown in figur...

  • Page 117

    Chapter 6 16-bit timer 20 user’s manual u15331ej4v1ud 117 6.4.4 16-bit timer counter 20 readout the count value of 16-bit timer counter 20 (tm20) is read out using a 16-bit manipulation instruction. Tm20 readout is performed via the counter read buffer. The counter read buffer latches the tm20 count...

  • Page 118

    Chapter 6 16-bit timer 20 118 user’s manual u15331ej4v1ud 6.5 cautions on using 16-bit timer 20 6.5.1 restrictions when rewriting 16-bit compare register 20 (1) disable interrupts (tmmk20 = 1) and inversion control of timer output (toc20 = 0) before rewriting the compare register (cr20). If the valu...

  • Page 119

    Chapter 6 16-bit timer 20 user’s manual u15331ej4v1ud 119 when rewriting using 16-bit access disable interrupts (tmmk20 = 1) and inversion control of timer output (toc20 = 0). Rewrite cr20 (16 bits). Wait for one cycle or more of the count clock. Clear the interrupt request flag (tmif20). Enable tim...

  • Page 120

    120 user’s manual u15331ej4v1ud chapter 7 8-bit timers 50, 60, and 61 7.1 functions of 8-bit timers 50, 60, and 61 one 8-bit timer channel (timer 50) and two 8-bit timer/event counter channels (timer 60 and 61) are incorporated in the µ pd789489 subseries. The operation modes listed in the following...

  • Page 121

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 121 (5) ppg output mode (ppg: programmable pulse generator) pulses are output using any cycle or duty ratio (pulse width) set (both the cycle and pulse width are programmable). (6) 24-bit event counter mode operation as an external ev...

  • Page 122

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 122 7.2 configuration of 8-bit timers 50, 60, and 61 8-bit timers 50, 60, and 61 include the following hardware. Table 7-2. Configuration of 8-bit timers 50, 60, and 61 item configuration timer counter 8 bits × 3 (tm50, tm60, tm61) re...

  • Page 123

    Cha pter 7 8-bit timers 50, 60, a nd 61 user’s manual u15331ej4v1ud 123 figure 7-2. Block diagram of timer 50 teg50 tcl500 tcl501 8-bit timer mode control register 50 (tmc50) decoder selector selector 8-bit compare register 50 (cr50) 8-bit timer counter 50 (tm50) selector count operation start signa...

  • Page 124

    Cha pter 7 8-bit timers 50, 60, a nd 61 user’s manual u15331ej4v1ud 124 tce60 tcl602 tcl601 tcl600 tmd601 tmd600 toe600 8-bit timer mode control register 60 (tmc60) carrier generator output control register 60 (tca60) decoder 8-bit timer counter 60 (tm60) f/f tm50 match signal (in cascade connection...

  • Page 125

    Cha pter 7 8-bit timers 50, 60, a nd 61 user’s manual u15331ej4v1ud 125 tce61 tcl612 tcl611 tcl610 tmd611 tmd610 toe610 8-bit timer mode control register 61 (tmc61) decoder 8-bit timer counter 61 (tm61) f/f clear 8-bit compare register 61 (cr61) selector inttm61 match to61/tmi61 /intp2/p32 reset ppg...

  • Page 126

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 126 figure 7-5. Block diagram of output controller (timer 60) f/f rmc60 nrz60 toe60 pm31 p31 output latch selector to60/intp1/p31 carrier generator mode carrier clock (1) 8-bit compare register 50 (cr50) this 8-bit register is used to...

  • Page 127

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 127 (4) 8-bit h width compare registers 60 and 61 (crh60, crh61) in carrier generator mode and ppg output mode, the high-level width of timer output is set by writing a value to crh6n. This 8-bit register is used to continually compar...

  • Page 128

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 128 7.3 control registers for 8-bit timers 50, 60, and 61 8-bit timers 50, 60, and 61 are controlled by the following six registers. • 8-bit timer mode control register 50 (tmc50) • 8-bit timer mode control register 60 (tmc60) • carri...

  • Page 129

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 129 figure 7-6. Format of 8-bit timer mode control register 50 (2/2) symbol 5 4 3 2 1 address after reset r/w tmc50 tce50 teg50 tcl502 tcl501 tcl500 tmd501 tmd500 toe50 ff4dh 00h r/w toe50 control of timer output note 4 0 output disab...

  • Page 130

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 130 figure 7-7. Format of 8-bit timer mode control register 60 symbol 6 5 4 3 2 1 address after reset r/w tmc60 tce60 0 tcl602 tcl601 tcl600 tmd601 tmd600 toe600 ff4eh 00h r/w tce60 control of tm60 count operation note 1 0 clear tm60 ...

  • Page 131

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 131 (3) carrier generator output control register 60 (tca60) this register is used to set the timer output data in carrier generator mode. Tca60 is set with a 1-bit or 8-bit memory manipulation instruction. Reset input sets this regis...

  • Page 132

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 132 (4) 8-bit timer mode control register 61 (tmc61) 8-bit timer mode control register 61 (tmc61) is used to control the timer 61 count clock setting and the operation mode setting. Tmc61 is set with a 1-bit or 8-bit memory manipulati...

  • Page 133

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 133 (5) port mode register 3 (pm3) this register is used to set the i/o mode of port 3 in 1-bit units. When using the p30/intp0/to50/tmi60 pin as a timer output (to50), set pm30 and the p30 output latch to 0. When used as a timer inpu...

  • Page 134

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 134 7.4 operation of 8-bit timers 50, 60, and 61 7.4.1 operation as 8-bit timer counter timer 50, timer 60, and timer 61 can be independently used as 8-bit timer counters. The following modes can be used for the 8-bit timer counter. •...

  • Page 135

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 135 table 7-3. Interval time of timer 50 tcl502 tcl501 tcl500 minimum interval time maximum interval time resolution 0 0 0 1/f x (0.2 µ s) 2 8 /f x (51.2 µ s) 1/f x (0.2 µ s) 0 0 1 2 3 /f x (1.6 µ s) 2 11 /f x (409.6 µ s) 2 3 /f x (1....

  • Page 136

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 136 figure 7-11. Timing of interval timer operation with 8-bit resolution (basic operation) count stop count clock crnm tcenm inttmnm tonm n t tmnm n 00h 01h n 00h 01h n 00h 00h 01h 00h 01h clear clear clear count start interrupt ackn...

  • Page 137

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 137 figure 7-13. Timing of interval timer operation with 8-bit resolution (when crnm is set to ffh) count clock crnm tcenm inttmnm tonm ffh tmnm ffh 00h 01h 00h 01h 00h ffh 00h 01h ffh ffh 00h clear clear clear count start remark nm =...

  • Page 138

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 138 figure 7-15. Timing of interval timer operation with 8-bit resolution (when crnm changes from n to m (n > m)) count clock crnm tcenm inttmnm tonm tmnm 00h 00h 00h n − 1 n m n m n m 00h ffh m h clear clear clear tmnm overflows beca...

  • Page 139

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 139 figure 7-16. Timing of interval timer operation with 8-bit resolution (when timer 60 match signal is selected for timer 50 count clock) timer 60 count clock cr60 tce60 inttm60 to60 tm60 n 00h m 00h 00h 01h m n m 00h m 00h 00h 01h ...

  • Page 140

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 140 (2) operation as external event counter with 8-bit resolution (timer 60 and timer 61 only) the external event counter counts the number of external clock pulses input to the tmi6m pin by using 8-bit timer counter 6m (tm6m). To ope...

  • Page 141

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 141 (3) operation as square-wave output with 8-bit resolution square waves of any frequency can be output at an interval specified by the value preset in 8-bit compare register nm (crnm). To operate timer nm for square-wave output, se...

  • Page 142

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 142 table 7-7. Square-wave output range of timer 60 tcl602 tcl601 tcl600 minimum pulse width maximum pulse width resolution 0 0 0 1/f x (0.2 µ s) 2 8 /f x (51.2 µ s) 1/f x (0.2 µ s) 0 0 1 2 2 /f x (0.8 µ s) 2 10 /f x (204 µ s) 2 2 /f ...

  • Page 143

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 143 7.4.2 operation as 16-bit timer counter timer 50 and timer 60 can be used as a 16-bit timer counter using cascade connection. In this case, 8-bit timer counter 50 (tm50) is the higher 8 bits and 8-bit timer counter 60 (tm60) is th...

  • Page 144

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 144 table 7-9. Interval time with 16-bit resolution tcl602 tcl601 tcl600 minimum interval time maximum interval time resolution 0 0 0 1/f x (0.2 µ s) 2 16 /f x (13.1 ms) 1/f x (0.2 µ s) 0 0 1 2 2 /f x (0.8 µ s) 2 18 /f x (52.4 ms) 2 2...

  • Page 145

    Cha pter 7 8-bit timers 50, 60, a nd 61 user’s manual u15331ej4v1ud 145 interval time count clock tm60 count value cr60 tce60 inttm60 to60 ffh 00h 7fh 00h n 00h n n n n 80h 7fh 80h ffh 00h n 00h n n n tm50 count pulse tm50 00h x x − 1 01h cr50 x x x 7fh 80h ffh 00h n 00h n n n x x − 1 00h t not clea...

  • Page 146

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 146 (2) operation as external event counter with 16-bit resolution the external event counter counts the number of external clock pulses input to the tmi60 pin by tm50 and tm60. To operate as an external event counter with 16-bit reso...

  • Page 147

    Cha pter 7 8-bit timers 50, 60, a nd 61 user’s manual u15331ej4v1ud 147 tmi60 pin input tm60 count value cr60 tce60 inttm60 ffh 00h 7fh 00h n 00h n n n n 80h 7fh 80h ffh 00h n 00h n n n tm50 count pulse tm50 00h x 01h cr50 x x x 7fh 80h ffh 00h n 00h n n n x x − 1 00h x − 1 not cleared because tm50 ...

  • Page 148

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 148 (3) operation as square-wave output with 16-bit resolution square waves of any frequency can be output at an interval specified by the count value preset in cr50 and cr60. To operate as a square-wave output with 16-bit resolution,...

  • Page 149

    Cha pter 7 8-bit timers 50, 60, a nd 61 user’s manual u15331ej4v1ud 149 count clock tm60 count value cr60 tce60 inttm60 to60 note ffh 00h 7fh 00h n 00h n n n n 80h 7fh 80h ffh 00h n 00h n n n tm50 count pulse tm50 00h x x − 1 01h cr50 x x x 7fh 80h ffh 00h n 00h n n n x x − 1 00h not cleared because...

  • Page 150

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 150 7.4.3 operation as carrier generator an arbitrary carrier clock generated by tm60 can be output in the cycle set in tm50. To operate timer 50 and timer 60 as carrier generators, settings must be made in the following sequence. Dis...

  • Page 151

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 151 figure 7-22. Timing of carrier generator operation (when cr60 = n, crh60 = m (m > n)) tm60 count clock tm60 count value cr60 tce60 inttm60 m 00h n 00h 01h n crh60 m n 00h carrier clock n 00h 00h n m 00h 01h l l 00h 01h l 00h 01h l...

  • Page 152

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 152 figure 7-23. Timing of carrier generator operation (when cr60 = n, crh60 = m (m n)) tm60 count clock tm60 count value cr60 tce60 inttm60 n 00h n l crh60 m carrier clock n 00h 00h 01h l 00h 01h l 00h 01h l 00h l 00h 01h tm50 count ...

  • Page 153

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 153 figure 7-24. Timing of carrier generator operation (when cr60 = crh60 = n) tm60 count clock tm60 count value cr60 tce60 inttm60 n 00h 00h 00h n crh60 n n carrier clock 00h 00h n n 00h 01h l 00h 01h l 00h 01h l 00h l 00h 01h tm50 c...

  • Page 154

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 154 7.4.4 pwm output mode operation (timer 50) in the pwm output mode, to50 becomes high level when tm50 overflows, and to50 becomes low level when cr50 and tm50 match. It is thus possible to output a pulse with any duty ratio (free-r...

  • Page 155

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 155 figure 7-26. Operation timing when overwriting cr50 (when rising edge is selected) (1) when setting cr50 > tm50 after overflow count clock cr50 tce50 inttm50 to50 n tm50 n 00h 00h 00h 01h ffh m ffh 01h m overflow overflow overflow...

  • Page 156

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 156 figure 7-27. Operation timing in pwm output mode (when both edges are selected) (1) cr50 = even number count clock cr50 tce50 inttm50 to50 2n tm50 2n 00h 00h 01h ffh ffh 2n 02h feh 01h 02h feh overflow overflow count start (2) whe...

  • Page 157

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 157 figure 7-28. Operation timing in pwm output mode (when both edges are selected) (when cr50 is overwritten) count clock cr50 tce50 inttm50 to50 2n + 1 tm50 2n 00h 00h 00h 01h ffh ffh 01h 2n + 1 01h 02h feh 2n overflow overflow over...

  • Page 158

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 158 7.4.5 ppg output mode operation (timer 60 and timer 61) in the ppg output mode, a pulse of any duty ratio can be output by setting a low-level width using cr6m and a high-level width using crh6m. To operate timer 6m in ppg output ...

  • Page 159

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 159 figure 7-29. Ppg output mode timing (basic operation) count clock tm6m count value cr6m tce6m inttm6m 00h n 00h 01h n crh6m m n to6m note 00h 00h 01h m 01h 01h m 00h clear clear clear clear count start note the initial value of to...

  • Page 160

    Chapter 7 8-bit timers 50, 60, and 61 user’s manual u15331ej4v1ud 160 7.5 cautions on using 8-bit timers 50, 60, and 61 (1) error on starting timer an error of up to 1.5 clocks is included in the time between the timer being started and a match signal being generated. This is because the rising edge...

  • Page 161

    User’s manual u15331ej4v1ud 161 chapter 8 watch timer 8.1 watch timer functions the watch timer has the following functions. • watch timer • interval timer the watch and interval timers can be used at the same time. Figure 8-1 shows a block diagram of the watch timer. Figure 8-1. Block diagram of wa...

  • Page 162

    Chapter 8 watch timer 162 user’s manual u15331ej4v1ud (1) watch timer an interrupt request (intwt) occurs at an interval of 0.5 second when using either the 4.19 mhz main system clock or the 32.768 khz subsystem clock. Also, an interrupt request (intwt) occurs at an interval of 1.0 seconds when usin...

  • Page 163

    Chapter 8 watch timer user’s manual u15331ej4v1ud 163 8.3 control registers for watch timer the watch timer is controlled by the following registers. • watch timer mode control register (wtm) • watch timer interrupt time selection register (wtim) (1) watch timer mode control register (wtm) this regi...

  • Page 164

    Chapter 8 watch timer 164 user’s manual u15331ej4v1ud (2) watch timer interrupt time selection register (wtim) this register is used to set the interrupt time by selecting either the source clock or the clock divided by 2 for the subsystem clock to be input to watch timer. Wtim is set with a 1-bit o...

  • Page 165

    Chapter 8 watch timer user’s manual u15331ej4v1ud 165 8.4 watch timer operation 8.4.1 operation as watch timer the main system clock (4.19 mhz) or subsystem clock (32.768 khz) is used to enable the watch timer to operate at 0.5-second intervals. Also, an interrupt request (intwt) occurs at an interv...

  • Page 166

    Chapter 8 watch timer 166 user’s manual u15331ej4v1ud figure 8-4. Watch timer/interval timer operation timing 0h start overflow overflow 5-bit counter count clock f w /2 9 watch timer interrupt intwt interval timer interrupt intwti watch timer interrupt time (0.5 s) watch timer interrupt time (0.5 s...

  • Page 167

    User’s manual u15331ej4v1ud 167 chapter 9 watchdog timer 9.1 watchdog timer functions the watchdog timer has the following functions. • watchdog timer • interval timer caution select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (wdtm). (1) watchdog timer t...

  • Page 168

    Chapter 9 watchdog timer 168 user’s manual u15331ej4v1ud 9.2 watchdog timer configuration the watchdog timer includes the following hardware. Table 9-3. Configuration of watchdog timer item configuration control registers watchdog timer clock selection register (wdcs) watchdog timer mode register (w...

  • Page 169

    Chapter 9 watchdog timer user’s manual u15331ej4v1ud 169 9.3 watchdog timer control registers the watchdog timer is controlled by the following two registers. • watchdog timer clock selection register (wdcs) • watchdog timer mode register (wdtm) (1) watchdog timer clock selection register (wdcs) thi...

  • Page 170

    Chapter 9 watchdog timer 170 user’s manual u15331ej4v1ud (2) watchdog timer mode register (wdtm) this register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. Wdtm is set with a 1-bit or 8-bit memory manipulation instruction. Reset input sets wdtm ...

  • Page 171

    Chapter 9 watchdog timer user’s manual u15331ej4v1ud 171 9.4 watchdog timer operation 9.4.1 operation as watchdog timer the watchdog timer detects a program loop when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1. The count clock (program loop detection time interval) of the w...

  • Page 172

    Chapter 9 watchdog timer 172 user’s manual u15331ej4v1ud 9.4.2 operation as interval timer when bits 4 and 3 (wdtm4, wdtm3) of the watchdog timer mode register (wdtm) are set to 0 and 1, respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at interval...

  • Page 173

    User’s manual u15331ej4v1ud 173 chapter 10 10-bit a/d converter 10.1 10-bit a/d converter functions the 10-bit a/d converter is a 10-bit resolution converter used to convert analog inputs into digital signals. This converter can control eight channels (ani0 to ani7) of analog inputs. A/d conversion ...

  • Page 174

    Chapter 10 10-bit a/d converter 174 user’s manual u15331ej4v1ud figure 10-1. Block diagram of 10-bit a/d converter ani3/p63 sample & hold circuit voltage comparator successive approximation register (sar) controller a/d conversion result register 0 (adcrl0) av ss intad0 a/d converter mode register 0...

  • Page 175

    Chapter 10 10-bit a/d converter user’s manual u15331ej4v1ud 175 (3) sample & hold circuit the sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends them to the voltage comparator. The sampled analog input voltage is held during a/d conversion. (4) volt...

  • Page 176

    Chapter 10 10-bit a/d converter 176 user’s manual u15331ej4v1ud 10.3 10-bit a/d converter control registers the 10-bit a/d converter is controlled by the following two registers. • a/d converter mode register 0 (adml0) • analog input channel specification register 0 (ads0) (1) a/d converter mode reg...

  • Page 177

    Chapter 10 10-bit a/d converter user’s manual u15331ej4v1ud 177 cautions 1. Start conversion (adcs0 = 1) after 14 µ s have elapsed following the setting of adce0. If adce0 is not used, the conversion result immediately after the setting of bit 7 (adcs0) is undefined. 2. The conversion result may be ...

  • Page 178

    Chapter 10 10-bit a/d converter 178 user’s manual u15331ej4v1ud 10.4 10-bit a/d converter operation 10.4.1 basic operation of 10-bit a/d converter bit 0 of a/d converter mode register 0 (adml0) is set (adce0 = 1). Select a channel for a/d conversion, using analog input channel specification register...

  • Page 179

    Chapter 10 10-bit a/d converter user’s manual u15331ej4v1ud 179 figure 10-4. Basic operation of 10-bit a/d converter conversion time sampling time sampling a/d conversion undefined conversion result conversion result a/d converter operation sar adcrl0 intad0 a/d conversion continues until bit 7 (adc...

  • Page 180

    Chapter 10 10-bit a/d converter 180 user’s manual u15331ej4v1ud figure 10-5. Relationship between analog input voltage and a/d conversion result 1,023 1,022 1,021 3 2 1 0 a/d conversion result (adcrl0) 1 2,048 1 1,024 3 2,048 2 1,024 5 2,048 3 1,024 2,043 2,048 1,022 1,024 2,045 2,048 1,023 1,024 2,...

  • Page 181

    Chapter 10 10-bit a/d converter user’s manual u15331ej4v1ud 181 10.4.3 operation mode of 10-bit a/d converter the a/d converter is initially in select mode. In this mode, analog input channel specification register 0 (ads0) is used to select an analog input channel from ani0 to ani7 for a/d conversi...

  • Page 182

    Chapter 10 10-bit a/d converter 182 user’s manual u15331ej4v1ud 10.5 cautions related to 10-bit a/d converter (1) current consumption in standby mode in standby mode, the a/d converter stops operation. Clearing bit 7 (adcs0) and bit 0 (adce0) of a/d converter mode register 0 (adml0) to 0 can reduce ...

  • Page 183

    Chapter 10 10-bit a/d converter user’s manual u15331ej4v1ud 183 (5) timing of undefined a/d conversion result the a/d conversion value may become undefined if the timing of the completion of a/d conversion and the timing to stop the a/d conversion operation conflict. Therefore, read the a/d conversi...

  • Page 184

    Chapter 10 10-bit a/d converter 184 user’s manual u15331ej4v1ud (6) noise prevention to maintain a resolution of 10 bits, watch for noise at the av dd and ani0 to ani7 pins. The higher the output impedance of the analog input source, the larger the effect by noise. To reduce noise, attach an externa...

  • Page 185

    Chapter 10 10-bit a/d converter user’s manual u15331ej4v1ud 185 (9) interrupt request flag (adif0) changing the contents of a/d converter mode register 0 (adml0) does not clear the interrupt request flag (adif0). If the analog input pins are changed during a/d conversion, therefore, the a/d conversi...

  • Page 186

    186 user’s manual u15331ej4v1ud chapter 11 serial interface 20 11.1 serial interface 20 functions serial interface 20 has the following three modes. • operation stop mode • asynchronous serial interface (uart) mode • 3-wire serial i/o mode (1) operation stop mode this mode is used when serial transf...

  • Page 187

    Cha pter 11 seria l interfa c e 20 user’s manual u15331ej4v1ud 187 internal bus receive buffer register 20 (rxb20) switch of the first bit asynchronous serial interface status register 20 (asis20) serial operation mode register 20 (csim20) receive shift register 20 (rxs20) csie20 dir20 csck20 pe20 f...

  • Page 188

    Cha pter 11 seria l interfa c e 20 188 user’s manual u15331ej4v1ud clock for receive detection transmit shift clock receive shift clock receive detection txe20 rxe20 csie20 1/2 1/2 transmit clock counter (3 bits) receive clock counter (3 bits) 4 f x /2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f ...

  • Page 189

    Chapter 11 serial interface 20 user’s manual u15331ej4v1ud 189 (1) transmit shift register 20 (txs20) txs20 is a register in which transmit data is prepared. The transmit data is output from txs20 bit-serially. When the data length is seven bits, bits 0 to 6 of the data in txs20 will be transmit dat...

  • Page 190

    Chapter 11 serial interface 20 190 user’s manual u15331ej4v1ud 11.3 serial interface 20 control registers serial interface 20 is controlled by the following six registers. • serial operation mode register 20 (csim20) • asynchronous serial interface mode register 20 (asim20) • asynchronous serial int...

  • Page 191

    Chapter 11 serial interface 20 user’s manual u15331ej4v1ud 191 (2) asynchronous serial interface mode register 20 (asim20) asim20 is used to make the settings related to asynchronous serial interface mode. Asim20 is set with a 1-bit or 8-bit memory manipulation instruction. Reset input sets asim20 t...

  • Page 192

    Chapter 11 serial interface 20 192 user’s manual u15331ej4v1ud table 11-2. Serial interface 20 operation mode settings (1) operation stop mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 pm22 p22 pm21 p21 pm20 p20 first bit shift clock p22/si20/ rxd20 pin function p21/so20/ txd20 pin function p20/...

  • Page 193

    Chapter 11 serial interface 20 user’s manual u15331ej4v1ud 193 (3) asynchronous serial interface status register 20 (asis20) asis20 indicates the type of a reception error, if it occurs while asynchronous serial interface mode is set. Asis20 is set with a 1-bit or 8-bit memory manipulation instructi...

  • Page 194

    Chapter 11 serial interface 20 194 user’s manual u15331ej4v1ud (4) baud rate generator control register 20 (brgc20) brgc20 is used to specify the serial clock for serial interface 20. Brgc20 is set with an 8-bit memory manipulation instruction. Reset input sets brgc20 to 00h. Figure 11-6. Format of ...

  • Page 195

    Chapter 11 serial interface 20 user’s manual u15331ej4v1ud 195 the baud rate transmit/receive clock to be generated is either a divided system clock signal, or a signal obtained by dividing the clock input to the asck20 pin. (a) generation of uart baud rate transmit/receive clock form system clock t...

  • Page 196

    Chapter 11 serial interface 20 196 user’s manual u15331ej4v1ud (b) generation of uart baud rate transmit/receive clock from external clock input to asck20 pin the transmit/receive clock is generated by dividing the clock input from the asck20 pin. The baud rate of a clock generated from the clock in...

  • Page 197

    Chapter 11 serial interface 20 user’s manual u15331ej4v1ud 197 11.4 serial interface 20 operation serial interface 20 provides the following three modes. • operation stop mode • asynchronous serial interface (uart) mode • 3-wire serial i/o mode 11.4.1 operation stop mode in operation stop mode, seri...

  • Page 198

    Chapter 11 serial interface 20 198 user’s manual u15331ej4v1ud (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. Reset input sets asim20 to 00h. Txe20 0 1 transmit operation control transmit operation stopped transmit ope...

  • Page 199

    Chapter 11 serial interface 20 user’s manual u15331ej4v1ud 199 11.4.2 asynchronous serial interface (uart) mode in this mode, the one-byte data following the start bit is transmitted/received, enabling full-duplex communication. This device incorporates a uart-dedicated baud rate generator that enab...

  • Page 200

    Chapter 11 serial interface 20 200 user’s manual u15331ej4v1ud (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. Reset input sets asim20 to 00h. Txe20 0 1 transmit operation control transmit operation stopped transmit ope...

  • Page 201

    Chapter 11 serial interface 20 user’s manual u15331ej4v1ud 201 (c) asynchronous serial interface status register 20 (asis20) asis20 is set with a 1-bit or 8-bit memory manipulation instruction. Reset input sets asis20 to 00h. Pe20 0 1 parity error flag no parity error occurred a parity error occurre...

  • Page 202

    Chapter 11 serial interface 20 202 user’s manual u15331ej4v1ud (d) baud rate generator control register 20 (brgc20) brgc20 is set with an 8-bit memory manipulation instruction. Reset input sets brgc20 to 00h. Tps203 0 0 0 0 0 0 0 0 1 tps202 0 0 0 0 1 1 1 1 0 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 ...

  • Page 203

    Chapter 11 serial interface 20 user’s manual u15331ej4v1ud 203 table 11-5. Example of relationship between system clock and baud rate error (%) baud rate (bps) n brgc20 set value f x = 5.0 mhz f x = 4.9152 mhz 1,200 8 70h 2,400 7 60h 4,800 6 50h 9,600 5 40h 19,200 4 30h 38,400 3 20h 76,800 2 10h 1.7...

  • Page 204

    Chapter 11 serial interface 20 204 user’s manual u15331ej4v1ud (2) communication operation (a) data format the transmit/receive data format is as shown in figure 11-7. One data frame consists of a start bit, character bits, parity bit, and stop bit(s). The specification of character bit length in on...

  • Page 205

    Chapter 11 serial interface 20 user’s manual u15331ej4v1ud 205 (b) parity types and operation the parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-...

  • Page 206

    Chapter 11 serial interface 20 206 user’s manual u15331ej4v1ud (c) transmission a transmit operation is started by writing transmit data to transmit shift register 20 (txs20). The start bit, parity bit, and stop bit(s) are added automatically. When the transmit operation starts, the data in txs20 is...

  • Page 207

    Chapter 11 serial interface 20 user’s manual u15331ej4v1ud 207 (d) reception when bit 6 (rxe20) of asynchronous serial interface mode register 20 (asim20) is set (1), a receive operation is enabled and sampling of the rxd20 pin input is performed. Rxd20 pin input sampling is performed using the seri...

  • Page 208

    Chapter 11 serial interface 20 208 user’s manual u15331ej4v1ud (e) receive errors the following three errors may occur during a receive operation: a parity error, framing error, and overrun error. After data reception, an error flag is set in asynchronous serial interface status register 20 (asis20)...

  • Page 209

    Chapter 11 serial interface 20 user’s manual u15331ej4v1ud 209 (f) reading receive data when the reception completion interrupt (intsr20) occurs, receive data can be read by reading the value of receive buffer register 20 (rxb20). To read the receive data stored in receive buffer register 20 (rxb20)...

  • Page 210

    Chapter 11 serial interface 20 210 user’s manual u15331ej4v1ud (3) cautions related to uart mode (a) when bit 7 (txe20) of asynchronous serial interface mode register 20 (asim20) is cleared during transmission, be sure to set transmit shift register 20 (txs20) to ffh, then set txe20 to 1 before exec...

  • Page 211

    Chapter 11 serial interface 20 user’s manual u15331ej4v1ud 211 11.4.3 3-wire serial i/o mode the 3-wire serial i/o mode is useful for connection of peripheral i/os and display controllers, etc., which incorporate a conventional clocked serial interface, such as the 75xl series, 78k series, and 17k s...

  • Page 212

    Chapter 11 serial interface 20 212 user’s manual u15331ej4v1ud (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. Reset input sets asim20 to 00h. When 3-wire serial i/o mode is selected, asim20 must be set to 00h. Txe20 0 ...

  • Page 213

    Chapter 11 serial interface 20 user’s manual u15331ej4v1ud 213 (c) baud rate generator control register 20 (brgc20) brgc20 is set with an 8-bit memory manipulation instruction. Reset input sets brgc20 to 00h. Tps203 0 0 0 0 0 0 0 0 tps202 0 0 0 0 1 1 1 1 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f ...

  • Page 214

    Chapter 11 serial interface 20 214 user’s manual u15331ej4v1ud (2) communication operation in 3-wire serial i/o mode, data transmission/reception is performed in 8-bit units. Data is transmitted/ received bit by bit in synchronization with the serial clock. Transmit shift register 20 (txs20/sio20) a...

  • Page 215

    Chapter 11 serial interface 20 user’s manual u15331ej4v1ud 215 figure 11-11. 3-wire serial i/o mode timing (2/2) (ii) slave operation timing (csck20=1) 1 2 3 4 5 6 7 8 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck20 si20 note so20 sio20 write intcsi20 note the value of the last...

  • Page 216

    216 user’s manual u15331ej4v1ud chapter 12 serial interface 1a0 12.1 function of serial interface 1a0 serial interface 1a0 has the following three modes. • operation stop mode • 3-wire serial i/o mode • 3-wire serial i/o mode with automatic transmit/receive function (1) operation stop mode this mode...

  • Page 217

    Chapter 12 serial interface 1a0 user’s manual u15331ej4v1ud 217 12.2 configuration of serial interface 1a0 serial interface 1a0 includes the following hardware. Table 12-1. Configuration of serial interface 1a0 item configuration registers serial i/o shift register 1a0 (sio1a0) automatic data transm...

  • Page 218

    Chapter 12 serial interface 1a0 218 user’s manual u15331ej4v1ud (1) serial i/o shift register 1a0 (sio1a0) this is an 8-bit register used to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. Sio1a0 is set w...

  • Page 219

    Chapter 12 serial interface 1a0 user’s manual u15331ej4v1ud 219 12.3 control registers for serial interface 1a0 serial interface 1a0 is controlled by the following five registers. • serial operation mode register 1a0 (csim1a0) • automatic data transmit/receive control register 0 (adtc0) • automatic ...

  • Page 220

    Chapter 12 serial interface 1a0 220 user’s manual u15331ej4v1ud figure 12-2. Format of serial operation mode register 1a0 symbol 6 3 2 1 0 address after reset r/w csim1a0 csie10 dir10 ate0 lsck10 0 0 scl101 scl100 ff78h 00h r/w specification of operation enable/disable csie10 shift register operatio...

  • Page 221

    Chapter 12 serial interface 1a0 user’s manual u15331ej4v1ud 221 (2) automatic data transmit/receive control register 0 (adtc0) this register sets automatic reception enable/disable, the operation mode, and displays the state of automatic transmit/receive control. Adtc0 is set via a 1-bit or 8-bit me...

  • Page 222

    Chapter 12 serial interface 1a0 222 user’s manual u15331ej4v1ud (3) automatic data transmit/receive interval specification register 0 (adti0) this register sets the automatic data transmit/receive function data transfer interval. Adti0 is set via a 1-bit or 8-bit memory manipulation instruction. Res...

  • Page 223

    Chapter 12 serial interface 1a0 user’s manual u15331ej4v1ud 223 figure 12-4. Format of automatic data transmit/receive interval specification register 0 (2/2) symbol 6 5 address after reset r/w adti0 adti07 0 0 adti04 adti03 adti02 adti01 adti00 ff7bh 00h r/w adti04 adti03 adti02 adti01 adti00 data ...

  • Page 224

    Chapter 12 serial interface 1a0 224 user’s manual u15331ej4v1ud 12.4 serial interface 1a0 operation serial interface 1a0 provides the following three modes. • operation stop mode • 3-wire serial i/o mode • 3-wire serial i/o mode with automatic transmit/receive function 12.4.1 operation stop mode in ...

  • Page 225

    Chapter 12 serial interface 1a0 user’s manual u15331ej4v1ud 225 12.4.2 3-wire serial i/o mode the 3-wire serial i/o mode is useful for connection of peripheral i/os and display controllers, etc., which incorporate a conventional clocked serial interface, such as the 75xl series, 78k series, and 17k ...

  • Page 226

    Chapter 12 serial interface 1a0 226 user’s manual u15331ej4v1ud symbol 6 3 2 1 0 address after reset r/w csim1a0 csie10 dir10 ate0 lsck10 0 0 scl101 scl100 ff78h 00h r/w specification of operation enable/disable csie10 shift register operation serial counter port note 0 operation stopped cleared por...

  • Page 227

    Chapter 12 serial interface 1a0 user’s manual u15331ej4v1ud 227 (2) communication operation in 3-wire serial i/o mode, data transmission/reception is performed in 8-bit units. Data is transmitted/received bit by bit in synchronization with the serial clock. Serial i/o shift register 1a0 (sio1a0) shi...

  • Page 228

    Chapter 12 serial interface 1a0 228 user’s manual u15331ej4v1ud figure 12-5. 3-wire serial i/o mode timing (2/2) (ii) slave operation timing 1 2 3 4 5 6 7 8 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck10 si10 note so10 sio1a0 write intcsi10 note the value of the last bit previ...

  • Page 229

    Chapter 12 serial interface 1a0 user’s manual u15331ej4v1ud 229 (3) msb/lsb switching as the start bit in the 3-wire serial i/o mode, transfer can be selected to start from the msb or lsb. Figure 12-6 shows the configuration of serial i/o shift register 1a0 (sio1a0) and the internal bus. As shown in...

  • Page 230

    Chapter 12 serial interface 1a0 230 user’s manual u15331ej4v1ud 12.4.3 3-wire serial i/o mode with automatic transmit/receive function this 3-wire serial i/o mode is used for transmission/reception of a maximum of 16-byte data without the use of software. Once transfer is started, the set number of ...

  • Page 231

    Chapter 12 serial interface 1a0 user’s manual u15331ej4v1ud 231 symbol 6 3 2 1 0 address after reset r/w csim1a0 csie10 dir10 ate0 lsck10 0 0 scl101 scl100 ff78h 00h r/w specification of operation enable/disable csie10 shift register operation serial counter port note 0 operation stopped cleared por...

  • Page 232

    Chapter 12 serial interface 1a0 232 user’s manual u15331ej4v1ud (b) automatic data transmit/receive control register 0 (adtc0) adtc0 is set via a 1-bit or 8-bit memory manipulation instruction. Reset input sets this register to 00h. Symbol 5 4 2 1 0 address after reset r/w adtc0 re0 arld0 0 0 trf0 0...

  • Page 233

    Chapter 12 serial interface 1a0 user’s manual u15331ej4v1ud 233 (c) automatic data transmit/receive interval specification register 0 (adti0) adti0 is set via a 1-bit or 8-bit memory manipulation instruction. Reset input sets this register to 00h. Symbol 6 5 address after reset r/w adti0 adti07 0 0 ...

  • Page 234

    Chapter 12 serial interface 1a0 234 user’s manual u15331ej4v1ud symbol 6 5 address after reset r/w adti0 adti07 0 0 adti04 adti03 adti02 adti01 adti00 ff7bh 00h r/w adti04 adti03 adti02 adti01 adti00 data transfer interval specification (f x = 5.0 mhz, f sck = 1.25 mhz) note 2 n 1 0 0 0 0 13.6 µ s +...

  • Page 235

    Chapter 12 serial interface 1a0 user’s manual u15331ej4v1ud 235 (2) automatic transmit/receive data setting (a) transmit data setting write transmit data from the least significant address ffa0h of buffer ram (up to ffafh). The transmit data should be in the order from higher address to lower addres...

  • Page 236

    Chapter 12 serial interface 1a0 236 user’s manual u15331ej4v1ud (3) communication operation (a) basic transmit/receive mode this transmit/receive mode is the same as the 3-wire serial i/o mode in which the specified number of data are transmitted/received in 8-bit units. Serial transfer is started w...

  • Page 237

    Chapter 12 serial interface 1a0 user’s manual u15331ej4v1ud 237 figure 12-8. Basic transmit/receive mode flowchart remark adtp0: automatic data transmit/receive address pointer 0 adti0: automatic data transmit/receive interval specification register 0 sio1a0: serial i/o shift register 1a0 trf0: bit ...

  • Page 238

    Chapter 12 serial interface 1a0 238 user’s manual u15331ej4v1ud in 6-byte transmission/reception (bit 6 (arld0) and bit 7 (re0) of automatic data transmit/receive control register 0 (adtc0) = 0, and 1, respectively) in basic transmit/receive mode, buffer ram operates as follows. (i) before transmiss...

  • Page 239

    Chapter 12 serial interface 1a0 user’s manual u15331ej4v1ud 239 figure 12-9. Buffer ram operation in 6-byte transmission/reception (in basic transmit/receive mode) (2/2) (b) 4th byte transmission/reception receive data 1 (r1) receive data 2 (r2) receive data 3 (r3) transmit data 4 (t4) transmit data...

  • Page 240

    Chapter 12 serial interface 1a0 240 user’s manual u15331ej4v1ud (b) basic transmit mode in this mode, the specified number of 8-bit unit data are transmitted. Serial transfer is started when any data is written to serial i/o shift register 1a0 (sio1a0) while bit 7 (csie10) of serial operation mode r...

  • Page 241

    Chapter 12 serial interface 1a0 user’s manual u15331ej4v1ud 241 figure 12-11. Basic transmit mode flowchart remark adtp0: automatic data transmit/receive address pointer 0 adti0: automatic data transmit/receive interval specification register 0 sio1a0: serial i/o shift register 1a0 trf0: bit 3 of au...

  • Page 242

    Chapter 12 serial interface 1a0 242 user’s manual u15331ej4v1ud in 6-byte transmission (bit 6 (arld0) and bit 7 (re0) of automatic data transmit/receive control register 0 (adtc0) are 0) in basic transmit mode, buffer ram operates as follows. (i) before transmission (refer to figure 12-12 (a)) after...

  • Page 243

    Chapter 12 serial interface 1a0 user’s manual u15331ej4v1ud 243 figure 12-12. Buffer ram operation in 6-byte transmission (in basic transmit mode) (2/2) (b) 4th byte transmission point transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit d...

  • Page 244

    Chapter 12 serial interface 1a0 244 user’s manual u15331ej4v1ud (c) repeat transmit mode in this mode, data stored in the buffer ram is transmitted repeatedly. Serial transfer is started by writing any data to serial shift i/o register 1a0 (sio1a0) when bit 7 (csie10) of serial operation mode regist...

  • Page 245

    Chapter 12 serial interface 1a0 user’s manual u15331ej4v1ud 245 figure 12-14. Repeat transmit mode flowchart start write transmit data in buffer ram set adtp0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the transmission/reception operation interv...

  • Page 246

    Chapter 12 serial interface 1a0 246 user’s manual u15331ej4v1ud in 6-byte transmission (bit 6 (arld0) and bit 7 (re0) of automatic data transmit/receive control register 0 (adtc0) are 1 and 0, respectively) in repeat transmit mode, buffer ram operates as follows. (i) before transmission (refer to fi...

  • Page 247

    Chapter 12 serial interface 1a0 user’s manual u15331ej4v1ud 247 figure 12-15. Buffer ram operation in 6-byte transmission (in repeat transmit mode) (2/2) (c) upon completion of transmission of 6 bytes transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5...

  • Page 248

    Chapter 12 serial interface 1a0 248 user’s manual u15331ej4v1ud (d) automatic transmission/reception suspension and restart automatic transmission/reception can be temporarily suspended by setting bit 7 (csie10) of serial operation mode register 1a0 (csim1a0) to 0. During 8-bit data transfer, the tr...

  • Page 249

    Chapter 12 serial interface 1a0 user’s manual u15331ej4v1ud 249 (4) timing of interrupt request signal generation the interrupt request signal is generated in synchronization with the timing shown in table 12-2. Table 12-2. Timing of interrupt request signal generation operation mode timing of inter...

  • Page 250

    250 user’s manual u15331ej4v1ud chapter 13 lcd controller/driver 13.1 lcd controller/driver functions the functions of the lcd controller/driver of the µ pd789489 subseries are as follows. (1) automatic output of segment and common signals based on automatic display data memory read (2) two differen...

  • Page 251

    Chapter 13 lcd controller/driver user’s manual u15331ej4v1ud 251 the correspondence with the lcd display ram is shown in figure 13-1 below. Figure 13-1. Correspondence with lcd display ram address bit segment 7 6 5 4 3 2 1 0 fa1bh 0 0 0 0 → s27 note fa1ah 0 0 0 0 → s26 note fa19h 0 0 0 0 → s25 note ...

  • Page 252

    Cha pter 13 lcd controller/driver 252 user’s manual u15331ej4v1ud lcdc03 lcdc02 lcdc01 lcdc00 2 2 f lcd 2 6 f lcd 2 7 f lcd 2 8 f lcd 2 9 lcdon0 vaon0 v lc0 com0 com1 com2 com3 3 2 1 0 3 2 1 0 6 5 7 4 fa00h lcdon0 3 2 1 0 3 2 1 0 6 5 7 4 fa1bh lcdon0 s27 f x /2 5 f x /2 6 f x /2 7 f xt s0 f lcd 3 2 ...

  • Page 253

    Chapter 13 lcd controller/driver user’s manual u15331ej4v1ud 253 13.3 registers controlling lcd controller/driver the lcd controller/driver is controlled by the following three registers. • lcd display mode register 0 (lcdm0) • lcd clock control register 0 (lcdc0) • lcd voltage boost control registe...

  • Page 254

    Chapter 13 lcd controller/driver 254 user’s manual u15331ej4v1ud (1) lcd display mode register 0 (lcdm0) lcdm0 specifies whether to enable display. It also specifies whether to enable booster circuit operation, segment pin/common pin output, and the display mode. Lcdm0 is set with a 1-bit or 8-bit m...

  • Page 255

    Chapter 13 lcd controller/driver user’s manual u15331ej4v1ud 255 (2) lcd clock control register 0 (lcdc0) lcdc0 specifies the lcd source clock and lcd clock. The frame frequency is determined according to the lcd clock and number of time slices. Lcdc0 is set with a 1-bit or 8-bit memory manipulation...

  • Page 256

    Chapter 13 lcd controller/driver 256 user’s manual u15331ej4v1ud (3) lcd voltage boost control register 0 (lcdva0) lcdva0 controls the voltage boost level during the voltage boost operation. Lcdva0 is set with a 1-bit or 8-bit memory manipulation instruction. Reset input sets lcdva0 to 00h. Figure 1...

  • Page 257

    Chapter 13 lcd controller/driver user’s manual u15331ej4v1ud 257 13.4 setting lcd controller/driver set the lcd controller/driver using the following procedure. Set the lcd clock using lcd clock control register 0 (lcdc0). Set the voltage boost level using lcd voltage boost control register 0 (lcdva...

  • Page 258

    Chapter 13 lcd controller/driver 258 user’s manual u15331ej4v1ud 13.6 common and segment signals each pixel of the lcd panel turns on when the potential difference between the corresponding common and segment signals becomes higher than a specific voltage (lcd drive voltage, v lcd ). It turns off wh...

  • Page 259

    Chapter 13 lcd controller/driver user’s manual u15331ej4v1ud 259 figure 13-7. Common signal waveforms comn (three-time-slice mode) t f = 3 × t v lc0 v ss v lcd v lc1 v lc2 t f = 4 × t comn (four-time-slice mode) v lc0 v lcd v lc1 v lc2 v ss t: one lcd clock period t f : frame frequency figure 13-8. ...

  • Page 260

    Chapter 13 lcd controller/driver 260 user’s manual u15331ej4v1ud 13.7 display modes 13.7.1 three-time-slice display example figure 13-10 shows how a nine-digit lcd panel having the display pattern shown in figure 13-9 is connected to the segment signals (s0 to s26) and the common signals (com0 to co...

  • Page 261

    Chapter 13 lcd controller/driver user’s manual u15331ej4v1ud 261 figure 13-10. Example of connecting three-time-slice lcd panel ××××××××××××××××××××××××××× x’ 00 x’ 10 x’ 10 x’ 00 x’ 10 x’ 11 x’ 00 x’ 10 x’ 00 01 10 11 11 11 11 01 11 11 001011011101110110111111111 bit 3 bit 2 bit 1 bit 0 timing stro...

  • Page 262

    Chapter 13 lcd controller/driver 262 user’s manual u15331ej4v1ud figure 13-11. Three-time-slice lcd drive waveform examples (1/3 bias method) v lc0 v lc2 com0 +v lcd 0 com0-s9 -v lcd v lc1 +1/3v lcd -1/3v lcd v ss v lc0 v lc2 com1 v lc1 v ss v lc0 v lc2 com2 v lc1 v ss v lc0 v lc2 s9 v lc1 v ss +v l...

  • Page 263

    Chapter 13 lcd controller/driver user’s manual u15331ej4v1ud 263 13.7.2 four-time-slice display example figure 13-13 shows how a 14-digit lcd panel having the display pattern shown in figure 13-12 is connected to the segment signals (s0 to s27) and the common signals (com0 to com3) of the µ pd789489...

  • Page 264

    Chapter 13 lcd controller/driver 264 user’s manual u15331ej4v1ud figure 13-13. Example of connecting four-time-slice lcd panel 0010100010110010001000101000 0110010101110111011101100101 0111111110100111110101111111 0001011011111111111100010110 bit 3 bit 2 bit 1 bit 0 timing strobe data memory address...

  • Page 265

    Chapter 13 lcd controller/driver user’s manual u15331ej4v1ud 265 figure 13-14. Four-time-slice lcd drive waveform examples (1/3 bias method) t f v lc0 v lc2 com0 +v lcd 0 com0-s16 -v lcd v lc1 +1/3v lcd -1/3v lcd v ss v lc0 v lc2 com1 v lc1 v ss v lc0 v lc2 com2 v lc1 v ss v lc0 v lc2 com3 v lc1 v s...

  • Page 266

    Chapter 13 lcd controller/driver 266 user’s manual u15331ej4v1ud 13.8 supplying lcd drive voltages v lc0 , v lc1 , and v lc2 the µ pd789489 subseries contains a booster circuit ( ×3 only) to generate a supply voltage to drive the lcd. The internal lcd reference voltage is output from the v lc2 pin. ...

  • Page 267

    User’s manual u15331ej4v1ud 267 chapter 14 multiplier 14.1 multiplier function the multiplier has the following function. • calculation of 8 bits × 8 bits = 16 bits 14.2 multiplier configuration (1) 16-bit multiplication result storage register 0 (mul0) this register stores the 16-bit result of mult...

  • Page 268

    Chapter 14 multiplier 268 user’s manual u15331ej4v1ud figure 14-1. Block diagram of multiplier internal bus selector counter value 3 cpu clock start clear counter output 16-bit adder 16-bit multiplication result storage register 0 (master) (mul0) 16-bit multiplication result storage register 0 (slav...

  • Page 269

    Chapter 14 multiplier user’s manual u15331ej4v1ud 269 14.3 multiplier control register the multiplier is controlled by the following register. • multiplier control register 0 (mulc0) (1) multiplier control register 0 (mulc0) mulc0 indicates the operating status of the multiplier after operation, as ...

  • Page 270

    Chapter 14 multiplier 270 user’s manual u15331ej4v1ud 14.4 multiplier operation the multiplier of the µpd789489 subseries can execute the calculation of 8 bits × 8 bits = 16 bits. Figure 14-3 shows the operation timing of the multiplier where mra0 is set to aah and mrb0 is set to d3h. Counting is st...

  • Page 271

    User’s manual u15331ej4v1ud 271 chapter 15 remote controller receiver ( µ pd789489, 78f9489 only) 15.1 remote controller receiver functions the remote controller receiver uses the following remote controller modes. • type a reception mode … guide pulse (half clock) provided 15.2 remote controller re...

  • Page 272

    Chapter 15 remote controller receiver ( µ pd789489, 78f9489 only) user’s manual u15331ej4v1ud 272 figure 15-1. Block diagram of remote controller receiver rin/p34 noise canceler f x /2 6 f x /2 7 f x /2 8 f xt clock counter selector remote controller receive control register ( rmcn) internal bus rmi...

  • Page 273

    Chapter 15 remote controller receiver ( µ pd789489, 78f9489 only) user’s manual u15331ej4v1ud 273 (2) remote controller receive data register (rmdr) this register holds the remote controller reception data. When the remote controller receive shift register (rmsr) overflows, the data in rmsr is trans...

  • Page 274

    Chapter 15 remote controller receiver ( µ pd789489, 78f9489 only) user’s manual u15331ej4v1ud 274 (4) remote controller receive gphs compare register (rmgphs) this register is used to detect the high level of a remote controller guide pulse (short side). Rmgphs is set with an 8-bit memory manipulati...

  • Page 275

    Chapter 15 remote controller receiver ( µ pd789489, 78f9489 only) user’s manual u15331ej4v1ud 275 (8) remote controller receive dh0s compare register (rmdh0s) this register is used to detect the high level of remote controller data 0 (short side). Rmdh0s is set with an 8-bit memory manipulation inst...

  • Page 276

    Chapter 15 remote controller receiver ( µ pd789489, 78f9489 only) user’s manual u15331ej4v1ud 276 (12) remote controller receive end-width select register (rmer) this register determines the interval between the timing at which the intrend signal is output. Rmer is set with an 8-bit memory manipulat...

  • Page 277

    Chapter 15 remote controller receiver ( µ pd789489, 78f9489 only) user’s manual u15331ej4v1ud 277 15.3 registers to control remote controller receiver the remote controller receiver is controlled by the following register. • remote controller receive control register (rmcn) (1) remote controller rec...

  • Page 278

    Chapter 15 remote controller receiver ( µ pd789489, 78f9489 only) user’s manual u15331ej4v1ud 278 figure 15-3. Format of remote controller receive control register (2/2) symbol 7 6 5 4 3 2 1 0 address after reset r/w rmcn rmen ncw prsen rmin 0 0 rmck1 rmck0 ff60h 00h r/w rmck1 rmck0 selection of sou...

  • Page 279

    Chapter 15 remote controller receiver ( µ pd789489, 78f9489 only) user’s manual u15331ej4v1ud 279 15.4 operation of remote controller receiver the following remote controller reception mode is used for this remote controller receiver. • type a reception mode with guide pulse (half clock) 15.4.1 form...

  • Page 280

    Chapter 15 remote controller receiver ( µ pd789489, 78f9489 only) user’s manual u15331ej4v1ud 280 figure 15-5. Operation flow of type a reception mode note read rmdr before data has been set to all the bits of rmsr. Longer than end interval? No yes start yes no generate intgp set data to all bits of...

  • Page 281

    Chapter 15 remote controller receiver ( µ pd789489, 78f9489 only) user’s manual u15331ej4v1ud 281 15.4.3 timing operation varies depending on the positions of the rin input waveform below. (1) guide pulse high level width determination relationship between rmgphs/rmgphl/counter position of waveform ...

  • Page 282

    Chapter 15 remote controller receiver ( µ pd789489, 78f9489 only) user’s manual u15331ej4v1ud 282 (3) data high level width determination relationship between rmdh0s/rmdh0l/rmdh1s/rmdh1l/counter position of waveform corresponding operation counter : short error interrupt intrerr is generated. Measur...

  • Page 283

    Chapter 15 remote controller receiver ( µ pd789489, 78f9489 only) user’s manual u15331ej4v1ud 283 (4) end width determination rin rmdls rmdll rin rmer ∆ relationship between rmer/counter position of waveform corresponding operation counter : short error interrupt intrerr is generated. Measuring the ...

  • Page 284

    Chapter 15 remote controller receiver ( µ pd789489, 78f9489 only) user’s manual u15331ej4v1ud 284 figure 15-6. Setting example (where n1 = 1, n2 = 2) rin rin_2 t w rin_1 clock rmgphs/rmdh0s/rmdh1s n1 n2 rmgphl/rmdh0l/rmdh1l rmdls rmdll t we rmer (1) formula for rmgphs, rmdls, rmdh0s, and rmdh1s − 2 ...

  • Page 285

    Chapter 15 remote controller receiver ( µ pd789489, 78f9489 only) user’s manual u15331ej4v1ud 285 15.4.5 error interrupt generation timing after the guide pulse has been detected normally, the intrerr signal is generated under any of the following conditions. • counter • rmdll ≤ counter and counter ...

  • Page 286

    Chapter 15 remote controller receiver ( µ pd789489, 78f9489 only) user’s manual u15331ej4v1ud 286 figure 15-7. Generation timing of intrerr signal rin intrerr rin intrerr rin intrerr rin intrerr rin intrerr rin intrerr rin intrerr intrend rin intrerr rin intrerr example 1 counter → intrerr is not ge...

  • Page 287

    Chapter 15 remote controller receiver ( µ pd789489, 78f9489 only) user’s manual u15331ej4v1ud 287 15.4.6 noise elimination this remote controller receiver provides a function that supplies the signals input from the outside to the rin pin after eliminating noise. Noise width can be eliminated by set...

  • Page 288

    Chapter 15 remote controller receiver ( µ pd789489, 78f9489 only) user’s manual u15331ej4v1ud 288 figure 15-8. Noise elimination operation example (1/2) (a) 1-clock noise elimination (prsen = 0, ncw = 0) remark internal rin is a signal after synchronization and sampling are performed twice, and is t...

  • Page 289

    Chapter 15 remote controller receiver ( µ pd789489, 78f9489 only) user’s manual u15331ej4v1ud 289 figure 15-8. Noise elimination operation example (2/2) (c) 2-clock noise elimination (prsen = 1, ncw = 0) remark internal rin is a signal after synchronization and sampling are performed twice, and is t...

  • Page 290

    290 user’s manual u15331ej4v1ud chapter 16 interrupt functions 16.1 interrupt function types the following two types of interrupt functions are used. (1) non-maskable interrupt this interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top priority ov...

  • Page 291

    Chapter 16 interrupt functions user’s manual u15331ej4v1ud 291 table 16-1. Interrupt sources ( µ pd789488, 78f9488) interrupt source interrupt type priority note 1 name trigger internal/ external vector table address basic configuration type note 2 non-maskable − intwdt watchdog timer overflow (with...

  • Page 292

    Chapter 16 interrupt functions 292 user’s manual u15331ej4v1ud table 16-2. Interrupt sources ( µ pd789489, 78f9489) interrupt source interrupt type priority note 1 name trigger internal/ external vector table address basic configuration type note 2 non-maskable − intwdt watchdog timer overflow (with...

  • Page 293

    Chapter 16 interrupt functions user’s manual u15331ej4v1ud 293 figure 16-1. Basic configuration of interrupt function (a) internal non-maskable interrupt internal bus interrupt request vector table address generator standby release signal (b) internal maskable interrupt mk if ie internal bus interru...

  • Page 294

    Chapter 16 interrupt functions 294 user’s manual u15331ej4v1ud 16.3 registers controlling interrupt function the following five types of registers are used to control the interrupt functions. • interrupt request flag registers (if0 to if2) • interrupt mask flag registers (mk0 to mk2) • external inte...

  • Page 295

    Chapter 16 interrupt functions user’s manual u15331ej4v1ud 295 (1) interrupt request flag registers (if0 to if2) an interrupt request flag is set (1) when the corresponding interrupt request is generated, or when an instruction is executed. It is cleared (0) when the interrupt request is acknowledge...

  • Page 296

    Chapter 16 interrupt functions 296 user’s manual u15331ej4v1ud (2) interrupt mask flag registers (mk0 to mk2) interrupt mask flags are used to enable and disable the corresponding maskable interrupts. Mk0 to mk2 are set with a 1-bit or 8-bit memory manipulation instruction. Reset input sets these re...

  • Page 297

    Chapter 16 interrupt functions user’s manual u15331ej4v1ud 297 (3) external interrupt mode registers (intm0, intm1) these registers are used to specify the valid edge for intp0 to intp3. Intm0 and intm1 are set with an 8-bit memory manipulation instruction. Reset input sets these registers to 00h. F...

  • Page 298

    Chapter 16 interrupt functions 298 user’s manual u15331ej4v1ud (4) program status word (psw) the program status word is used to hold the instruction execution results and the current status of the interrupt requests. The ie flag, used to enable and disable maskable interrupts, is mapped to the psw. ...

  • Page 299

    Chapter 16 interrupt functions user’s manual u15331ej4v1ud 299 (5) key return mode register 00 (krm00) this register is used to set the pin that is to detect the key return signal (rising edge of port 0). Krm00 is set with a 1-bit or 8-bit memory manipulation instruction. Reset input sets this regis...

  • Page 300

    Chapter 16 interrupt functions 300 user’s manual u15331ej4v1ud (6) key return mode register 01 (krm01) ( µ pd789489, 78f9489 only) this register is used to set the pin that is to detect the key return signal (falling edge of port 6). Krm01 is set with a 1-bit or 8-bit memory manipulation instruction...

  • Page 301

    Chapter 16 interrupt functions user’s manual u15331ej4v1ud 301 16.4 interrupt servicing operation 16.4.1 non-maskable interrupt request acknowledgment operation the non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not subject to interrupt priori...

  • Page 302

    Chapter 16 interrupt functions 302 user’s manual u15331ej4v1ud figure 16-10. Flow from generation of non-maskable interrupt request to acknowledgment start wdtm4 = 1 (watchdog timer mode is selected) interval timer no wdt overflows no yes reset processing no yes yes interrupt request is generated in...

  • Page 303

    Chapter 16 interrupt functions user’s manual u15331ej4v1ud 303 16.4.2 maskable interrupt request acknowledgment operation a maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt is ac...

  • Page 304

    Chapter 16 interrupt functions 304 user’s manual u15331ej4v1ud figure 16-14. Interrupt request acknowledgment timing (example: mov a, r) clock cpu mov a, r saving psw and pc, and jump to interrupt servicing 8 clocks interrupt servicing program interrupt if the interrupt request has generated an inte...

  • Page 305

    Chapter 16 interrupt functions user’s manual u15331ej4v1ud 305 figure 16-16. Example of multiple interrupt servicing example 1. Acknowledging multiple interrupts intyy ei main servicing ei intyy servicing intxx servicing reti ie = 0 intxx reti ie = 0 the interrupt request intyy is acknowledged durin...

  • Page 306

    Chapter 16 interrupt functions 306 user’s manual u15331ej4v1ud 16.4.4 putting interrupt requests on hold if an interrupt request (such as a maskable, non-maskable, or external interrupt) is generated when a certain type of instruction is being executed, the interrupt request will not be acknowledged...

  • Page 307

    User’s manual u15331ej4v1ud 307 chapter 17 standby function 17.1 standby function and configuration 17.1.1 standby function the standby function is used to reduce the power consumption of the system and can be effected in the following two modes. (1) halt mode this mode is set when the halt instruct...

  • Page 308

    Chapter 17 standby function 308 user’s manual u15331ej4v1ud 17.1.2 register controlling standby function the wait time after the stop mode is released upon interrupt request generation until oscillation stabilizes is controlled by the oscillation stabilization time selection register (osts). Osts is...

  • Page 309

    Chapter 17 standby function user’s manual u15331ej4v1ud 309 17.2 standby function operation 17.2.1 halt mode (1) halt mode the halt mode is set by executing the halt instruction. The operation statuses in the halt mode are shown in the following table. Table 17-1. Operation statuses in halt mode hal...

  • Page 310

    Chapter 17 standby function 310 user’s manual u15331ej4v1ud (2) releasing halt mode the halt mode can be released by the following three sources. (a) release by unmasked interrupt request the halt mode is released by an unmasked interrupt request. In this case, if interrupts are enabled to be acknow...

  • Page 311

    Chapter 17 standby function user’s manual u15331ej4v1ud 311 (c) release by reset input when the halt mode is released by the reset signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. Figure 17-3. Releasing halt ...

  • Page 312

    Chapter 17 standby function 312 user’s manual u15331ej4v1ud 17.2.2 stop mode (1) setting and operation status of stop mode the stop mode is set by executing the stop instruction. Caution because the standby mode can be released by an interrupt request signal, the standby mode is released as soon as ...

  • Page 313

    Chapter 17 standby function user’s manual u15331ej4v1ud 313 (2) releasing stop mode the stop mode can be released by the following two sources. (a) release by unmasked interrupt request the stop mode can be released by an unmasked interrupt request. In this case, if interrupts are enabled to be ackn...

  • Page 314

    Chapter 17 standby function 314 user’s manual u15331ej4v1ud (b) release by reset input when the stop mode is released by the reset signal, the reset operation is performed after the oscillation stabilization time has elapsed. Figure 17-5. Releasing stop mode by reset input stop instruction reset sig...

  • Page 315

    User’s manual u15331ej4v1ud 315 chapter 18 reset function the following two operations are available to generate reset signals. (1) external reset input by reset pin (2) internal reset by watchdog timer program loop time detection external and internal reset have no functional differences. In both c...

  • Page 316

    Chapter 18 reset function 316 user’s manual u15331ej4v1ud figure 18-2. Reset timing by reset input x1 reset internal reset signal port pin during normal operation delay delay hi-z reset period (oscillation stops) normal operation (reset processing) oscillation stabilization time wait figure 18-3. Re...

  • Page 317

    Chapter 18 reset function user’s manual u15331ej4v1ud 317 table 18-1. Status of hardware after reset (1/2) hardware status after reset program counter (pc) note 1 contents of reset vector table (0000h, 0001h) set stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2...

  • Page 318

    Chapter 18 reset function 318 user’s manual u15331ej4v1ud table 18-1. Status of hardware after reset (2/2) hardware status after reset operation mode register (csim1a0) 00h shift register (sio1a0) 00h buffer memory (sbmem0 to sbmemf) undefined automatic data transmit/receive control register (adtc0)...

  • Page 319

    User’s manual u15331ej4v1ud 319 chapter 19 flash memory version the µ pd78f9488 is available as the flash memory version of the µ pd789488 (mask rom version). The µ pd78f9489 is available as the flash memory version of the µ pd789489 (mask rom version). The differences between the µ pd78f9488, 78f94...

  • Page 320

    Chapter 19 flash memory version 320 user’s manual u15331ej4v1ud 19.1 flash memory characteristics flash memory programming is performed by connecting a dedicated flash programmer (flashpro iii (part no. Fl- pr3, pg-fp3)/flashpro iv (part no. Fl-pr4, pg-fp4)) to the target system with the µ pd78f9488...

  • Page 321

    Chapter 19 flash memory version user’s manual u15331ej4v1ud 321 19.1.2 communication mode use the communication mode shown in table 19-2 to perform communication between the dedicated flash programmer and µ pd78f9488 or 78f9489. Table 19-2. Communication mode list type setting note 1 cpu clock commu...

  • Page 322

    Chapter 19 flash memory version 322 user’s manual u15331ej4v1ud figure 19-3. Example of connection with dedicated flash programmer (a) 3-wire serial i/o dedicated flash programmer vpp1 vdd reset sck so si clk note 1 gnd v pp v dd reset sck20 si20 so20 x1 v ss pd78f9488 pd78f9489 µ µ (b) 3-wire seria...

  • Page 323

    Chapter 19 flash memory version user’s manual u15331ej4v1ud 323 if flashpro iii/flashpro iv is used as a dedicated flash programmer, the following signals are generated for the µ pd78f9488 and 78f9489. For details, refer to the manual of flashpro iii/flashpro iv. Table 19-3. Pin connection list sign...

  • Page 324

    Chapter 19 flash memory version 324 user’s manual u15331ej4v1ud 19.1.3 on-board pin processing when performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. An on-board function that allows switching between normal operation mod...

  • Page 325

    Chapter 19 flash memory version user’s manual u15331ej4v1ud 325 (1) signal conflict if the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other...

  • Page 326

    Chapter 19 flash memory version 326 user’s manual u15331ej4v1ud if the reset signal of the dedicated flash programmer is connected to the reset pin connected to the reset signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal generator. If ...

  • Page 327

    Chapter 19 flash memory version user’s manual u15331ej4v1ud 327 19.1.4 connection of adapter for flash writing the following figure shows an example of recommended connection when the adapter for flash writing is used. Figure 19-8. Wiring example for flash writing adapter with 3-wire serial i/o gnd ...

  • Page 328

    Chapter 19 flash memory version 328 user’s manual u15331ej4v1ud figure 19-9. Wiring example for flash writing adapter with 3-wire serial i/o with handshake pd78f9488, pd78f9489 gnd vdd vdd2 (lvdd) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 ‘5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 ...

  • Page 329

    Chapter 19 flash memory version user’s manual u15331ej4v1ud 329 figure 19-10. Wiring example for flash writing adapter with uart gnd vdd si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 4...

  • Page 330

    Chapter 19 flash memory version 330 user’s manual u15331ej4v1ud 19.2 cautions on µ pd78f9488 and 78f9489 (1) when using halt mode with subclock multiplied by four observe the following constraints when using the flash version ( µ pd78f9488 and 78f9489) in the halt mode with the subclock multiplied b...

  • Page 331

    User’s manual u15331ej4v1ud 331 chapter 20 mask options the µ pd789488 and 789489 have the following mask options. • pin function the segment pins of the lcd and port 7 (input port) can be selected in 1-bit units. S (16 + n) p7n (n = 0 to 3) the segment pins of the lcd and port 8 (i/o port) can be s...

  • Page 332

    332 user’s manual u15331ej4v1ud chapter 21 instruction set this chapter lists the instruction set of the µ pd789489 subseries. For details of the operation and machine language (instruction code) of each instruction, refer to 78k/0s series instructions user’s manual (u11047e). 21.1 operation 21.1.1 ...

  • Page 333

    Chapter 21 instruction set user’s manual u15331ej4v1ud 333 21.1.2 description of “operation” column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de ...

  • Page 334

    Chapter 21 instruction set 334 user’s manual u15331ej4v1ud 21.2 operation list mnemonic operands bytes clocks operation flag z ac cy mov r, #byte 3 6 r ← byte saddr, #byte 3 6 (saddr) ← byte sfr, #byte 3 6 sfr ← byte a, r note 1 2 4 a ← r r, a note 1 2 4 r ← a a, saddr 2 4 a ← (saddr) saddr, a 2 4 (...

  • Page 335

    Chapter 21 instruction set user’s manual u15331ej4v1ud 335 mnemonic operands bytes clocks operation flag z ac cy movw rp, #word 3 6 rp ← word ax, saddrp 2 6 ax ← (saddrp) saddrp, ax 2 8 (saddrp) ← ax ax, rp note 1 4 ax ← rp rp, ax note 1 4 rp ← ax xchw ax, rp note 1 8 ax ↔ rp add a, #byte 2 4 a, cy ...

  • Page 336

    Chapter 21 instruction set 336 user’s manual u15331ej4v1ud mnemonic operands bytes clocks operation flag z ac cy subc a, #byte 2 4 a, cy ← a − byte − cy x x x saddr, #byte 3 6 (saddr), cy ← (saddr) − byte − cy x x x a, r 2 4 a, cy ← a − r − cy x x x a, saddr 2 4 a, cy ← a − (saddr) − cy x x x a, !Ad...

  • Page 337

    Chapter 21 instruction set user’s manual u15331ej4v1ud 337 mnemonic operands bytes clocks operation flag z ac cy cmp a, #byte 2 4 a − byte x x x saddr, #byte 3 6 (saddr) − byte x x x a, r 2 4 a − r x x x a, saddr 2 4 a − (saddr) x x x a, !Addr16 3 8 a − (addr16) x x x a, [hl] 1 6 a − (hl) x x x a, [...

  • Page 338

    Chapter 21 instruction set 338 user’s manual u15331ej4v1ud mnemonic operands bytes clocks operation flag z ac cy call !Addr16 3 6 (sp − 1) ← (pc + 3) h , (sp − 2) ← (pc + 3) l , pc ← addr16, sp ← sp − 2 callt [addr5] 1 8 (sp − 1) ← (pc + 1) h , (sp − 2) ← (pc + 1) l , pc h ← (00000000, addr5 + 1), p...

  • Page 339

    Chapter 21 instruction set user’s manual u15331ej4v1ud 339 21.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, inc, dec, ror, rol, rorc, rolc, push, pop, dbnz 2nd operand 1st operand #byte a r sfr saddr !Addr16 psw [de] [hl] [hl+byte]...

  • Page 340

    Chapter 21 instruction set 340 user’s manual u15331ej4v1ud (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw 2nd operand 1st operand #word ax rp note saddrp sp none ax addw subw cmpw movw xchw movw movw rp movw movw note incw decw push pop saddrp movw sp movw note only when...

  • Page 341

    Chapter 21 instruction set user’s manual u15331ej4v1ud 341 (4) call instructions/branch instructions call, callt, br, bc, bnc, bz, bnz, dbnz 2nd operand 1st operand ax !Addr16 [addr5] $addr16 basic instructions br call br callt br bc bnc bz bnz compound instructions dbnz (5) other instructions ret, ...

  • Page 342

    342 user’s manual u15331ej4v1ud chapter 22 electrical specifications ( µ pd789488, 78f9488, 789489, 78f9489) absolute maximum ratings (t a = 25 °c) parameter symbol conditions ratings unit v dd power supply voltage av dd v dd = av dd −0.3 to +6.5 v v pp µ pd78f9488, 78f9489 only, note 1 −0.3 to +10....

  • Page 343

    Chapter 22 electrical specifications ( µ pd789488, 78f9488, 789489, 78f9489) user’s manual u15331ej4v1ud 343 caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product i...

  • Page 344

    Chapter 22 electrical specifications ( µ pd789488, 78f9488, 789489, 78f9489) 344 user’s manual u15331ej4v1ud main system clock oscillator characteristics (t a = –40 to +85 °c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. Typ. Max. Unit oscillation frequency (f x ) not...

  • Page 345

    Chapter 22 electrical specifications ( µ pd789488, 78f9488, 789489, 78f9489) user’s manual u15331ej4v1ud 345 subsystem clock oscillator characteristics (t a = –40 to +85 °c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. Typ. Max. Unit oscillation frequency (f xt ) note...

  • Page 346

    Chapter 22 electrical specifications ( µ pd789488, 78f9488, 789489, 78f9489) 346 user’s manual u15331ej4v1ud dc characteristics (t a = –40 to +85 °c, v dd = 1.8 to 5.5 v) (1/6) parameter symbol conditions min. Typ. Max. Unit per pin 10 ma output current, low i ol all pins 80 ma per pin –1 ma output ...

  • Page 347

    Chapter 22 electrical specifications ( µ pd789488, 78f9488, 789489, 78f9489) user’s manual u15331ej4v1ud 347 dc characteristics (t a = –40 to +85 °c, v dd = 1.8 to 5.5 v) (2/6) parameter symbol conditions min. Typ. Max. Unit i lih1 p00 to p07, p10, p11, p20 to p25, p30 to p34, p60 to p67, p70 to p73...

  • Page 348

    Chapter 22 electrical specifications ( µ pd789488, 78f9488, 789489, 78f9489) 348 user’s manual u15331ej4v1ud dc characteristics (t a = –40 to +85 °c, v dd = 1.8 to 5.5 v) (3/6) parameter symbol conditions min. Typ. Max. Unit v dd = 5.0 v ±10% note 2 2 3.5 ma v dd = 3.0 v ±10% note 3 0.4 1 ma i dd1 5...

  • Page 349

    Chapter 22 electrical specifications ( µ pd789488, 78f9488, 789489, 78f9489) user’s manual u15331ej4v1ud 349 dc characteristics (t a = –40 to +85 °c, v dd = 1.8 to 5.5 v) (4/6) parameter symbol conditions min. Typ. Max. Unit v dd = 5.0 v ±10% note 2 5.5 9.0 ma v dd = 3.0 v ±10% note 3 1.3 2.3 ma i d...

  • Page 350

    Chapter 22 electrical specifications ( µ pd789488, 78f9488, 789489, 78f9489) 350 user’s manual u15331ej4v1ud dc characteristics (t a = –40 to +85 °c, v dd = 1.8 to 5.5 v) (5/6) parameter symbol conditions min. Typ. Max. Unit v dd = 5.0 v ±10% note 2 2.5 5.0 ma v dd = 3.0 v ±10% note 3 0.5 1.2 ma i d...

  • Page 351

    Chapter 22 electrical specifications ( µ pd789488, 78f9488, 789489, 78f9489) user’s manual u15331ej4v1ud 351 dc characteristics (t a = –40 to +85 °c, v dd = 1.8 to 5.5 v) (6/6) parameter symbol conditions min. Typ. Max. Unit v dd = 5.0 v ±10% note 2 6.0 12.0 ma v dd = 3.0 v ±10% note 3 1.6 3.2 ma i ...

  • Page 352

    Chapter 22 electrical specifications ( µ pd789488, 78f9488, 789489, 78f9489) 352 user’s manual u15331ej4v1ud ac characteristics (1) basic operation (t a = –40 to +85 °c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. Typ. Max. Unit v dd = 2.7 to 5.5 v 0.4 8.0 µ s operating with main system cl...

  • Page 353

    Chapter 22 electrical specifications ( µ pd789488, 78f9488, 789489, 78f9489) user’s manual u15331ej4v1ud 353 (2) serial interface 20 (sio20) (t a = –40 to +85 °c, v dd = 1.8 to 5.5 v) (a) 3-wire serial i/o mode (internal clock output) parameter symbol conditions min. Typ. Max. Unit v dd = 2.7 to 5.5...

  • Page 354

    Chapter 22 electrical specifications ( µ pd789488, 78f9488, 789489, 78f9489) 354 user’s manual u15331ej4v1ud (d) uart mode (external clock input) parameter symbol conditions min. Typ. Max. Unit v dd = 2.7 to 5.5 v 800 ns asck20 cycle time t kcy3 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns...

  • Page 355

    Chapter 22 electrical specifications ( µ pd789488, 78f9488, 789489, 78f9489) user’s manual u15331ej4v1ud 355 (3) serial interface 1a0 (sio1a0) (t a = –40 to +85 °c, v dd = 1.8 to 5.5 v) (a) 3-wire serial i/o mode, 3-wire serial i/o mode with automatic transmit/receive function (internal clock output...

  • Page 356

    Chapter 22 electrical specifications ( µ pd789488, 78f9488, 789489, 78f9489) 356 user’s manual u15331ej4v1ud ac timing measurement points (excluding x1 and xt1 inputs) 0.8v dd 0.2v dd point of measurement 0.8v dd 0.2v dd clock timing 1/f x t xl t xh x1 input v ih4 (min.) v il4 (max.) 1/f xt t xtl t ...

  • Page 357

    Chapter 22 electrical specifications ( µ pd789488, 78f9488, 789489, 78f9489) user’s manual u15331ej4v1ud 357 key return input timing t krl kr0 to kr7 ( pd789488, 78f9488) , kr00 to kr07, kr10 to kr17 ( pd789489, 78f9489) µ µ reset input timing reset t rsl serial transfer timing 3-wire serial i/o mod...

  • Page 358

    Chapter 22 electrical specifications ( µ pd789488, 78f9488, 789489, 78f9489) 358 user’s manual u15331ej4v1ud 10-bit a/d converter characteristics (t a = –40 to +85 °c, 1.8 v ≤ av dd = v dd ≤ 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. Typ. Max. Unit resolution 10 10 10 bit 4.5 v ≤ av...

  • Page 359

    Chapter 22 electrical specifications ( µ pd789488, 78f9488, 789489, 78f9489) user’s manual u15331ej4v1ud 359 lcd characteristics (t a = –40 to +85 °c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. Typ. Max. Unit gain = 1 0.84 1.0 1.165 v lcd output voltage variation range v lcd2 c1 to c4 not...

  • Page 360

    Chapter 22 electrical specifications ( µ pd789488, 78f9488, 789489, 78f9489) 360 user’s manual u15331ej4v1ud data retention timing (stop mode release by reset) v dd data retention mode stop mode halt mode internal reset operation operation mode t srel t wait stop instruction execution v dddr reset d...

  • Page 361

    Chapter 22 electrical specifications ( µ pd789488, 78f9488, 789489, 78f9489) user’s manual u15331ej4v1ud 361 flash memory writing and erasing characteristics (t a = 10 to 40 °c, v dd = 1.8 to 5.5 v) ( µ pd78f9488, 78f9489 only) parameter symbol conditions min. Typ. Max. Unit write/erase operating fr...

  • Page 362

    362 user’s manual u15331ej4v1ud chapter 23 characteristics curves of lcd controller/driver (reference values) (1) characteristics curves of voltage boosting stabilization time the following shows the characteristics curves of the time from the start of voltage boosting (vaon0 = 1) and the changes in...

  • Page 363

    Chapter 23 characteristics curves of lcd controller/driver (reference values) user’s manual u15331ej4v1ud 363 (2) temperature characteristics of lcd output voltage the following shows the temperature characteristics curves of lcd output voltage. Lcd output voltage [v] v lcd2 v lcd1 v lcd0 v lcd2 v l...

  • Page 364

    364 user’s manual u15331ej4v1ud chapter 24 package drawings 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.P.) at maximum material condition. Item millimeters a b d g 17.20 ± 0.20 14.00 ± 0.20 0.13 0.825 i 17.20 ± 0.20 j c 14.00 ± 0.20 h 0.32 ±...

  • Page 365

    Chapter 24 package drawings user’s manual u15331ej4v1ud 365 80-pin plastic tqfp (fine pitch) (12x12) item millimeters g h 0.22 ± 0.05 1.25 a 14.0 ± 0.2 c 12.0 ± 0.2 d f 1.25 14.0 ± 0.2 b 12.0 ± 0.2 m n 0.08 0.145 ± 0.05 p q 0.1 ± 0.05 1.0 j 0.5 (t.P.) k l 0.5 1.0 ± 0.2 i 0.08 s 1.1 ± 0.1 r 3 °+ 4 ° ...

  • Page 366

    366 user’s manual u15331ej4v1ud chapter 25 recommended soldering conditions the µ pd789489 subseries should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. Fo...

  • Page 367

    Chapter 25 recommended soldering conditions user’s manual u15331ej4v1ud 367 table 25-1. Surface mounting type soldering conditions (2/3) (3) µ pd78f9489gc-8bt: 80-pin plastic qfp (14x14) soldering method soldering conditions recommended condition symbol interface reflow package peak temperature: 235...

  • Page 368

    Chapter 25 recommended soldering conditions 368 user’s manual u15331ej4v1ud table 25-1. Surface mounting type soldering conditions (3/3) (5) µ pd789488gc- ×××-8bt-a: 80-pin plastic qfp (14x14) µ pd78f9488gc-8bt-a: 80-pin plastic qfp (14x14) µ pd789489gc- ×××-8bt-a: 80-pin plastic qfp (14x14) µ pd78f...

  • Page 369

    369 user’s manual u15331ej4v1ud appendix a development tools the following development tools are available for development of systems using the µ pd789489 subseries. Figure a-1 shows development tools. • support for pc98-nx series unless specified otherwise, the products supported by ibm pc/at™ comp...

  • Page 370

    Appendix a development tools user’s manual u15331ej4v1ud 370 figure a-1. Development tools language processing software · assembler package · c compiler package · device file · c library source file note 1 debugging software · integrated debugger · system simulator host machine (pc or ews) interface...

  • Page 371

    Appendix a development tools user’s manual u15331ej4v1ud 371 a.1 software package software tools for development of the 78k/0s series are combined in this package. The following tools are included. Ra78k0s, cc78k0s, id78k0s-ns, sm78k0s, and device files sp78k0s software package part number: µ s ××××...

  • Page 372

    Appendix a development tools 372 user’s manual u15331ej4v1ud remark ×××× in the part number differs depending on the host machine and operating system to be used. µ s ××××ra78k0s µ s ××××cc78k0s ×××× host machine os supply medium ab13 japanese windows 3.5" 2hd fd bb13 english windows ab17 japanese w...

  • Page 373

    Appendix a development tools user’s manual u15331ej4v1ud 373 a.5 debugging tools (hardware) ie-78k0s-ns in-circuit emulator in-circuit emulator for debugging hardware and software of an application system using the 78k/0s series. Can be used with the integrated the debugger id78k0s-ns. Used in combi...

  • Page 374

    Appendix a development tools 374 user’s manual u15331ej4v1ud a.6 debugging tools (software) this debugger supports the in-circuit emulators ie-78k0s-ns and ie-78k0s-ns-a for the 78k/0s series. The id78k0s-ns is windows-based software. It has improved c-compatible debugging functions and can display ...

  • Page 375

    User’s manual u15331ej4v1ud 375 appendix b notes on target system design figures b-1 to b-6 show the conditions when connecting the emulation probe to the conversion adapter or conversion socket. Follow the configuration below and consider the shape of parts to be mounted on the target system when d...

  • Page 376

    Appendix b notes on target system design user’s manual u15331ej4v1ud 376 figure b-2. Connection conditions of target system (when np-80gc-tq is used) emulation probe np-80gc-tq emulation board ie-789488-ns-em1 24.8 mm 25 mm 40 mm 34 mm target system 21 mm pin 1 11 mm 21 mm conversion adapter tgc-080...

  • Page 377

    Appendix b notes on target system design user’s manual u15331ej4v1ud 377 (2) np-80gk, np-h80gk-tq figure b-4. Distance between in-circuit emulator and conversion adapter (80gk) 170 mm note in-circuit emulator ie-78k0s-ns or ie-78k0s-ns-a emulation board ie-789488-ns-em1 conversion adapter tgk-080sdp...

  • Page 378

    Appendix b notes on target system design user’s manual u15331ej4v1ud 378 figure b-5. Connection conditions of target system (when np-80gk is used) emulation probe np-80gk emulation board ie-789488-ns-em1 23 mm 40 mm 34 mm target system 16 mm pin 1 11 mm 25 mm 16 mm conversion adapter tgk-080sdp figu...

  • Page 379

    379 user’s manual u15331ej4v1ud appendix c register index c.1 register index (register names in alphabetic order) [a] a/d conversion result register 0 (adcrl0) .......................................................................................................... 174 a/d converter mode register 0...

  • Page 380

    Appendix c register index 380 user’s manual u15331ej4v1ud [l] lcd clock control register 0 (lcdc0) ..................................................................................................................256 lcd display mode register 0 (lcdm0)...................................................

  • Page 381

    Appendix c register index user’s manual u15331ej4v1ud 381 remote controller receive end width select register (rmer) ............................................................................... 276 remote controller receive shift receive (rmsr)........................................................

  • Page 382

    Appendix c register index 382 user’s manual u15331ej4v1ud c.2 register index (register symbols alphabetic order) [a] adcrl0: a/d conversion result register 0........................................................................................................174 adml0: a/d converter mode register ...

  • Page 383

    Appendix c register index user’s manual u15331ej4v1ud 383 mul0h: 16-bit multiplication result storage register h.................................................................................... 267 mul0l: 16-bit multiplication result storage register l................................................

  • Page 384

    Appendix c register index 384 user’s manual u15331ej4v1ud sio1a0: serial i/o shift register 1a0 ...............................................................................................................218 ssck: subclock selection register ..........................................................

  • Page 385

    User’s manual u15331ej4v1ud 385 appendix d revision history the following table shows the revision history up to this edition. The “applied to:” column indicates the chapters of each edition in which the revision was applied. (1/4) edition major revision from previous edition applied to: correction ...

  • Page 386

    Appendix d revision history user’s manual u15331ej4v1ud 386 (2/4) edition major revision from previous edition applied to: addition of descriptions of µ pd789489, 78f9489 (under development) • key return detection function added to port 6 ( µ pd789489, 78f9489 only) • key return pin name of port 0 c...

  • Page 387

    Appendix d revision history user’s manual u15331ej4v1ud 387 (3/4) edition major revision from previous edition applied to: change of descriptions of µ pd789489, 78f9489 • change of status from under development to development completed • change of the subseries name to “ µ pd789489 subseries” throug...

  • Page 388

    Appendix d revision history user’s manual u15331ej4v1ud 388 (4/4) edition major revision from previous edition applied to: modification of descriptionsin figure 12-4. Format of automatic data transmit/receive interval specification register 0 chapter 12 serial interface 1a0 addition offormal specifi...