Quatech DS-202 User Manual - page 6
FUNCTIONAL DESCRIPTION
D e s i g n e d t o b e c o m p a t i b l e w i t h t h e 1 6 4 5 0 , t h e
1 6 5 5 0 A C E e n t e r s c h a r a c t e r m o d e o n r e s e t a n d i n t h i s
m o d e a p p e a r s a s a 1 6 4 5 0 t o a p p l i c a t i o n s o f t w a r e . A n
a d d i t i o n a l m o d e , F I F O m o d e , c a n b e i n v o k e d t h r o u g h
s o f t w a r e t o r e d u c e C P U o v e r h e a d b y p r o v i d i n g t w o 1 6 -
b y t e F I F O s ( o n e t r a n s m i t , o n e r e c e i v e ) t o b u f f e r d a t a
and reduce the number of interrupts issued to the CPU.
Other features of the 16450/16550 include:
Programmable baud rate, character length, parity,
and number of stop bits.
Automatic addition and removal of start, stop, and
parity bits.
Independent and prioritized transmit, receive and
status interrupts.
The following pages provide a brief summary of the
internal registers available within the 16450 and 16550
ACEs. The registers are addressed as shown in figure 2
b e l o w . R e g i s t e r s a n d f u n c t i o n s s p e c i f i c t o t h e
optional 16550 are indicated with an asterisk (*).
+---------------+------------------------------+
| DLAB A2 A1 A0 | REGISTER DESCRIPTION |
+---------------+------------------------------+
| 0 0 0 0 | Receive buffer (read only) |
| | Transmit holding register |
| | (writeonly) |
| 0 0 0 1 | Interrupt enable |
| x 0 1 0 | Interrupt identification |
| | (read only) |
| | FIFO control
* (write only) |
| x 0 1 1 | Line control |
| x 1 0 0 | MODEM control |
| x 1 0 1 | Line status |
| x 1 1 0 | MODEM status |
| x 1 1 1 | Scratch |
| 1 0 0 0 | Divisor latch (LSB) |
| 1 0 0 1 | Divisor latch (MSB) |
+---------------+------------------------------+
Figure 2. Internal register map for 16450/16550 ACE.
D L A B i s a c c e s s e d t h r o u g h t h e L i n e C o n t r o l
Register.
* with optional 16550.