Es-100m / qs-100m multi-port asynchronous communications adapter user's manual quatech, inc. Tel: (330) 434-3154 662 wolf ledges parkway fax: (330) 434-1409 akron, ohio 44311 bbs: (330) 434-2481.
Es-100 user's manual version 2.00 october 1994 p/n. 940-0019-200
Warranty information quatech inc. Warrants the es-100m / qs-100m to be free of defects for one (1) year from the date of purchase. Quatech inc. Will repair or replace any adapter that fails to perform under normal operating conditions and in accordance with the procedures outlined in this document d...
Table of contents list of figures iii i. General information 1 ii. Installation 2 iii. Addressing ports 5 iv. Interrupt level (irq) 8 interrupt sharing 8 interrupt status register 8 v. External connections 10 channel output configuration 11 vi. Serial port functional description 14 accessing the ser...
List of figures figure 1. Default address and irq settings 2 figure 2. Diagram of qs-100m / es-100m 3 figure 3. Port address map 5 figure 4. Examination of a serial port base address 6 figure 5. Serial port base i/o address selection switches 7 figure 6. Interrupt level (irq) selection 8 figure 7. E...
I. General information the quatech, inc. Es-100m provides eight rs-232 asynchronous serial communication interfaces for ibm-compatible personal computer systems using the 16-bit isa (industry standard architecture) expansion bus. The qs-100m is a four-port version of the same product (with several b...
Ii. Installation if the default address and interrupt settings are sufficient, the qs/es-100m can be quickly installed and put to use. The factory defaults are listed in figure 1. Port address irq serial 1 300 hex 3 serial 2 308 hex 3 serial 3 310 hex 3 serial 4 318 hex 3 serial 5 (es only) 320 hex ...
Figure 2 --- diagram of qs/es-100m (diagram not to scale) sw1 sw2 set addresses here (sw1, sw2) j1 cn1 16450/16550 16450/16550 16450/16550 16450/16550 j10 quatech inc. 16450/16550 16450/16550 16450/16550 16450/16550 j8 j9 j2 j3 j4 j5 j6 j7 j11 j13 j12 j14 j15 j17 j16 j18 set irq level here (j10) sha...
(this page left blank intentionally.) 4 quatech qs-100m/es-100m user's manual.
Iii. Addressing ports setting the address the base address of the qs/es-100m is set using the two dip switch packs. When setting the address selection switches, a switch in the "on" position specifies that the corresponding address line must be a logic 0 for the port to be selected. Similarly, a swi...
Switch sw1 and the first four positions of switch sw2 select address lines a15 through a6. The fifth position of sw2 selects address line a5 on the qs-100m and is not used on the es-100m. This reflects the different i/o space requirements of the two products. The remaining address lines, a4 - a0 for...
Figure 5 --- serial port base i/o address selection switches switch on bit = 0 switch off bit = 1 factory default setting --- 0300 hex on 2 0 0 0 1 1 2 3 4 5 6 sw2 0 0 0 0 0 0 3 1 2 3 4 5 6 sw1 0 0 (no digits) position 6 of sw2 is used to enable or disable the interrupt status register. Another exam...
Iv. Interrupt level (irq) the qs/es-100m allows the use of any interrupt level in the range irq2 to irq7, irq10 to irq12, irq14, or irq15, selected using jumper pack j10. (early versions of the qs/es-100m are limited to irq2-7.) in figure 6, the factory default setting of irq3 is shown. To select a ...
The choice of using the interrupt status register or the uart scratchpads (factory default) is made using position 6 of switch sw2 as shown in figure 7. Figure 7 --- enabling the interrupt status register when a hardware interrupt occurs, reading the interrupt status register will return the interru...
V. External connections rs-232-c devices are classified by their function as either data terminal equipment (dte) or data communication equipment (dce). Generally, data terminal equipment is defined as the communication source and data communication equipment is defined as the device that provides a...
Channel output configuration the qs/es-100m connects to peripheral equipment through rj-11 connectors, or using the optional adapter cables, male d-25 connectors. When the rj-11 connector is converted to a d-25 connector, the conversion cable must be assembled with respect to either a dte or dce con...
The auxin and auxout signals on the rj-11 connector must be determined as well. Auxin may be selected to be either cts or dsr. Auxout may be selected to be either rts or dtr. The decision of which signals to use is made separately for each channel. Figure 13 --- auxiliary signal configuration jumper...
A feature available on the es/qs-100m revision b and newer is the ability to input the carrier detect (dcd) signal from the rj-11 connector. When shipped from the factory, the es/qs-100m is configured for compatibility with revision 'a' of the adapter as shown in figure 14(a) below. In this configur...
Vi. Serial port functional description this section contains information intended for advanced users planning to do custom programming with the qs/es-100m. The information presented here is a technical description of the interface to the 16450 or 16550 uart. The 16450 uart is an improved functional ...
Accessing the serial port registers figure 15 lists the address map for the 16450 and 16550 uarts. Each register can be accessed by reading from or writing to the proper i/o address. This i/o address is determined by adding an offset to the base address set for the particular serial port. The base a...
Interrupt enable register this register is located at i/o address [base+1]. It enables the five types of uart interrupts. Interrupts can be totally disabled by setting all of the enable bits in this register to a logic 0. Setting any bit to a logic 1 enables that particular interrupt. Bit descriptio...
Bit description 7 ffe --- fifo enable: (16550 only) when logic 1, indicates fifo mode enabled. Always logic 0 for the 16450. 6 ffe --- fifo enable: (16550 only) when logic 1, indicates fifo mode enabled. Always logic 0 for the 16450. 5 0 --- reserved 4 0 --- reserved 3 iid2 --- interrupt identificat...
Fifo control register (16550 only) this register, which applies only to the 16550 uart, is a write-only register located at i/o address [base+2]. It is used to enable the fifo mode, clear the fifos, set the threshold level for the receive fifo to generate interrupts, and to set the mode under which ...
Line control register this register is located at i/o address [base+3]. It is used for specifying the format of the asynchronous serial data to be processed by the uart, and to set the divisor latch access bit (dlab) allowing access to the baud rate divisor latches. Bit description 7 dlab --- diviso...
Modem control register this register is located at i/o address [base+4], and is used to control the interface with the modem or device used in place of a modem. This register allows the states of the "modem control signals" to be changed. These are dtr (data terminal ready) and rts (request to send)...
Line status register this register is located at i/o address [base+5]. It is used to provide various types of status information concerning the data transfer. As figure 22 shows, the line status register indicates several types of errors, an empty transmit buffer, a ready receive buffer, or a break ...
Modem status register this register is located at i/o address [base+6]. It reports on the status of signals coming from the modem or equipment used in place of a modem. It allows the current states of "modem control signals" to be sensed. These signals include the dcd (data carrier detect), ri (ring...
Fifo interrupt mode operation (16550 uart only) when the receiver fifo and receiver interrupts are enabled: 1. The receive data interrupt is issued when the receive fifo reaches the trigger level. The interrupt is cleared as soon as the receive fifo falls below the trigger level. 2. The interrupt id...
Fifo polled mode operation (16550 uart only) the receiver and transmitter are operated independently, which would allow either or both to be used in a polled mode rather than using interrupts to determine when the uart needs to be serviced. To use the uart in a polled mode, the software is responsib...
Baud rate selection the 16450 or 16550 uart determines the baud rate of the serial output using a combination of the clock input frequency and the value written to the divisor latches. Standard personal computer serial interfaces use an input clock of 1.8432 mhz. To increase versatility, the qs/es-1...
Desired baud rate divisor latch value error between desired and actual values (%) 50 2304 - 75 1536 - 110 1047 0.026 150 768 - 300 384 - 600 192 - 1200 96 - 1800 64 - 2000 58 0.69 2400 48 - 3600 32 - 4800 24 - 7200 16 - 9600 12 - 19200 6 - 38400 3 - 56000 2 2.86 figure 25 --- divisor latch settings ...
Vii. Specifications bus interface: industry standard architecture (isa) 16-bit bus ibm pc-at tm compatible dimensions: 13.4" x 4.2" serial ports number of ports: qs-100m --- four ports es-100m --- eight ports controllers: 16450 (16550 optional) interface: rj-11 connector male d-25 connector (using o...
Viii. Troubleshooting listed here are some common problems and frequent causes of those problems. Suggestions for corrective action are given. If the information here does not provide a solution, contact quatech customer service for technical support. Any unauthorized repairs or modifications will v...
