Summary of CPU360
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Quin systems limited cpu360 issue d/e hardware manual issue 4 june 2004 (man530).
Page 2: Quin Systems Limited
Quin systems limited cpu360 issue d/e hardware manual issue 4 april 2004 (man530).
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Copyright notice copyright 2004 quin systems limited. All rights reserved. Reproduction of this document, in part or whole, by any means, without the prior written consent of quin systems limited is strictly prohibited. Hardware issue this manual reflects the issue d/e cpu360 hardware. Important not...
Page 4: Contents
Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 1 contents contents 1 list of figures 3 1. Introduction 4 2. Using the cpu360 5 2.1 processor selection 5 2.2 software control 5 2.3 chip selects 5 2.4 g64 bus address map 7 2.5 i/o address map 8 2.6 68360 internal registers 9...
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Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 2 4. Connections 19 4.1 signal names 19 4.2 power supplies 19 4.3 serial ports 19 4.4 canbus 20 4.5 daughter board 21 4.6 ethernet 21 4.7 g64 bus 22 4.8 general purpose i/o 23 4.9 background debug port 24 4.10 jtag port 24 5. ...
Page 6: List Of Figures
Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 3 list of figures figure 1. Address map 6 figure 2. G64 bus address map 7 figure 3. I/o address map 8 figure 4. Interrupt configuration : j5 14 figure 5. Reset and watchdog : j6 15 figure 6. Processor configuration : j7 15 fig...
Page 7: Introduction
Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 4 1. Introduction this document describes the quin systems cpu360 single board computer. The cpu360 module is a medium performance 32-bit processor module, based around the motorola 68en360 integrated processor. It is designed...
Page 8: Using The Cpu360
Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 5 2. Using the cpu360 2.1 processor selection the 68360 processor config pins select the initial bus size, and whether it is in normal cpu or slave mode. For normal use with the cpu32+ processor core enabled, 32 bit rom chip s...
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Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 6 because the cpu360 module uses the programmable chip select outputs for the rom, ram and i/o areas, the address map is determined by the software at startup. A suggested address map is shown in the following table. Figure 1....
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Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 7 2.4 g64 bus address map the address map within the g64 bus address space is shown below. Note that the g64 data bus is 16 bits wide, but is accessed on the 32 bit processor bus to allow for the optional 68040 cpu. This means...
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Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 8 2.5 i/o address map the address map for the cpu360 i/o devices is shown below. Note that these devices are all 8 bits wide, but are accessed on the 32 bit processor bus to allow for the optional 68040 cpu. This means that th...
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Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 9 2.6 68360 internal registers in the 68360 processor, the internal registers in the sim module and the dual port ram for the communications processor module (cpm) occupy an 8k byte block. This block is located on any 8k byte ...
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Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 10 2.9 communications ports the serial communications ports on the cpu360 are very flexible, and use the cpm communications processor module on the 68en360 cpu. The four ports are allocated as follows to the four serial commun...
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Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 11 2.11 daughter board port serial channel scc2 is connected to daughter board socket xs6. It uses the following port pins. Pa2 rxd2 pa3 txd2 pc1 rts2 pc6 cts2 pc7 cd2 pa10 tclk2 pa11 rclk2 pb4 mode0 pb5 mode1 the function of ...
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Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 12 2.12 serial ports the two standard serial ports use programmable rs-232/485 transceivers. These are controlled by output port signals from the processor, and need to be set up appropriately by the system software. Port b us...
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Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 13 2.13 serial eeprom the following port pins are used for the serial eeprom device. This is normally an spi compatible device, a xicor x25040, having a capacity of 4k bits (512 × 8). Pb0 /spisel serial eeprom enable pb1 spicl...
Page 17: Configuration
Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 14 3. Configuration 3.1 eprom/flash pin 31 : j1 j1 selects the signal connected to pin 31 of the eprom or flash rom devices in sockets ic3-6. For 27c020 or similar eproms (256k × 8), link pins 1 and 2 only. For 27c040 eproms (...
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Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 15 3.6 reset and watchdog : j6 jumper j6 sets up options for the hardware watchdog and reset device. Link pins 1 and 2 to give a manual reset signal to the processor. Link pins 3 and 4 to enable the external hardware watchdog....
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Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 16 3.8 cio clock frequency : j8 jumper j8 sets the z8536 cio peripheral clock frequency as a power of 2 division of the main processor clock. The normal configuration is for a cio clock of 6mhz from a main processor clock o f ...
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Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 17 3.9 serial port a override : j9 the serial ports on the cpu360 module are configured by the software for rs-232 or rs-485 as required, to reduce the number of jumpers that need to be configured by the customer for different...
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Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 18 3.12 jumper locations figure 11. Jumper locations cpu360 module - component side s2 top bottom s1 p1 p2 j9 j5 j8 j4 j6 1 1 1 s5 s6 s4 s3 j2 1 j1 1 j3 1 1 j7 1 p3 1 j11 1 p4 1 j1 1.
Page 22: Connections
Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 19 4. Connections 4.1 signal names on all signals, a ‘/’ prefix is used to denote an inverted or active low signal. For example, the /vpa signal is the active low valid peripheral address signal on the g64 bus. 4.2 power suppl...
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Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 20 4.4 canbus the cpu360 has two double 9 way d plugs and sockets for two separate canbus interfaces. Optional software will allow multiple pts systems to be linked together via canbus. This will support motor synchronisation ...
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Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 21 4.5 daughter board two additional 9 way d sockets are fitted to the cpu360 in position s3. These are provided for use by any optional daughter board. The lower d socket connects to daughter board socket xs5, and the upper d...
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Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 22 4.7 g64 bus the connections to the g64 bus (p1) are given in this table. Signal pin signal pin 0v supply gnd 1a 0v supply gnd 1b address line a0 2a address line a8 2b address line a1 3a address line a9 3b address line a2 4a...
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Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 23 4.8 general purpose i/o the general purpose input/output connections on plug p2 are given here. Signal pin signal pin 0v supply gnd 1a 0v supply gnd 1c +5v supply vcc 2a +5v supply vcc 2c port line pa1 3a port line pa0 3c p...
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Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 24 4.9 background debug port the connections on the background debug connector p3 are given here. It is used during software development and testing. 4.10 jtag port the connections on the jtag test connector p4 are given here....
Page 28: Diagnostics And Tests
Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 25 5. Diagnostics and tests the flashboot functions of the cpu360 perform a brief self-test before starting the pts code. Issue e also has features to enable firmware upgrade from the toolkit 2000. 5.1 switch-on self-test the ...
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Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 26 as far as possible the user can upgrade a unit or change mode without needing any deep understanding. The erase function is normally automatic before programming, and the user is given a file already named, so need not know...
Page 30: Index
Issue 4 cpu360 hardware manual copyright © 2004 quin systems ltd page 27 index 68040 processor 5 , 15 a address map g64 bus 7 i/o 8 memory 6 b background debug port 24 battery configuration 15 board layout 18 burst cycles 14 c canbus 13 connections 20 network power supply 13 canbus interrupt 17 chip...
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Issue 4 cpu360 hardware manual copyright © 2004 quin systems limited page 28 profibus 13 programmable chip selects 5 r reset configuration 15 rs-232 12 rs-485 12 s self-test 25 serial eeprom 13 serial eeprom write protect 14 serial port a override 17 serial port connections 19 serial port 12 signal ...