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ST STM32F101 series Reference Manual

Manual is about: advanced ARM-based 32-bit MCUs

Summary of STM32F101 series

  • Page 1

    June 2014 docid13902 rev 15 1/1128 rm0008 reference manual stm32f101xx, stm32f102xx, stm32f103xx, stm32f105xx and stm32f107xx advanced arm ® -based 32-bit mcus introduction this reference manual targets application developers. It provides complete information on how to use the stm32f101xx, stm32f102...

  • Page 2: Contents

    Docid13902 rev 15 2/1128 rm0008 contents 26 contents 1 overview of the manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2 documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.1 list of abbreviations for registers . . . . ...

  • Page 3

    Contents rm0008 3/1128 docid13902 rev 15 5.2.2 programmable voltage detector (pvd) . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.3 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.3.1 slowing down system clocks . . . . . . . . . . . . ...

  • Page 4

    Docid13902 rev 15 4/1128 rm0008 contents 26 7.2.4 lse clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.2.5 lsi clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.2.6 system clock (sysclk...

  • Page 5

    Contents rm0008 5/1128 docid13902 rev 15 8.3.1 clock control register (rcc_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 8.3.2 clock configuration register (rcc_cfgr) . . . . . . . . . . . . . . . . . . . . . 134 8.3.3 clock interrupt register (rcc_cir) . . . . . . . . . . . . . ...

  • Page 6

    Docid13902 rev 15 6/1128 rm0008 contents 26 9.3.2 using osc_in/osc_out pins as gpio ports pd0/pd1 . . . . . . . . . . 175 9.3.3 can1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 9.3.4 can2 alternate function remapping . . . . . . . . . . . . . . . . . . . . ...

  • Page 7

    Contents rm0008 7/1128 docid13902 rev 15 10.3.6 pending register (exti_pr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 10.3.7 exti register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 11 analog-to-digital converter (adc) . . . . . ....

  • Page 8

    Docid13902 rev 15 8/1128 rm0008 contents 26 11.12.2 adc control register 1 (adc_cr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 11.12.3 adc control register 2 (adc_cr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 11.12.4 adc sample time register 1 (adc_smpr1) . . . . . ....

  • Page 9

    Contents rm0008 9/1128 docid13902 rev 15 12.4.9 simultaneous trigger with different lfsr generation . . . . . . . . . . . . . 263 12.4.10 simultaneous trigger with same triangle generation . . . . . . . . . . . . . . 263 12.4.11 simultaneous trigger with different triangle generation . . . . . . . ....

  • Page 10

    Docid13902 rev 15 10/1128 rm0008 contents 26 13.4 dma registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 13.4.1 dma interrupt status register (dma_isr) . . . . . . . . . . . . . . . . . . . . . . 284 13.4.2 dma interrupt flag clear register (dma_i...

  • Page 11

    Contents rm0008 11/1128 docid13902 rev 15 14.4 tim1&tim8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 14.4.1 tim1&tim8 control register 1 (timx_cr1) . . . . . . . . . . . . . . . . . . . . . 333 14.4.2 tim1&tim8 control register 2 (timx_cr2) . . . . . ....

  • Page 12

    Docid13902 rev 15 12/1128 rm0008 contents 26 15.3.11 clearing the ocxref signal on an external event . . . . . . . . . . . . . . . 384 15.3.12 encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 15.3.13 timer input xor function . . . . . . . . . . . . ....

  • Page 13

    Contents rm0008 13/1128 docid13902 rev 15 16.3.5 input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 16.3.6 pwm input mode (only for tim9/12) . . . . . . . . . . . . . . . . . . . . . . . . . . 429 16.3.7 forced output mode . . . . . . . . . . . . . ....

  • Page 14

    Docid13902 rev 15 14/1128 rm0008 contents 26 17 basic timers (tim6&tim7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 17.1 tim6&tim7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 17.2 tim6&tim7 main features . . . . . . . . . ...

  • Page 15

    Contents rm0008 15/1128 docid13902 rev 15 19 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 19.1 iwdg introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 19.2 iwdg main features . . . . . . . . . . . . . . . ...

  • Page 16

    Docid13902 rev 15 16/1128 rm0008 contents 26 21.5.1 external memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 21.5.2 supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 506 21.5.3 general timing rules . . . . . . . . . . . . . . . ....

  • Page 17

    Contents rm0008 17/1128 docid13902 rev 15 22.4.13 sd i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 22.4.14 commands and responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 22.5 response formats . . . . . . . . . . . ....

  • Page 18

    Docid13902 rev 15 18/1128 rm0008 contents 26 22.9.14 sdio fifo counter register (sdio_fifocnt) . . . . . . . . . . . . . . . . . . 610 22.9.15 sdio data fifo register (sdio_fifo) . . . . . . . . . . . . . . . . . . . . . . . . 611 22.9.16 sdio register map . . . . . . . . . . . . . . . . . . . . . ....

  • Page 19

    Contents rm0008 19/1128 docid13902 rev 15 24.5.3 loop back combined with silent mode . . . . . . . . . . . . . . . . . . . . . . . . . 651 24.6 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 24.7 bxcan functional description . . . . . . . ....

  • Page 20

    Docid13902 rev 15 20/1128 rm0008 contents 26 25.4.1 i 2 s general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 25.4.2 supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 25.4.3 clock generator . . . . . . . . . ...

  • Page 21

    Contents rm0008 21/1128 docid13902 rev 15 26.6.1 i 2 c control register 1 (i2c_cr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 26.6.2 i 2 c control register 2 (i2c_cr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 26.6.3 i 2 c own address register 1 (i2c_oar1) . ....

  • Page 22

    Docid13902 rev 15 22/1128 rm0008 contents 26 27.6.5 control register 2 (usart_cr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816 27.6.6 control register 3 (usart_cr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 27.6.7 guard time and prescaler register (usart_gtpr) ....

  • Page 23

    Contents rm0008 23/1128 docid13902 rev 15 28.12 host fifo architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 28.12.1 host rx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 28.12.2 host tx fifos . . . . . . . ...

  • Page 24

    Docid13902 rev 15 24/1128 rm0008 contents 26 29.4.2 media-independent interface: mii . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966 29.4.3 reduced media-independent interface: rmii . . . . . . . . . . . . . . . . . . . 968 29.4.4 mii/rmii selection . . . . . . . . . . . . . . . . . . . ...

  • Page 25

    Contents rm0008 25/1128 docid13902 rev 15 31.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068 31.2 reference arm® documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070 31.3 swj debug port (serial wire and jtag) . . ....

  • Page 26

    Docid13902 rev 15 26/1128 rm0008 contents 26 31.15.4 configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090 31.16 mcu debug component (dbgmcu) . . . . . . . . . . . . . . . . . . . . . . . . . . 1090 31.16.1 debug support for low-power modes . . . . . . . ...

  • Page 27: List of Tables

    List of tables rm0008 27/1128 docid13902 rev 15 list of tables table 1. Sections related to each stm32f10xxx product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 2. Sections related to each peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

  • Page 28

    Docid13902 rev 15 28/1128 rm0008 list of tables 31 table 49. Tim11 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 50. Tim13 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

  • Page 29

    List of tables rm0008 29/1128 docid13902 rev 15 table 100. Nor/psram bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 table 101. External memory address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

  • Page 30

    Docid13902 rev 15 30/1128 rm0008 list of tables 31 table 151. Erase size field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 table 152. Erase timeout field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 31

    List of tables rm0008 31/1128 docid13902 rev 15 table 202. Host-mode control and status registers (csrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847 table 203. Device-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848...

  • Page 32: List of Figures

    Docid13902 rev 15 32/1128 rm0008 list of figures 39 list of figures figure 1. System architecture (low-, medium-, xl-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 2. System architecture in connectivity line devices. . . . . . . . . . . . . . . . . . . . . . . . . . . ....

  • Page 33

    List of figures rm0008 33/1128 docid13902 rev 15 figure 49. Dma block diagram in low-, medium- high- and xl-density devices . . . . . . . . . . . . . . . . 275 figure 50. Dma1 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 figu...

  • Page 34

    Docid13902 rev 15 34/1128 rm0008 list of figures 39 figure 99. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 332 figure 100. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

  • Page 35

    List of figures rm0008 35/1128 docid13902 rev 15 figure 151. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 figure 152. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424...

  • Page 36

    Docid13902 rev 15 36/1128 rm0008 list of figures 39 figure 199. Asynchronous wait during a read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 figure 200. Asynchronous wait during a write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

  • Page 37

    List of figures rm0008 37/1128 docid13902 rev 15 discontinuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706 figure 246. Transmission using dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 38

    Docid13902 rev 15 38/1128 rm0008 list of figures 39 figure 297. Reception using dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807 figure 298. Hardware flow control between two usarts . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

  • Page 39

    List of figures rm0008 39/1128 docid13902 rev 15 figure 349. System time update using the fine correction method. . . . . . . . . . . . . . . . . . . . . . . . . . . 997 figure 350. Ptp trigger output to tim2 itr1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999 fig...

  • Page 40: Overview of The Manual

    Docid13902 rev 15 40/1128 rm0008 overview of the manual 46 1 overview of the manual legend for table 1 : the section in each row applies to products in columns marked with “ • " table 1. Sections related to each stm32f10xxx product l o w-de nsity stm32 f 1 01xx med iu m -d ens ity st m3 2f1 01x x hi...

  • Page 41

    Overview of the manual rm0008 41/1128 docid13902 rev 15 section 11: analog-to- digital converter (adc) • • • • • • • • • • section 12: digital-to- analog converter (dac) • • • • section 14: advanced- control timers (tim1&tim8) • • • • • • section 15: general- purpose timers (tim2 to tim5) • • • • • ...

  • Page 42

    Docid13902 rev 15 42/1128 rm0008 overview of the manual 46 note: available only on xl-density devices. Section 24: controller area network (bxcan) · · · · · section 25: serial peripheral interface (spi) • • • • • • • • • • section 26: inter- integrated circuit (i2c) interface • • • • • • • • • • sec...

  • Page 43

    Overview of the manual rm0008 43/1128 docid13902 rev 15 legend for table 2 : • the section in this row must be read when using the peripherals in columns marked with “ • " the section in this row can optionally be read when using the peripherals in columns marked with “ " table 2. Sections related t...

  • Page 44

    Docid13902 rev 15 44/1128 rm0008 overview of the manual 46 section 9: general- purpose and alternate- function i/os (gpios and afios)  • • • • • • à • • • • • • • • • • • section 10: interrupts and events section 13: direct memory access controller (dma) section 11: analog-to- digital converter (ad...

  • Page 45

    Overview of the manual rm0008 45/1128 docid13902 rev 15 section 19: independent watchdog (iwdg) · section 20: window watchdog (wwdg) · section 21: flexible static memory controller (fsmc) · section 1: secure digital input/output interface (sdio) · section 23: universal serial bus full-speedÂ...

  • Page 46

    Docid13902 rev 15 46/1128 rm0008 overview of the manual 46 section 28: usb on- the-go full-speed (otg_fs) · section 29: ethernet (eth): media access control (mac) with dma controller · section 30: device electronic signature section 31: debug support (dbg) table 2. Sections related to each periphera...

  • Page 47: 2 Documentation

    Documentation conventions rm0008 47/1128 docid13902 rev 15 2 documentation conventions 2.1 list of abbreviations for registers the following abbreviations are used in register descriptions: 2.2 glossary • low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the fla...

  • Page 48: Memory and Bus Architecture

    Docid13902 rev 15 48/1128 rm0008 memory and bus architecture 63 3 memory and bus architecture 3.1 system architecture in low-, medium-, high- and xl-density devices, the main system consists of: • four masters: – cortex ® -m3 core dcode bus (d-bus) and system bus (s-bus) – gp-dma1 & 2 (general-purpo...

  • Page 49

    Memory and bus architecture rm0008 49/1128 docid13902 rev 15 in connectivity line devices the main system consists of: • five masters: – cortex ® -m3 core dcode bus (d-bus) and system bus (s-bus) – gp-dma1 & 2 (general-purpose dma) – ethernet dma • three slaves: – internal sram – internal flash memo...

  • Page 50: 3.2 Memory

    Docid13902 rev 15 50/1128 rm0008 memory and bus architecture 63 dcode bus this bus connects the dcode bus (literal load and debug access) of the cortex ® -m3 core to the flash memory data interface. System bus this bus connects the system bus of the cortex ® -m3 core (peripherals bus) to a busmatrix...

  • Page 51: 3.3 Memory

    Memory and bus architecture rm0008 51/1128 docid13902 rev 15 3.3 memory map see the datasheet corresponding to your device for a comprehensive diagram of the memory map. Table 3 gives the boundary addresses of the peripherals available in all stm32f10xxx devices. Table 3. Register boundary addresses...

  • Page 52

    Docid13902 rev 15 52/1128 rm0008 memory and bus architecture 63 0x4001 5800 - 0x4001 7fff reserved apb2 0x4001 5400 - 0x4001 57ff tim11 timer section 16.5.10 on page 459 0x4001 5000 - 0x4001 53ff tim10 timer section 16.5.10 on page 459 0x4001 4c00 - 0x4001 4fff tim9 timer section 16.4.13 on page 449...

  • Page 53

    Memory and bus architecture rm0008 53/1128 docid13902 rev 15 0x4000 7800 - 0x4000 ffff reserved apb1 0x4000 7400 - 0x4000 77ff dac section 12.5.14 on page 272 0x4000 7000 - 0x4000 73ff power control pwr section 5.4.3 on page 80 0x4000 6c00 - 0x4000 6fff backup registers (bkp) section 6.4.5 on page 8...

  • Page 54

    Docid13902 rev 15 54/1128 rm0008 memory and bus architecture 63 3.3.1 embedded sram the stm32f10xxx features up to 96 kbytes of static sram. It can be accessed as bytes, half-words (16 bits) or full words (32 bits). The sram start address is 0x2000 0000. 3.3.2 bit banding the cortex ® -m3 memory map...

  • Page 55

    Memory and bus architecture rm0008 55/1128 docid13902 rev 15 3.3.3 embedded flash memory the high-performance flash memory module has the following key features: • for xl-density devices: density of up to 1 mbyte with dual bank architecture for read- while-write (rww) capability: – bank 1: fixed siz...

  • Page 56

    Docid13902 rev 15 56/1128 rm0008 memory and bus architecture 63 information block system memory 0x1fff f000 - 0x1fff f7ff 2 kbytes option bytes 0x1fff f800 - 0x1fff f80f 16 flash memory interface registers flash_acr 0x4002 2000 - 0x4002 2003 4 flash_keyr 0x4002 2004 - 0x4002 2007 4 flash_optkeyr 0x4...

  • Page 57

    Memory and bus architecture rm0008 57/1128 docid13902 rev 15 table 6. Flash module organization (high-density devices) block name base addresses size (bytes) main memory page 0 0x0800 0000 - 0x0800 07ff 2 kbytes page 1 0x0800 0800 - 0x0800 0fff 2 kbytes page 2 0x0800 1000 - 0x0800 17ff 2 kbytes page...

  • Page 58

    Docid13902 rev 15 58/1128 rm0008 memory and bus architecture 63 flash memory interface registers flash_acr 0x4002 2000 - 0x4002 2003 4 flash_keyr 0x4002 2004 - 0x4002 2007 4 flash_optkeyr 0x4002 2008 - 0x4002 200b 4 flash_sr 0x4002 200c - 0x4002 200f 4 flash_cr 0x4002 2010 - 0x4002 2013 4 flash_ar 0...

  • Page 59

    Memory and bus architecture rm0008 59/1128 docid13902 rev 15 note: for further information on the flash memory interface registers, please refer to the: “stm32f10xxx xl-density flash programming manual” (pm0068) for xl-density devices “stm32f10xxx flash programming manual” (pm0075) for other devices...

  • Page 60

    Docid13902 rev 15 60/1128 rm0008 memory and bus architecture 63 used only with a low-frequency clock of 8 mhz or less. It can be generated from the hsi or the hse but not from the pll. The prefetch buffer must be kept on when using a prescaler different from 1 on the ahb clock. The prefetch buffer m...

  • Page 61: 3.4 Boot

    Memory and bus architecture rm0008 61/1128 docid13902 rev 15 flash access control register (flash_acr) address offset: 0x00 reset value: 0x0000 0030 3.4 boot configuration in the stm32f10xxx, 3 different boot modes can be selected through boot[1:0] pins as shown in table 9 . 31 30 29 28 27 26 25 24 ...

  • Page 62

    Docid13902 rev 15 62/1128 rm0008 memory and bus architecture 63 the values on the boot pins are latched on the 4th rising edge of sysclk after a reset. It is up to the user to set the boot1 and boot0 pins after reset to select the required boot mode. The boot pins are also re-sampled when exiting fr...

  • Page 63

    Memory and bus architecture rm0008 63/1128 docid13902 rev 15 the usart peripheral operates with the internal 8 mhz oscillator (hsi). The can and usb otg fs, however, can only function if an external 8 mhz, 14.7456 mhz or 25 mhz clock (hse) is present. Note: for further details, please refer to an260...

  • Page 64: Crc Calculation Unit

    Docid13902 rev 15 64/1128 rm0008 crc calculation unit 66 4 crc calculation unit low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102xx and stm32f103xx microc...

  • Page 65: 4.3

    Crc calculation unit rm0008 65/1128 docid13902 rev 15 4.3 crc functional description the crc calculation unit mainly consists of a single 32-bit data register, which: • is used as an input register to enter new data in the crc calculator (when writing into the register) • holds the result of the pre...

  • Page 66

    Docid13902 rev 15 66/1128 rm0008 crc calculation unit 66 4.4.3 control register (crc_cr) address offset: 0x08 reset value: 0x0000 0000 4.4.4 crc register map the following table the crc register map and reset values. Bits 31:8 reserved, must be kept at reset value. Bits 7:0 general-purpose 8-bit dat...

  • Page 67: Power Control (Pwr)

    Power control (pwr) rm0008 67/1128 docid13902 rev 15 5 power control (pwr) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontro...

  • Page 68

    Docid13902 rev 15 68/1128 rm0008 power control (pwr) 80 figure 4. Power supply overview 1. V dda and v ssa must be connected to v dd and v ss , respectively. 5.1.1 independent a/d and d/a converter supply and reference voltage to improve conversion accuracy, the adc and the dac have an independent p...

  • Page 69

    Power control (pwr) rm0008 69/1128 docid13902 rev 15 5.1.2 battery backup domain to retain the content of the backup registers and supply the rtc function when v dd is turned off, v bat pin can be connected to an optional standby voltage supplied by a battery or by another source. The v bat pin powe...

  • Page 70: 5.2 Power

    Docid13902 rev 15 70/1128 rm0008 power control (pwr) 80 5.1.3 voltage regulator the voltage regulator is always enabled after reset. It works in three different modes depending on the application modes. • in run mode, the regulator supplies full power to the 1.8 v domain (core, memories and digital ...

  • Page 71

    Power control (pwr) rm0008 71/1128 docid13902 rev 15 pvd output interrupt can be generated when v dd /v dda drops below the pvd threshold and/or when v dd /v dda rises above the pvd threshold depending on exti line16 rising/falling edge configuration. As an example the service routine could perform ...

  • Page 72: 5.3 Low-Power

    Docid13902 rev 15 72/1128 rm0008 power control (pwr) 80 5.3 low-power modes by default, the microcontroller is in run mode after a system or a power reset. Several low- power modes are available to save power when the cpu does not need to be kept running, for example when waiting for an external eve...

  • Page 73

    Power control (pwr) rm0008 73/1128 docid13902 rev 15 5.3.2 peripheral clock gating in run mode, the hclk and pclkx for individual peripherals and memories can be stopped at any time to reduce power consumption. To further reduce power consumption in sleep mode the peripheral clocks can be disabled p...

  • Page 74

    Docid13902 rev 15 74/1128 rm0008 power control (pwr) 80 5.3.4 stop mode the stop mode is based on the cortex ® -m3 deepsleep mode combined with peripheral clock gating. The voltage regulator can be configured either in normal or low-power mode. In stop mode, all clocks in the 1.8 v domain are stoppe...

  • Page 75

    Power control (pwr) rm0008 75/1128 docid13902 rev 15 section 19.3: iwdg functional description in section 19: independent watchdog (iwdg) . • real-time clock (rtc): this is configured by the rtcen bit in the backup domain control register (rcc_bdcr) • internal rc oscillator (lsi rc): this is configu...

  • Page 76

    Docid13902 rev 15 76/1128 rm0008 power control (pwr) 80 5.3.5 standby mode the standby mode allows to achieve the lowest power consumption. It is based on the cortex ® -m3 deepsleep mode, with the voltage regulator disabled. The 1.8 v domain is consequently powered off. The pll, the hsi oscillator a...

  • Page 77: 5.4 Power

    Power control (pwr) rm0008 77/1128 docid13902 rev 15 i/o states in standby mode in standby mode, all i/o pins are high impedance except: • reset pad (still available) • tamper pin if configured for tamper or calibration out • wkup pin, if enabled debug mode by default, the debug connection is lost i...

  • Page 78

    Docid13902 rev 15 78/1128 rm0008 power control (pwr) 80 bits 31:9 reserved, must be kept at reset value.. Bit 8 dbp: disable backup domain write protection. In reset state, the rtc and backup registers are protected against parasitic write access. This bit must be set to enable write access to these...

  • Page 79

    Power control (pwr) rm0008 79/1128 docid13902 rev 15 5.4.2 power control/status register (pwr_csr) address offset: 0x04 reset value: 0x0000 0000 (not reset by wakeup from standby mode) additional apb cycles are needed to read this register versus a standard apb read. 31 30 29 28 27 26 25 24 23 22 21...

  • Page 80

    Docid13902 rev 15 80/1128 rm0008 power control (pwr) 80 5.4.3 pwr register map the following table summarizes the pwr registers. Refer to table 3 on page 51 for the register boundary addresses. Table 16. Pwr register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1...

  • Page 81: 6 Backup

    Backup registers (bkp) rm0008 81/1128 docid13902 rev 15 6 backup registers (bkp) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102xx and stm32f103xx micro...

  • Page 82: 6.3

    Docid13902 rev 15 82/1128 rm0008 backup registers (bkp) 89 6.3 bkp functional description 6.3.1 tamper detection the tamper pin generates a tamper detection event when the pin changes from 0 to 1 or from 1 to 0 depending on the tpal bit in the backup control register (bkp_cr) . A tamper detection ev...

  • Page 83: 6.4 Bkp

    Backup registers (bkp) rm0008 83/1128 docid13902 rev 15 6.4 bkp registers refer to section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 6.4.1 backup data register x (bkp_drx) (x = 1 ..42) ...

  • Page 84

    Docid13902 rev 15 84/1128 rm0008 backup registers (bkp) 89 6.4.3 backup control register (bkp_cr) address offset: 0x30 reset value: 0x0000 0000 note: setting the tpal and tpe bits at the same time is always safe, however resetting both at the same time can generate a spurious tamper event. For this ...

  • Page 85

    Backup registers (bkp) rm0008 85/1128 docid13902 rev 15 6.4.5 bkp register map bkp registers are mapped as 16-bit addressable registers as described in the table below: bits 15:10 reserved, must be kept at reset value. Bit 9 tif:tamper interrupt flag this bit is set by hardware when a tamper event i...

  • Page 86

    Docid13902 rev 15 86/1128 rm0008 backup registers (bkp) 89 0x08 bkp_dr2 reserved d[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0c bkp_dr3 reserved d[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x10 bkp_dr4 reserved d[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x14 bkp_dr5 reserv...

  • Page 87

    Backup registers (bkp) rm0008 87/1128 docid13902 rev 15 0x44 bkp_dr12 reserved d[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x48 bkp_dr13 reserved d[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x4c bkp_dr14 reserved d[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x50 bkp_dr15 reser...

  • Page 88

    Docid13902 rev 15 88/1128 rm0008 backup registers (bkp) 89 0x7c bkp_dr26 reserved d[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x80 bkp_dr27 reserved d[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x84 bkp_dr28 reserved d[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x88 bkp_dr29 re...

  • Page 89

    Backup registers (bkp) rm0008 89/1128 docid13902 rev 15 refer to table 3 on page 51 for the register boundary addresses. 0xb4 bkp_dr40 reserved d[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xb8 bkp_dr41 reserved d[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xbc bkp_dr42 reserved d[15:0...

  • Page 90: Control (Rcc)

    Docid13902 rev 15 90/1128 rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) 122 7 low-, medium-, high- and xl-density reset and clock control (rcc) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 1...

  • Page 91

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 91/1128 docid13902 rev 15 low-power management reset there are two ways to generate a low-power management reset: 1. Reset generated when entering standby mode: this type of reset is enabled by resetting nrst_stdby bit in user ...

  • Page 92: 7.2 Clocks

    Docid13902 rev 15 92/1128 rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) 122 7.1.3 backup domain reset the backup domain has two specific resets that affect only the backup domain (see figure 4 ). A backup domain reset is generated when one of the following events occurs: 1...

  • Page 93

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 93/1128 docid13902 rev 15 figure 8. Clock tree 1. When the hsi is used as a pll clock input, the maximum system clock frequency that can be achieved is 64 mhz. 2. For full details about the internal and external clock source ch...

  • Page 94

    Docid13902 rev 15 94/1128 rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) 122 the timer clock frequencies are automatically fixed by hardware. There are two cases: 1. If the apb prescaler is 1, the timer clock frequencies are set to the same frequency as that of the apb doma...

  • Page 95

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 95/1128 docid13902 rev 15 external source (hse bypass) in this mode, an external clock source must be provided. It can have a frequency of up to 25 mhz. You select this mode by setting the hsebyp and hseon bits in the clock con...

  • Page 96

    Docid13902 rev 15 96/1128 rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) 122 7.2.3 pll the internal pll can be used to multiply the hsi rc output or hse crystal output clock frequency. Refer to figure 8 and clock control register (rcc_cr) . The pll configuration (selection ...

  • Page 97

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 97/1128 docid13902 rev 15 lsi calibration the frequency dispersion of the low speed internal rc (lsi) oscillator can be calibrated to have accurate rtc time base and/or iwdg timeout (when lsi is used as clock source for these p...

  • Page 98

    Docid13902 rev 15 98/1128 rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) 122 7.2.8 rtc clock the rtcclk clock source can be either the hse/128, lse or lsi clocks. This is selected by programming the rtcsel[1:0] bits in the backup domain control register (rcc_bdcr) . This se...

  • Page 99: 7.3 Rcc

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 99/1128 docid13902 rev 15 7.3 rcc registers refer to section 2.1 on page 47 for a list of abbreviations used in register descriptions. 7.3.1 clock control register (rcc_cr) address offset: 0x00 reset value: 0x0000 xx83 where x ...

  • Page 100

    Docid13902 rev 15 100/1128 rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) 122 bit 16 hseon: hse clock enable set and cleared by software. Cleared by hardware to stop the hse oscillator when entering stop or standby mode. This bit cannot be reset if the hse oscillator is use...

  • Page 101

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 101/1128 docid13902 rev 15 7.3.2 clock configuration register (rcc_cfgr) address offset: 0x04 reset value: 0x0000 0000 access: 0 ≤ wait state ≤ 2, word, half-word and byte access 1 or 2 wait states inserted only if the access o...

  • Page 102

    Docid13902 rev 15 102/1128 rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) 122 bits 21:18 pllmul: pll multiplication factor these bits are written by software to define the pll multiplication factor. These bits can be written only when pll is disabled. Caution: the pll outpu...

  • Page 103

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 103/1128 docid13902 rev 15 bits 10:8 ppre1: apb low-speed prescaler (apb1) set and cleared by software to control the division factor of the apb low-speed clock (pclk1). Warning: the software has to set correctly these bits to ...

  • Page 104

    Docid13902 rev 15 104/1128 rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) 122 7.3.3 clock interrupt register (rcc_cir) address offset: 0x08 reset value: 0x0000 0000 access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserv...

  • Page 105

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 105/1128 docid13902 rev 15 bit 11 hserdyie: hse ready interrupt enable set and cleared by software to enable/disable interrupt caused by the external 4-16 mhz oscillator stabilization. 0: hse ready interrupt disabled 1: hse rea...

  • Page 106

    Docid13902 rev 15 106/1128 rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) 122 7.3.4 apb2 peripheral reset register (rcc_apb2rstr) address offset: 0x0c reset value: 0x00000 0000 access: no wait state, word, half-word and byte access bit 2 hsirdyf: hsi ready interrupt flag se...

  • Page 107

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 107/1128 docid13902 rev 15 bit 15 adc3rst: adc3 interface reset set and cleared by software. 0: no effect 1: reset adc3 interface bit 14 usart1rst: usart1 reset set and cleared by software. 0: no effect 1: reset usart1 bit 13 t...

  • Page 108

    Docid13902 rev 15 108/1128 rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) 122 bit 4 iopcrst: io port c reset set and cleared by software. 0: no effect 1: reset io port c bit 3 iopbrst: io port b reset set and cleared by software. 0: no effect 1: reset io port b bit 2 iopars...

  • Page 109

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 109/1128 docid13902 rev 15 7.3.5 apb1 peripheral reset register (rcc_apb1rstr) address offset: 0x10 reset value: 0x0000 0000 access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

  • Page 110

    Docid13902 rev 15 110/1128 rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) 122 bit 20 uart5rst: usart5 reset set and cleared by software. 0: no effect 1: reset usart5 bit 19 uart4rst: usart4 reset set and cleared by software. 0: no effect 1: reset usart4 bit 18 usart3rst: us...

  • Page 111

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 111/1128 docid13902 rev 15 7.3.6 ahb peripheral clock enable register (rcc_ahbenr) address offset: 0x14 reset value: 0x0000 0014 access: no wait state, word, half-word and byte access note: when the peripheral clock is not acti...

  • Page 112

    Docid13902 rev 15 112/1128 rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) 122 7.3.7 apb2 peripheral clock enable register (rcc_apb2enr) address: 0x18 reset value: 0x0000 0000 access: word, half-word and byte access no wait states, except if the access occurs while an access...

  • Page 113

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 113/1128 docid13902 rev 15 reserved tim11 en tim10 en tim9 en reserved rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 adc3 en usart 1en tim8 en spi1 en tim1 en adc2 en adc1 en iopg en iopf en iope en iopd en iopc en iopb en iop...

  • Page 114

    Docid13902 rev 15 114/1128 rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) 122 bit 9 adc1en: adc 1 interface clock enable set and cleared by software. 0: adc 1 interface disabled 1: adc 1 interface clock enabled bit 8 iopgen: io port g clock enable set and cleared by softwar...

  • Page 115

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 115/1128 docid13902 rev 15 7.3.8 apb1 peripheral clock enable register (rcc_apb1enr) address: 0x1c reset value: 0x0000 0000 access: word, half-word and byte access no wait state, except if the access occurs while an access to a...

  • Page 116

    Docid13902 rev 15 116/1128 rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) 122 bit 22 i2c2en: i2c2 clock enable set and cleared by software. 0: i2c2 clock disabled 1: i2c2 clock enabled bit 21 i2c1en: i2c1 clock enable set and cleared by software. 0: i2c1 clock disabled 1: i...

  • Page 117

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 117/1128 docid13902 rev 15 bit 7 tim13en: tim13 timer clock enable set and cleared by software. 0: tim13 clock disabled 1: tim13 clock enabled bit 6 tim12en: tim12 timer clock enable set and cleared by software. 0: tim12 clock ...

  • Page 118

    Docid13902 rev 15 118/1128 rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) 122 7.3.9 backup domain control register (rcc_bdcr) address offset: 0x20 reset value: 0x0000 0000, reset by backup domain reset. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access wait states...

  • Page 119

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 119/1128 docid13902 rev 15 7.3.10 control/status register (rcc_csr) address: 0x24 reset value: 0x0c00 0000, reset by system reset, except reset flags by power reset only. Access: 0 ≤ wait state ≤ 3, word, half-word and byte acc...

  • Page 120

    Docid13902 rev 15 120/1128 rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) 122 bit 31 lpwrrstf: low-power reset flag set by hardware when a low-power management reset occurs. Cleared by writing to the rmvf bit. 0: no low-power management reset occurred 1: low-power managemen...

  • Page 121

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 121/1128 docid13902 rev 15 7.3.11 rcc register map the following table gives the rcc register map and the reset values. Table 18. Rcc register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

  • Page 122

    Docid13902 rev 15 122/1128 rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) 122 refer to table 1 on page 24  for the register boundary addresses. 0x24 rcc_csr lp wrstf wwdg r s t f iwdgrs t f sftrstf porrstf pinrstf reser v ed rmvf reserved lsi r d y lsi o n reset val...

  • Page 123: (Rcc)

    Connectivity line devices: reset and clock control (rcc) rm0008 123/1128 docid13902 rev 15 8 connectivity line devices: reset and clock control (rcc) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medi...

  • Page 124

    Docid13902 rev 15 124/1128 rm0008 connectivity line devices: reset and clock control (rcc) 158 low-power management reset there are two ways to generate a low-power management reset: 1. Reset generated when entering standby mode: this type of reset is enabled by resetting nrst_stdby bit in user opti...

  • Page 125: 8.2 Clocks

    Connectivity line devices: reset and clock control (rcc) rm0008 125/1128 docid13902 rev 15 8.1.3 backup domain reset the backup domain has two specific resets that affect only the backup domain (see figure 4 ). A backup domain reset is generated when one of the following events occurs: 1. Software r...

  • Page 126

    Docid13902 rev 15 126/1128 rm0008 connectivity line devices: reset and clock control (rcc) 158 figure 11. Clock tree 1. When the hsi is used as a pll clock input, the maximum system clock frequency that can be achieved is 36 mhz. 2. For full details about the internal and external clock source chara...

  • Page 127

    Connectivity line devices: reset and clock control (rcc) rm0008 127/1128 docid13902 rev 15 several prescalers allow the configuration of the ahb frequency, the high speed apb (apb2) and the low speed apb (apb1) domains. The maximum frequency of the ahb and the apb2 domains is 72 mhz. The maximum all...

  • Page 128

    Docid13902 rev 15 128/1128 rm0008 connectivity line devices: reset and clock control (rcc) 158 external source (hse bypass) in this mode, an external clock source must be provided. It can have a frequency of up to 50 mhz. You select this mode by setting the hsebyp and hseon bits in the clock control...

  • Page 129

    Connectivity line devices: reset and clock control (rcc) rm0008 129/1128 docid13902 rev 15 calibration rc oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by st for 1% accuracy at t a = 25 °c. After reset,...

  • Page 130

    Docid13902 rev 15 130/1128 rm0008 connectivity line devices: reset and clock control (rcc) 158 external source (lse bypass) in this mode, an external clock source must be provided. It can have a frequency of up to 1 mhz. You select this mode by setting the lsebyp and lseon bits in the backup domain ...

  • Page 131

    Connectivity line devices: reset and clock control (rcc) rm0008 131/1128 docid13902 rev 15 8.2.7 clock security system (css) clock security system can be activated by software. In this case, the clock detector is enabled after the hse oscillator startup delay, and disabled when this oscillator is st...

  • Page 132: 8.3 Rcc

    Docid13902 rev 15 132/1128 rm0008 connectivity line devices: reset and clock control (rcc) 158 8.2.10 clock-out capability the microcontroller clock output (mco) capability allows the clock to be output onto the external mco pin. The configuration registers of the corresponding gpio port must be pro...

  • Page 133

    Connectivity line devices: reset and clock control (rcc) rm0008 133/1128 docid13902 rev 15 bit 27 pll2rdy: pll2 clock ready flag set by hardware to indicate that the pll2 is locked. 0: pll2 unlocked 1: pll2 locked bit 26 pll2on: pll2 enable set and cleared by software to enable pll2. Cleared by hard...

  • Page 134

    Docid13902 rev 15 134/1128 rm0008 connectivity line devices: reset and clock control (rcc) 158 8.3.2 clock configuration register (rcc_cfgr) address offset: 0x04 reset value: 0x0000 0000 access: 0 ≤ wait state ≤ 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs...

  • Page 135

    Connectivity line devices: reset and clock control (rcc) rm0008 135/1128 docid13902 rev 15 bits 31:27 reserved, must be kept at reset value. Bits 26:24 mco[3:0]: microcontroller clock output set and cleared by software. 00xx: no clock 0100: system clock (sysclk) selected 0101: hsi clock selected 011...

  • Page 136

    Docid13902 rev 15 136/1128 rm0008 connectivity line devices: reset and clock control (rcc) 158 bit 16 pllsrc: pll entry clock source set and cleared by software to select pll clock source. This bit can be written only when pll is disabled. 0: hsi oscillator clock / 2 selected as pll input clock 1: c...

  • Page 137

    Connectivity line devices: reset and clock control (rcc) rm0008 137/1128 docid13902 rev 15 8.3.3 clock interrupt register (rcc_cir) address offset: 0x08 reset value: 0x0000 0000 access: no wait state, word, half-word and byte access bits 7:4 hpre[3:0]: ahb prescaler set and cleared by software to co...

  • Page 138

    Docid13902 rev 15 138/1128 rm0008 connectivity line devices: reset and clock control (rcc) 158 bits 31:24 reserved, must be kept at reset value. Bit 23 cssc: clock security system interrupt clear this bit is set by software to clear the cssf flag. 0: no effect 1: clear cssf flag bit 22 pll3rdyc: pll...

  • Page 139

    Connectivity line devices: reset and clock control (rcc) rm0008 139/1128 docid13902 rev 15 bit 11 hserdyie: hse ready interrupt enable set and cleared by software to enable/disable interrupt caused by the external 3-25 mhz oscillator stabilization. 0: hse ready interrupt disabled 1: hse ready interr...

  • Page 140

    Docid13902 rev 15 140/1128 rm0008 connectivity line devices: reset and clock control (rcc) 158 bit 2 hsirdyf: hsi ready interrupt flag set by hardware when the internal high speed clock becomes stable and hsirdyie is set. It is cleared by software setting the hsirdyc bit. 0: no clock ready interrupt...

  • Page 141

    Connectivity line devices: reset and clock control (rcc) rm0008 141/1128 docid13902 rev 15 8.3.4 apb2 peripheral reset register (rcc_apb2rstr) address offset: 0x0c reset value: 0x00000 0000 access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserve...

  • Page 142

    Docid13902 rev 15 142/1128 rm0008 connectivity line devices: reset and clock control (rcc) 158 8.3.5 apb1 peripheral reset register (rcc_apb1rstr) address offset: 0x10 reset value: 0x0000 0000 access: no wait state, word, half-word and byte access bit 4 iopcrst: io port c reset set and cleared by so...

  • Page 143

    Connectivity line devices: reset and clock control (rcc) rm0008 143/1128 docid13902 rev 15 bit 26 can2rst: can2 reset set and cleared by software. 0: no effect 1: reset can2 bit 25 can1rst: can1 reset set and cleared by software. 0: no effect 1: reset can1 bits 24:23 reserved, must be kept at reset ...

  • Page 144

    Docid13902 rev 15 144/1128 rm0008 connectivity line devices: reset and clock control (rcc) 158 bit 11 wwdgrst: window watchdog reset set and cleared by software. 0: no effect 1: reset window watchdog bits 10:6 reserved, must be kept at reset value. Bit 5 tim7rst: timer 7 reset set and cleared by sof...

  • Page 145

    Connectivity line devices: reset and clock control (rcc) rm0008 145/1128 docid13902 rev 15 8.3.6 ahb peripheral clock enable register (rcc_ahbenr) address offset: 0x14 reset value: 0x0000 0014 access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rese...

  • Page 146

    Docid13902 rev 15 146/1128 rm0008 connectivity line devices: reset and clock control (rcc) 158 8.3.7 apb2 peripheral clock enable register (rcc_apb2enr) address: 0x18 reset value: 0x0000 0000 access: word, half-word and byte access no wait states, except if the access occurs while an access to a per...

  • Page 147

    Connectivity line devices: reset and clock control (rcc) rm0008 147/1128 docid13902 rev 15 bit 11 tim1en: tim1 timer clock enable set and cleared by software. 0: tim1 timer clock disabled 1: tim1 timer clock enabled bit 10 adc2en: adc 2 interface clock enable set and cleared by software. 0: adc 2 in...

  • Page 148

    Docid13902 rev 15 148/1128 rm0008 connectivity line devices: reset and clock control (rcc) 158 8.3.8 apb1 peripheral clock enable register (rcc_apb1enr) address: 0x1c reset value: 0x0000 0000 access: word, half-word and byte access no wait state, except if the access occurs while an access to a peri...

  • Page 149

    Connectivity line devices: reset and clock control (rcc) rm0008 149/1128 docid13902 rev 15 bit 21 i2c1en: i2c 1 clock enable set and cleared by software. 0: i2c 1 clock disabled 1: i2c 1 clock enabled bit 20 uart5en: usart 5 clock enable set and cleared by software. 0: usart 5 clock disabled 1: usar...

  • Page 150

    Docid13902 rev 15 150/1128 rm0008 connectivity line devices: reset and clock control (rcc) 158 8.3.9 backup domain control register (rcc_bdcr) address: 0x20 reset value: 0x0000 0000, reset by backup domain reset. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access wait states are inserted in...

  • Page 151

    Connectivity line devices: reset and clock control (rcc) rm0008 151/1128 docid13902 rev 15 bits 31:17 reserved, must be kept at reset value. Bit 16 bdrst: backup domain software reset set and cleared by software. 0: reset not activated 1: resets the entire backup domain bit 15 rtcen: rtc clock enabl...

  • Page 152

    Docid13902 rev 15 152/1128 rm0008 connectivity line devices: reset and clock control (rcc) 158 8.3.10 control/status register (rcc_csr) address: 0x24 reset value: 0x0c00 0000, reset by system reset, except reset flags by power reset only. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access w...

  • Page 153

    Connectivity line devices: reset and clock control (rcc) rm0008 153/1128 docid13902 rev 15 8.3.11 ahb peripheral clock reset register (rcc_ahbrstr) address offset: 0x28 reset value: 0x0000 0000 access: no wait state, word, half-word and byte access bit 24 rmvf: remove reset flag set by software to c...

  • Page 154

    Docid13902 rev 15 154/1128 rm0008 connectivity line devices: reset and clock control (rcc) 158 8.3.12 clock configuration register2 (rcc_cfgr2) address offset: 0x2c reset value: 0x0000 0000 access: no wait state, word, half-word and byte access 7 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reser...

  • Page 155

    Connectivity line devices: reset and clock control (rcc) rm0008 155/1128 docid13902 rev 15 bits 11:8 pll2mul[3:0]: pll2 multiplication factor set and cleared by software to control pll2 multiplication factor. These bits can be written only when pll2 is disabled. 00xx: reserved 010x: reserved 0110: p...

  • Page 156

    Docid13902 rev 15 156/1128 rm0008 connectivity line devices: reset and clock control (rcc) 158 8.3.13 rcc register map the following table gives the rcc register map and the reset values. Bits 3:0 prediv1[3:0]: prediv1 division factor set and cleared by software to select prediv1 division factor. Th...

  • Page 157

    Connectivity line devices: reset and clock control (rcc) rm0008 157/1128 docid13902 rev 15 0x00c rcc_apb2rstr reserved usa r t1rst reser v ed spi 1rst ti m1 r s t adc2rst adc1rst reser v ed io pe rs t iopdrst iopcrst io pb rs t io p a rs t reser v ed afi o rs t reset value 0 0 0 0 0 0 0 0 0 0 0 0x01...

  • Page 158

    Docid13902 rev 15 158/1128 rm0008 connectivity line devices: reset and clock control (rcc) 158 refer to table 3 on page 51 for the register boundary addresses. 0x02c rcc_cfgr2 reserved i2s3src i2s 2 src predi v 1s rc pll3mul [3:0] pll2mul [3:0] prediv2[3: 0] prediv1[3: 0] reset value 0 0 0 0 0 0 0 0...

  • Page 159: And Afios)

    General-purpose and alternate-function i/os (gpios and afios) rm0008 159/1128 docid13902 rev 15 9 general-purpose and alternate-function i/os (gpios and afios) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kb...

  • Page 160

    Docid13902 rev 15 160/1128 rm0008 general-purpose and alternate-function i/os (gpios and afios) 195 figure 13. Basic structure of a standard i/o port bit figure 14. Basic structure of a five-volt tolerant i/o port bit 1. V dd_ft is a potential specific to five-volt tolerant i/os and different from v...

  • Page 161

    General-purpose and alternate-function i/os (gpios and afios) rm0008 161/1128 docid13902 rev 15 9.1.1 general-purpose i/o (gpio) during and just after reset, the alternate functions are not active and the i/o ports are configured in input floating mode (cnfx[1:0]=01b, modex[1:0]=00b). The jtag pins ...

  • Page 162

    Docid13902 rev 15 162/1128 rm0008 general-purpose and alternate-function i/os (gpios and afios) 195 or for reset only gpiox_brr) to select the bits you want to modify. The unselected bits will not be modified. 9.1.3 external interrupt/wakeup lines all ports have external interrupt capability. To use...

  • Page 163

    General-purpose and alternate-function i/os (gpios and afios) rm0008 163/1128 docid13902 rev 15 9.1.7 input configuration when the i/o port is programmed as input: • the output buffer is disabled • the schmitt trigger input is activated • the weak pull-up and pull-down resistors are activated or not...

  • Page 164

    Docid13902 rev 15 164/1128 rm0008 general-purpose and alternate-function i/os (gpios and afios) 195 9.1.8 output configuration when the i/o port is programmed as output: • the output buffer is enabled: – open drain mode: a “0” in the output register activates the n-mos while a “1” in the output regi...

  • Page 165

    General-purpose and alternate-function i/os (gpios and afios) rm0008 165/1128 docid13902 rev 15 9.1.9 alternate function configuration when the i/o port is programmed as alternate function: • the output buffer is turned on in open drain or push-pull configuration • the output buffer is driven by the...

  • Page 166

    Docid13902 rev 15 166/1128 rm0008 general-purpose and alternate-function i/os (gpios and afios) 195 9.1.10 analog configuration when the i/o port is programmed as analog configuration: • the output buffer is disabled. • the schmitt trigger input is de-activated providing zero consumption for every a...

  • Page 167

    General-purpose and alternate-function i/os (gpios and afios) rm0008 167/1128 docid13902 rev 15 table 23. General-purpose timers tim2/3/4/5 tim2/3/4/5 pinout configuration gpio configuration tim2/3/4/5_chx input capture channel x input floating output compare channel x alternate function push-pull t...

  • Page 168

    Docid13902 rev 15 168/1128 rm0008 general-purpose and alternate-function i/os (gpios and afios) 195 table 26. I2s i2s pinout configuration gpio configuration i2sx_ ws master alternate function push-pull slave input floating i2sx_ck master alternate function push-pull slave input floating i2sx_sd tra...

  • Page 169

    General-purpose and alternate-function i/os (gpios and afios) rm0008 169/1128 docid13902 rev 15 the gpio configuration of the adc inputs should be analog. Otg_fs_id host no need if the force host mode is selected by software (fhmod set in the otg_fs_gusbcfg register) device no need if the force devi...

  • Page 170

    Docid13902 rev 15 170/1128 rm0008 general-purpose and alternate-function i/os (gpios and afios) 195 fsmc_nwait fsmc_cd input floating/ input pull-up fsmc_nios16, fsmc_intr fsmc_int[3:2] input floating fsmc_nl fsmc_nbl[1:0] alternate function push-pull fsmc_niord, fsmc_niowr fsmc_nreg alternate funct...

  • Page 171: 9.2 Gpio

    General-purpose and alternate-function i/os (gpios and afios) rm0008 171/1128 docid13902 rev 15 9.2 gpio registers refer to section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 9.2.1 port configuration regis...

  • Page 172

    Docid13902 rev 15 172/1128 rm0008 general-purpose and alternate-function i/os (gpios and afios) 195 9.2.2 port configuration register high (gpiox_crh) (x=a..G) address offset: 0x04 reset value: 0x4444 4444 9.2.3 port input data register (gpiox_idr) (x=a..G) address offset: 0x08h reset value: 0x0000 ...

  • Page 173

    General-purpose and alternate-function i/os (gpios and afios) rm0008 173/1128 docid13902 rev 15 9.2.4 port output data register (gpiox_odr) (x=a..G) address offset: 0x0c reset value: 0x0000 0000 9.2.5 port bit set/reset register (gpiox_bsrr) (x=a..G) address offset: 0x10 reset value: 0x0000 0000 31 ...

  • Page 174

    Docid13902 rev 15 174/1128 rm0008 general-purpose and alternate-function i/os (gpios and afios) 195 9.2.6 port bit reset register (gpiox_brr) (x=a..G) address offset: 0x14 reset value: 0x0000 0000 9.2.7 port configuration lock register (gpiox_lckr) (x=a..G) this register is used to lock the configur...

  • Page 175: 9.3

    General-purpose and alternate-function i/os (gpios and afios) rm0008 175/1128 docid13902 rev 15 9.3 alternate function i/o and debug configuration (afio) to optimize the number of peripherals available for the 64-pin or the 100-pin or the 144-pin package, it is possible to remap some alternate funct...

  • Page 176

    Docid13902 rev 15 176/1128 rm0008 general-purpose and alternate-function i/os (gpios and afios) 195 9.3.3 can1 alternate function remapping the can signals can be mapped on port a, port b or port d as shown in table 34 . For port d, remapping is not possible in devices delivered in 36-, 48- and 64-p...

  • Page 177

    General-purpose and alternate-function i/os (gpios and afios) rm0008 177/1128 docid13902 rev 15 to optimize the number of free gpios during debugging, this mapping can be configured in different ways by programming the swj_cfg[1:0] bits in the af remap and debug i/o configuration register (afio_mapr...

  • Page 178

    Docid13902 rev 15 178/1128 rm0008 general-purpose and alternate-function i/os (gpios and afios) 195 9.3.7 timer alternate function remapping timer 4 channels 1 to 4 can be remapped from port b to port d. Other timer remapping possibilities are listed in table 44 to table 46 . Refer to af remap and d...

  • Page 179

    General-purpose and alternate-function i/os (gpios and afios) rm0008 179/1128 docid13902 rev 15 table 45. Tim2 alternate function remapping alternate function tim2_remap[1: 0] = “00” (no remap) tim2_remap[1: 0] = “01” (partial remap) tim2_remap[1: 0] = “10” (partial remap) (1) 1. Remap not available...

  • Page 180

    Docid13902 rev 15 180/1128 rm0008 general-purpose and alternate-function i/os (gpios and afios) 195 9.3.8 usart alternate function remapping refer to af remap and debug i/o configuration register (afio_mapr) . Table 49. Tim11 remapping (1) 1. Refer to the af remap and debug i/o configuration registe...

  • Page 181

    General-purpose and alternate-function i/os (gpios and afios) rm0008 181/1128 docid13902 rev 15 9.3.9 i2c1 alternate function remapping refer to af remap and debug i/o configuration register (afio_mapr) 9.3.10 spi1 alternate function remapping refer to af remap and debug i/o configuration register (...

  • Page 182

    Docid13902 rev 15 182/1128 rm0008 general-purpose and alternate-function i/os (gpios and afios) 195 table 58. Eth remapping alternate function eth_remap = 0 eth_remap = 1 rx_dv-crs_dv pa7 pd8 rxd0 pc4 pd9 rxd1 pc5 pd10 rxd2 pb0 pd11 rxd3 pb1 pd12.

  • Page 183: 9.4 Afio

    General-purpose and alternate-function i/os (gpios and afios) rm0008 183/1128 docid13902 rev 15 9.4 afio registers refer to section 2.1 on page 47 for a list of abbreviations used in register descriptions. Note: to read/write the afio_evcr, afio_mapr and afio_exticrx registers, the afio clock should...

  • Page 184

    Docid13902 rev 15 184/1128 rm0008 general-purpose and alternate-function i/os (gpios and afios) 195 9.4.2 af remap and debug i/o configuration register (afio_mapr) address offset: 0x04 reset value: 0x0000 0000 memory map and bit definitions for low-, medium- high- and xl-density devices: 31 30 29 28...

  • Page 185

    General-purpose and alternate-function i/os (gpios and afios) rm0008 185/1128 docid13902 rev 15 bits 17 adc1_etrginj_remap:adc 1 external trigger injected conversion remapping set and cleared by software. This bit controls the trigger input connected to adc1 external trigger injected conversion. Whe...

  • Page 186

    Docid13902 rev 15 186/1128 rm0008 general-purpose and alternate-function i/os (gpios and afios) 195 bits 7:6 tim1_remap[1:0]: tim1 remapping these bits are set and cleared by software. They control the mapping of tim1 channels 1 to 4, 1n to 3n, external trigger (etr) and break input (bkin) on the gp...

  • Page 187

    General-purpose and alternate-function i/os (gpios and afios) rm0008 187/1128 docid13902 rev 15 memory map and bit definitions for connectivity line devices: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res. Ptp_p ps_re map tim2it r1_ irema p spi3_ rema p res. Swj_ cfg[2:0] mii_r mii_se l can2_ r...

  • Page 188

    Docid13902 rev 15 188/1128 rm0008 general-purpose and alternate-function i/os (gpios and afios) 195 bit 23 mii_rmii_sel:mii or rmii selection this bit is set and cleared by software. It configures the ethernet mac internally for use with an external mii or rmii phy. 0: configure ethernet mac for con...

  • Page 189

    General-purpose and alternate-function i/os (gpios and afios) rm0008 189/1128 docid13902 rev 15 bits 11:10 tim3_remap[1:0]: tim3 remapping these bits are set and cleared by software. They control the mapping of tim3 channels 1 to 4 on the gpio ports. 00: no remap (ch1/pa6, ch2/pa7, ch3/pb0, ch4/pb1)...

  • Page 190

    Docid13902 rev 15 190/1128 rm0008 general-purpose and alternate-function i/os (gpios and afios) 195 bit 2 usart1_remap: usart1 remapping this bit is set and cleared by software. It controls the mapping of usart1 tx and rx alternate functions on the gpio ports. 0: no remap (tx/pa9, rx/pa10) 1: remap ...

  • Page 191

    General-purpose and alternate-function i/os (gpios and afios) rm0008 191/1128 docid13902 rev 15 9.4.3 external interrupt configuration register 1 (afio_exticr1) address offset: 0x08 reset value: 0x0000 9.4.4 external interrupt configuration register 2 (afio_exticr2) address offset: 0x0c reset value:...

  • Page 192

    Docid13902 rev 15 192/1128 rm0008 general-purpose and alternate-function i/os (gpios and afios) 195 9.4.5 external interrupt configuration register 3 (afio_exticr3) address offset: 0x10 reset value: 0x0000 9.4.6 external interrupt configuration register 4 (afio_exticr4) address offset: 0x14 reset va...

  • Page 193

    General-purpose and alternate-function i/os (gpios and afios) rm0008 193/1128 docid13902 rev 15 9.4.7 af remap and debug i/o configuration register2 (afio_mapr2) address offset: 0x1c reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

  • Page 194: 9.5

    Docid13902 rev 15 194/1128 rm0008 general-purpose and alternate-function i/os (gpios and afios) 195 9.5 gpio and afio register maps refer to table 3 on page 51 for the register boundary addresses. The following tables give the gpio and afio register map and the reset values. Table 59. Gpio register ...

  • Page 195

    General-purpose and alternate-function i/os (gpios and afios) rm0008 195/1128 docid13902 rev 15 refer to table 3 on page 51 for the register boundary addresses. 0x04 afio_mapr connectivity line devices reserved ptp_p ps_ remap t im2i t r1_i remap spi 3_ r e map reserved swj _ cfg [2] swj _ cfg [1] s...

  • Page 196: Interrupts and Events

    Docid13902 rev 15 196/1128 rm0008 interrupts and events 213 10 interrupts and events low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102xx and stm32f103xx m...

  • Page 197

    Interrupts and events rm0008 197/1128 docid13902 rev 15 10.1.2 interrupt and exception vectors table 61 and table 63 are the vector tables for connectivity line and other stm32f10xxx devices, respectively. Table 61. Vector table for connectivity line devices position priority type of priority acrony...

  • Page 198

    Docid13902 rev 15 198/1128 rm0008 interrupts and events 213 10 17 settable exti4 exti line4 interrupt 0x0000_0068 11 18 settable dma1_channel1 dma1 channel1 global interrupt 0x0000_006c 12 19 settable dma1_channel2 dma1 channel2 global interrupt 0x0000_0070 13 20 settable dma1_channel3 dma1 channel3...

  • Page 199

    Interrupts and events rm0008 199/1128 docid13902 rev 15 39 46 settable usart3 usart3 global interrupt 0x0000_00dc 40 47 settable exti15_10 exti line[15:10] interrupts 0x0000_00e0 41 48 settable rtcalarm rtc alarm through exti line interrupt 0x0000_00e4 42 49 settable otg_fs_wkup usb on-the-go fs wak...

  • Page 200

    Docid13902 rev 15 200/1128 rm0008 interrupts and events 213 table 62. Vector table for xl-density devices posit ion priority type of priority acronym description address - - - reserved 0x0000_0000 -3 fixed reset reset 0x0000_0004 -2 fixed nmi nonmaskable interrupt. The rcc clock security system (css...

  • Page 201

    Interrupts and events rm0008 201/1128 docid13902 rev 15 14 21 settable dma1_channel4 dma1 channel4 global interrupt 0x0000_0078 15 22 settable dma1_channel5 dma1 channel5 global interrupt 0x0000_007c 16 23 settable dma1_channel6 dma1 channel6 global interrupt 0x0000_0080 17 24 settable dma1_channel7...

  • Page 202

    Docid13902 rev 15 202/1128 rm0008 interrupts and events 213 41 48 settable rtcalarm rtc alarm through exti line interrupt 0x0000_00e4 42 49 settable usbwakeup usb wakeup from suspend through exti line interrupt 0x0000_00e8 43 50 settable tim8_brk_tim12 tim8 break interrupt and tim12 global interrupt...

  • Page 203

    Interrupts and events rm0008 203/1128 docid13902 rev 15 table 63. Vector table for other stm32f10xxx devices posit ion priority type of priority acronym description address - - - reserved 0x0000_0000 -3 fixed reset reset 0x0000_0004 -2 fixed nmi non maskable interrupt. The rcc clock security system ...

  • Page 204

    Docid13902 rev 15 204/1128 rm0008 interrupts and events 213 13 20 settable dma1_channel3 dma1 channel3 global interrupt 0x0000_0074 14 21 settable dma1_channel4 dma1 channel4 global interrupt 0x0000_0078 15 22 settable dma1_channel5 dma1 channel5 global interrupt 0x0000_007c 16 23 settable dma1_chan...

  • Page 205: 10.2 External

    Interrupts and events rm0008 205/1128 docid13902 rev 15 10.2 external interrupt/event controller (exti) the external interrupt/event controller consists of up to 20 edge detectors in connectivity line devices, or 19 edge detectors in other devices for generating event/interrupt requests. Each input ...

  • Page 206

    Docid13902 rev 15 206/1128 rm0008 interrupts and events 213 10.2.1 main features the exti controller main features are the following: • independent trigger and mask on each interrupt/event line • dedicated status bit for each interrupt line • generation of up to 20 software event/interrupt requests ...

  • Page 207

    Interrupts and events rm0008 207/1128 docid13902 rev 15 resumes from wfe, the peripheral interrupt pending bit and the peripheral nvic irq channel pending bit (in the nvic interrupt clear pending register) have to be cleared. • or configuring an external or internal exti line in event mode. When the...

  • Page 208

    Docid13902 rev 15 208/1128 rm0008 interrupts and events 213 10.2.5 external interrupt/event line mapping the 112 gpios are connected to the 16 external interrupt/event lines in the following manner: figure 21. External interrupt/event gpio mapping 1. To configure the afio_exticrx for the mapping of ...

  • Page 209

    Interrupts and events rm0008 209/1128 docid13902 rev 15 the four other exti lines are connected as follows: • exti line 16 is connected to the pvd output • exti line 17 is connected to the rtc alarm event • exti line 18 is connected to the usb wakeup event • exti line 19 is connected to the ethernet...

  • Page 210: 10.3

    Docid13902 rev 15 210/1128 rm0008 interrupts and events 213 10.3 exti registers refer to section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 10.3.1 interrupt mask register (exti_imr) address offset: 0x00 re...

  • Page 211

    Interrupts and events rm0008 211/1128 docid13902 rev 15 10.3.3 rising trigger selection register (exti_rtsr) address offset: 0x08 reset value: 0x0000 0000 note: the external wakeup lines are edge triggered, no glitches must be generated on these lines. If a rising edge on external interrupt line occ...

  • Page 212

    Docid13902 rev 15 212/1128 rm0008 interrupts and events 213 10.3.5 software interrupt event register (exti_swier) address offset: 0x10 reset value: 0x0000 0000 10.3.6 pending register (exti_pr) address offset: 0x14 reset value: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved swier...

  • Page 213

    Interrupts and events rm0008 213/1128 docid13902 rev 15 10.3.7 exti register map the following table gives the exti register map and the reset values. Bits 19 in all registers, are used in connectivity line devices and is reserved otherwise. Refer to table 3 on page 51 for the register boundary addr...

  • Page 214: 11.1 Adc

    Docid13902 rev 15 214/1128 rm0008 analog-to-digital converter (adc) 252 11 analog-to-digital converter (adc) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32...

  • Page 215: 11.2

    Analog-to-digital converter (adc) rm0008 215/1128 docid13902 rev 15 11.2 adc main features • 12-bit resolution • interrupt generation at end of conversion, end of injected conversion and analog watchdog event • single and continuous conversion modes • scan mode for automatic conversion of channel 0 ...

  • Page 216

    Docid13902 rev 15 216/1128 rm0008 analog-to-digital converter (adc) 252 figure 22. Single adc block diagram 1. Adc3 has regular and injected conversion triggers different from those of adc1 and adc2. 2. Tim8_ch4 and tim8_trgo with their corresponding remap bits exist only in high-density and xl-dens...

  • Page 217

    Analog-to-digital converter (adc) rm0008 217/1128 docid13902 rev 15 table 65. Adc pins name signal type remarks v ref+ input, analog reference positive the higher/positive reference voltage for the adc, 2.4 v ≤ v ref+ ≤ v dda v dda (1) 1. V dda and v ssa have to be connected to v dd and v ss , respe...

  • Page 218

    Docid13902 rev 15 218/1128 rm0008 analog-to-digital converter (adc) 252 11.3.1 adc on-off control the adc can be powered-on by setting the adon bit in the adc_cr2 register. When the adon bit is set for the first time, it wakes up the adc from power down mode. Conversion starts when adon bit is set f...

  • Page 219

    Analog-to-digital converter (adc) rm0008 219/1128 docid13902 rev 15 once the conversion of the selected channel is complete: • if a regular channel was converted: – the converted data is stored in the 16-bit adc_dr register – the eoc (end of conversion) flag is set – and an interrupt is generated if...

  • Page 220

    Docid13902 rev 15 220/1128 rm0008 analog-to-digital converter (adc) 252 11.3.7 analog watchdog the awd analog watchdog status bit is set if the analog voltage converted by the adc is below a low threshold or above a high threshold. These thresholds are programmed in the 12 least significant bits of ...

  • Page 221

    Analog-to-digital converter (adc) rm0008 221/1128 docid13902 rev 15 11.3.9 injected channel management triggered injection to use triggered injection, the jauto bit must be cleared and scan bit must be set in the adc_cr1 register. 1. Start conversion of a group of regular channels either by external...

  • Page 222: 11.4 Calibration

    Docid13902 rev 15 222/1128 rm0008 analog-to-digital converter (adc) 252 11.3.10 discontinuous mode regular group this mode is enabled by setting the discen bit in the adc_cr1 register. It can be used to convert a short sequence of n conversions (n conversions selected in the adc_sqrx registers. The ...

  • Page 223: 11.5 Data

    Analog-to-digital converter (adc) rm0008 223/1128 docid13902 rev 15 (digital word) is calculated for each capacitor, and during all subsequent conversions, the error contribution of each capacitor is removed using this code. Calibration is started by setting the cal bit in the adc_cr2 register. Once...

  • Page 224: 11.6 Channel-By-Channel

    Docid13902 rev 15 224/1128 rm0008 analog-to-digital converter (adc) 252 11.6 channel-by-channel programmable sample time adc samples the input voltage for a number of adc_clk cycles which can be modified us- ing the smp[2:0] bits in the adc_smpr1 and adc_smpr2 registers. Each channel can be sampled ...

  • Page 225

    Analog-to-digital converter (adc) rm0008 225/1128 docid13902 rev 15 table 68. External trigger for injected channels for adc1 and adc2 source connection type jextsel[2:0] tim1_trgo event internal signal from on-chip timers 000 tim1_cc4 event 001 tim2_trgo event 010 tim2_cc1 event 011 tim3_cc4 event ...

  • Page 226: 11.8 Dma

    Docid13902 rev 15 226/1128 rm0008 analog-to-digital converter (adc) 252 the software source trigger events can be generated by setting a bit in a register (swstart and jswstart in adc_cr2). A regular group conversion can be interrupted by an injected trigger. 11.8 dma request since converted regular...

  • Page 227: 11.9

    Analog-to-digital converter (adc) rm0008 227/1128 docid13902 rev 15 11.9 dual adc mode in devices with two adcs or more, dual adc mode can be used (see figure 29 ). In dual adc mode the start of conversion is triggered alternately or simultaneously by the adc1 master to the adc2 slave, depending on ...

  • Page 228

    Docid13902 rev 15 228/1128 rm0008 analog-to-digital converter (adc) 252 figure 29. Dual adc block diagram (1) 1. External triggers are present on adc2 but are not shown for the purposes of this diagram. 2. In some dual adc modes, the adc1 data register (adc1_dr) contains both adc1 and adc2 regular c...

  • Page 229

    Analog-to-digital converter (adc) rm0008 229/1128 docid13902 rev 15 11.9.1 injected simultaneous mode this mode converts an injected channel group. The source of external trigger comes from the injected group mux of adc1 (selected by the jextsel[2:0] bits in the adc1_cr2 register). A simultaneous tr...

  • Page 230

    Docid13902 rev 15 230/1128 rm0008 analog-to-digital converter (adc) 252 figure 31. Regular simultaneous mode on 16 channels 11.9.3 fast interleaved mode this mode can be started only on a regular channel group (usually one channel). The source of external trigger comes from the regular channel mux o...

  • Page 231

    Analog-to-digital converter (adc) rm0008 231/1128 docid13902 rev 15 after an eoc interrupt is generated by adc1 (if enabled through the eocie bit) a 32-bit dma transfer request is generated (if the dma bit is set) which transfers to sram the adc1_dr 32-bit register containing the adc2 converted data...

  • Page 232

    Docid13902 rev 15 232/1128 rm0008 analog-to-digital converter (adc) 252 if the injected discontinuous mode is enabled for both adc1 and adc2: • when the 1st trigger occurs, the first injected channel in adc1 is converted. • when the 2nd trigger arrives, the first injected channel in adc2 are convert...

  • Page 233

    Analog-to-digital converter (adc) rm0008 233/1128 docid13902 rev 15 figure 36. Alternate + regular simultaneous if a trigger occurs during an injected conversion that has interrupted a regular conversion, it will be ignored. Figure 37 shows the behavior in this case (2nd trig is ignored). Figure 37....

  • Page 234: 11.10 Temperature

    Docid13902 rev 15 234/1128 rm0008 analog-to-digital converter (adc) 252 11.10 temperature sensor the temperature sensor can be used to measure the ambient temperature (t a ) of the device. The temperature sensor is internally connected to the adcx_in16 input channel which is used to convert the sens...

  • Page 235: 11.11 Adc

    Analog-to-digital converter (adc) rm0008 235/1128 docid13902 rev 15 reading the temperature to use the sensor: 1. Select the adcx_in16 input channel. 2. Select a sample time of 17.1 µs 3. Set the tsvrefe bit in the adc control register 2 (adc_cr2) to wake up the temperature sensor from power down mo...

  • Page 236: 11.12 Adc

    Docid13902 rev 15 236/1128 rm0008 analog-to-digital converter (adc) 252 11.12 adc registers refer to section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 11.12.1 adc status register (adc_sr) address offset: ...

  • Page 237

    Analog-to-digital converter (adc) rm0008 237/1128 docid13902 rev 15 11.12.2 adc control register 1 (adc_cr1) address offset: 0x04 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved awde n jawde n reserved dualmod[3:0] rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

  • Page 238

    Docid13902 rev 15 238/1128 rm0008 analog-to-digital converter (adc) 252 bit 12 jdiscen: discontinuous mode on injected channels this bit set and cleared by software to enable/disable discontinuous mode on injected group channels 0: discontinuous mode on injected channels disabled 1: discontinuous mo...

  • Page 239

    Analog-to-digital converter (adc) rm0008 239/1128 docid13902 rev 15 11.12.3 adc control register 2 (adc_cr2) address offset: 0x08 reset value: 0x0000 0000 bit 6 awdie: analog watchdog interrupt enable this bit is set and cleared by software to enable/disable the analog watchdog interrupt. 0: analog ...

  • Page 240

    Docid13902 rev 15 240/1128 rm0008 analog-to-digital converter (adc) 252 bits 31:24 reserved, must be kept at reset value. Bit 23 tsvrefe: temperature sensor and v refint enable this bit is set and cleared by software to enable/disable the temperature sensor and v refint channel. In devices with dual...

  • Page 241

    Analog-to-digital converter (adc) rm0008 241/1128 docid13902 rev 15 bit 15 jexttrig: external trigger conversion mode for injected channels this bit is set and cleared by software to enable/disable the external trigger used to start conversion of an injected channel group. 0: conversion on external ...

  • Page 242

    Docid13902 rev 15 242/1128 rm0008 analog-to-digital converter (adc) 252 bit 2 cal: a/d calibration this bit is set by software to start the calibration. It is reset by hardware after calibration is complete. 0: calibration completed 1: enable calibration bit 1 cont: continuous conversion this bit is...

  • Page 243

    Analog-to-digital converter (adc) rm0008 243/1128 docid13902 rev 15 11.12.4 adc sample time register 1 (adc_smpr1) address offset: 0x0c reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved smp17[2:0] smp16[2:0] smp15[2:1] rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6...

  • Page 244

    Docid13902 rev 15 244/1128 rm0008 analog-to-digital converter (adc) 252 11.12.5 adc sample time register 2 (adc_smpr2) address offset: 0x10 reset value: 0x0000 0000 11.12.6 adc injected channel data offset register x (adc_jofrx)(x=1..4) address offset: 0x14-0x20 reset value: 0x0000 0000 31 30 29 28 ...

  • Page 245

    Analog-to-digital converter (adc) rm0008 245/1128 docid13902 rev 15 11.12.7 adc watchdog high threshold register (adc_htr) address offset: 0x24 reset value: 0x0000 0fff 11.12.8 adc watchdog low threshold register (adc_ltr) address offset: 0x28 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 2...

  • Page 246

    Docid13902 rev 15 246/1128 rm0008 analog-to-digital converter (adc) 252 11.12.9 adc regular sequence register 1 (adc_sqr1) address offset: 0x2c reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved l[3:0] sq16[4:1] rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

  • Page 247

    Analog-to-digital converter (adc) rm0008 247/1128 docid13902 rev 15 11.12.10 adc regular sequence register 2 (adc_sqr2) address offset: 0x30 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sq12[4:0] sq11[4:0] sq10[4:1] rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14...

  • Page 248

    Docid13902 rev 15 248/1128 rm0008 analog-to-digital converter (adc) 252 11.12.11 adc regular sequence register 3 (adc_sqr3) address offset: 0x34 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sq6[4:0] sq5[4:0] sq4[4:1] rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 1...

  • Page 249

    Analog-to-digital converter (adc) rm0008 249/1128 docid13902 rev 15 11.12.12 adc injected sequence register (adc_jsqr) address offset: 0x38 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved jl[1:0] jsq4[4:1] rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 jsq4...

  • Page 250

    Docid13902 rev 15 250/1128 rm0008 analog-to-digital converter (adc) 252 11.12.13 adc injected data register x (adc_jdrx) (x= 1..4) address offset: 0x3c - 0x48 reset value: 0x0000 0000 11.12.14 adc regular data register (adc_dr) address offset: 0x4c reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23...

  • Page 251

    Analog-to-digital converter (adc) rm0008 251/1128 docid13902 rev 15 11.12.15 adc register map the following table summarizes the adc registers. Table 72. Adc register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 adc_s...

  • Page 252

    Docid13902 rev 15 252/1128 rm0008 analog-to-digital converter (adc) 252 refer to table 1 on page 24  for the register boundary addresses. 0x2c adc_sqr1 reserved l[3:0] sq16[4:0] 16th conversion in regular sequence bits sq15[4:0] 15th conversion in regular sequence bits sq14[4:0] 14thÂ...

  • Page 253: 12.1 Dac

    Digital-to-analog converter (dac) rm0008 253/1128 docid13902 rev 15 12 digital-to-analog converter (dac) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102...

  • Page 254

    Docid13902 rev 15 254/1128 rm0008 digital-to-analog converter (dac) 272 figure 40. Dac channel block diagram 1. In connectivity line devices, the tim8_trgo trigger is replaced by tim3_trgo . Note: once the dac channelx is enabled, the corresponding gpio pin (pa4 or pa5) is automatically connected to...

  • Page 255: 12.3

    Digital-to-analog converter (dac) rm0008 255/1128 docid13902 rev 15 12.3 dac functional description 12.3.1 dac channel enable each dac channel can be powered on by setting its corresponding enx bit in the dac_cr register. The dac channel is then enabled after a startup time t wakeup . Note: the enx ...

  • Page 256

    Docid13902 rev 15 256/1128 rm0008 digital-to-analog converter (dac) 272 figure 41. Data registers in single dac channel mode • dual dac channels, there are three possibilities: – 8-bit right alignment: data for dac channel1 to be loaded into dac_dhr8rd [7:0] bits (stored into dhr1[11:4] bits) and da...

  • Page 257

    Digital-to-analog converter (dac) rm0008 257/1128 docid13902 rev 15 figure 43. Timing diagram for conversion with trigger disabled ten = 0 12.3.5 dac output voltage digital inputs are converted to output voltages on a linear conversion between 0 and v ref+ . The analog output voltages on each dac ch...

  • Page 258

    Docid13902 rev 15 258/1128 rm0008 digital-to-analog converter (dac) 272 note: tselx[2:0] bit cannot be changed when the enx bit is set. When software trigger is selected, it takes only one apb1 clock cycle for dac_dhrx-to- dac_dorx register transfer. 12.3.7 dma request each dac channel has a dma cap...

  • Page 259

    Digital-to-analog converter (dac) rm0008 259/1128 docid13902 rev 15 figure 45. Dac conversion (sw trigger enabled) with lfsr wave generation note: dac trigger must be enabled for noise generation, by setting the tenx bit in the dac_cr register. 12.3.9 triangle-wave generation it is possible to add a...

  • Page 260: 12.4

    Docid13902 rev 15 260/1128 rm0008 digital-to-analog converter (dac) 272 figure 47. Dac conversion (sw trigger enabled) with triangle wave generation note: dac trigger must be enabled for noise generation, by setting the tenx bit in the dac_cr register. Mampx[3:0] bits must be configured before enabl...

  • Page 261

    Digital-to-analog converter (dac) rm0008 261/1128 docid13902 rev 15 12.4.2 independent trigger with same lfsr generation to configure the dac in this conversion mode, the following sequence is required: • set the two dac channel trigger enable bits ten1 and ten2 • configure different trigger sources...

  • Page 262

    Docid13902 rev 15 262/1128 rm0008 digital-to-analog converter (dac) 272 dac_dor1 (three apb1 clock cycles later). The dac channel1 triangle counter is then updated. When a dac channel2 trigger arrives, the dac channel2 triangle counter, with the same triangle amplitude, is added to the dhr2 register...

  • Page 263

    Digital-to-analog converter (dac) rm0008 263/1128 docid13902 rev 15 12.4.8 simultaneous trigger with same lfsr generation to configure the dac in this conversion mode, the following sequence is required: • set the two dac channel trigger enable bits ten1 and ten2 • configure the same trigger source ...

  • Page 264: 12.5 Dac

    Docid13902 rev 15 264/1128 rm0008 digital-to-analog converter (dac) 272 added to the dhr2 register and the sum is transferred into dac_dor2 (three apb1 clock cycles later). The dac channel2 triangle counter is then updated. 12.4.11 simultaneous trigger with different triangle generation to configure...

  • Page 265

    Digital-to-analog converter (dac) rm0008 265/1128 docid13902 rev 15 bits 31:29 reserved. Bit 28 dmaen2: dac channel2 dma enable this bit is set and cleared by software. 0: dac channel2 dma mode disabled 1: dac channel2 dma mode enabled bit 27:24 mamp2[3:0]: dac channel2 mask/amplitude selector these...

  • Page 266

    Docid13902 rev 15 266/1128 rm0008 digital-to-analog converter (dac) 272 bit 17 boff2: dac channel2 output buffer disable this bit set and cleared by software to enable/disable dac channel2 output buffer. 0: dac channel2 output buffer enabled 1: dac channel2 output buffer disabled bit 16 en2: dac cha...

  • Page 267

    Digital-to-analog converter (dac) rm0008 267/1128 docid13902 rev 15 12.5.2 dac software trigger register (dac_swtrigr) address offset: 0x04 reset value: 0x0000 0000 bit 2 ten1: dac channel1 trigger enable this bit set and cleared by software to enable/disable dac channel1 trigger 0: dac channel1 tri...

  • Page 268

    Docid13902 rev 15 268/1128 rm0008 digital-to-analog converter (dac) 272 12.5.3 dac channel1 12-bit right-aligned data holding register (dac_dhr12r1) address offset: 0x08 reset value: 0x0000 0000 12.5.4 dac channel1 12-bit left aligned data holding register (dac_dhr12l1) address offset: 0x0c reset va...

  • Page 269

    Digital-to-analog converter (dac) rm0008 269/1128 docid13902 rev 15 12.5.6 dac channel2 12-bit right aligned data holding register (dac_dhr12r2) address offset: 0x14 reset value: 0x0000 0000 12.5.7 dac channel2 12-bit left aligned data holding register (dac_dhr12l2) address offset: 0x18 reset value:...

  • Page 270

    Docid13902 rev 15 270/1128 rm0008 digital-to-analog converter (dac) 272 12.5.9 dual dac 12-bit right-aligned data holding register (dac_dhr12rd) address offset: 0x20 reset value: 0x0000 0000 12.5.10 dual dac 12-bit left aligned data holding register (dac_dhr12ld) address offset: 0x24 reset value: 0x...

  • Page 271

    Digital-to-analog converter (dac) rm0008 271/1128 docid13902 rev 15 12.5.11 dual dac 8-bit right aligned data holding register (dac_dhr8rd) address offset: 0x28 reset value: 0x0000 0000 12.5.12 dac channel1 data output register (dac_dor1) address offset: 0x2c reset value: 0x0000 0000 12.5.13 dac cha...

  • Page 272

    Docid13902 rev 15 272/1128 rm0008 digital-to-analog converter (dac) 272 12.5.14 dac register map the following table summarizes the dac registers. Note: refer to table 3 on page 51 for the register boundary addresses. Table 75. Dac register map offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 ...

  • Page 273: 13.1 Dma

    Direct memory access controller (dma) rm0008 273/1128 docid13902 rev 15 13 direct memory access controller (dma) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, s...

  • Page 274

    Docid13902 rev 15 274/1128 rm0008 direct memory access controller (dma) 291 figure 48. Dma block diagram in connectivity line devices &,)4& #h #h #h !Rbiter #ortex - 32!- !(" $-! )#ode $#ode 3ys tem $-! !0" &lash "ridge "ridge #h #h #h !Rbiter !(" $-! !0" aib $-! "us ix $-! $-! 2eset control !$# 53!...

  • Page 275: 13.3

    Direct memory access controller (dma) rm0008 275/1128 docid13902 rev 15 figure 49. Dma block diagram in low-, medium- high- and xl-density devices 1. The dma2 controller is available only in high-density and xl-density devices. 1. Adc3, spi/i2s3, uart4, sdio, tim5, tim6, dac, tim7, tim8 dma requests...

  • Page 276

    Docid13902 rev 15 276/1128 rm0008 direct memory access controller (dma) 291 in summary, each dma transfer consists of three operations: • the loading of data from the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start ...

  • Page 277

    Direct memory access controller (dma) rm0008 277/1128 docid13902 rev 15 transfer addresses (in the current internal peripheral/memory address register) are not accessible by software. If the channel is configured in noncircular mode, no dma request is served after the last transfer (that is once the...

  • Page 278

    Docid13902 rev 15 278/1128 rm0008 direct memory access controller (dma) 291 register. The transfer stops once the dma_cndtrxregister reaches zero. Memory to memory mode may not be used at the same time as circular mode. 13.3.4 programmable data width, data alignment and endians when psize and msize ...

  • Page 279

    Direct memory access controller (dma) rm0008 279/1128 docid13902 rev 15 addressing an ahb peripheral that does not support byte or halfword write operations when the dma initiates an ahb byte or halfword write operation, the data are duplicated on the unused lanes of the hwdata[31:0] bus. So when th...

  • Page 280

    Docid13902 rev 15 280/1128 rm0008 direct memory access controller (dma) 291 13.3.6 interrupts an interrupt can be produced on a half-transfer, transfer complete or transfer error for each dma channel. Separate interrupt enable bits are available for flexibility. Note: in high-density and xl-density ...

  • Page 281

    Direct memory access controller (dma) rm0008 281/1128 docid13902 rev 15 figure 50. Dma1 request mapping fixed hardware priority channel 3 internal hw request 3 high priority low priority peripheral channel 2 hw request 2 channel 1 sw trigger (mem2mem bit) channel 1 en bit hw request 1 channel 4 hw r...

  • Page 282

    Docid13902 rev 15 282/1128 rm0008 direct memory access controller (dma) 291 table 78 lists the dma requests for each channel. Dma2 controller the 5 requests from the peripherals (timx[5,6,7,8], adc3, spi/i2s3, uart4, dac_channel[1,2] and sdio) are simply logically ored before entering the dma2, this...

  • Page 283

    Direct memory access controller (dma) rm0008 283/1128 docid13902 rev 15 figure 51. Dma2 request mapping table 79 lists the dma2 requests for each channel. Table 79. Summary of dma2 requests for each channel peripherals channel 1 channel 2 channel 3 channel 4 channel 5 adc3 (1) adc3 spi/i2s3 spi/i2s3...

  • Page 284: 13.4 Dma

    Docid13902 rev 15 284/1128 rm0008 direct memory access controller (dma) 291 13.4 dma registers refer to section 2.1 on page 47 for a list of abbreviations used in register descriptions. Note: in the following registers, all bits related to channel6 and channel7 are not relevant for dma2 since it has...

  • Page 285

    Direct memory access controller (dma) rm0008 285/1128 docid13902 rev 15 13.4.2 dma interrupt flag clear register (dma_ifcr) address offset: 0x04 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved cteif 7 chtif 7 ctcif7 cgif7 cteif6 chtif6 ctcif6 cgif6 cteif5 chtif5 ctc...

  • Page 286

    Docid13902 rev 15 286/1128 rm0008 direct memory access controller (dma) 291 13.4.3 dma channel x configuration register (dma_ccrx) (x = 1..7, where x = channel number) address offset: 0x08 + 0d20 × (channel number – 1) reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved...

  • Page 287

    Direct memory access controller (dma) rm0008 287/1128 docid13902 rev 15 13.4.4 dma channel x number of data register (dma_cndtrx) (x = 1..7), where x = channel number) address offset: 0x0c + 0d20 × (channel number – 1) reset value: 0x0000 0000 bit 4 dir: data transfer direction this bit is set and c...

  • Page 288

    Docid13902 rev 15 288/1128 rm0008 direct memory access controller (dma) 291 13.4.5 dma channel x peripheral address register (dma_cparx) (x = 1..7), where x = channel number) address offset: 0x10 + 0d20 × (channel number – 1) reset value: 0x0000 0000 this register must not be written when the channe...

  • Page 289

    Direct memory access controller (dma) rm0008 289/1128 docid13902 rev 15 13.4.7 dma register map the following table gives the dma register map and the reset values. Table 80. Dma register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5...

  • Page 290

    Docid13902 rev 15 290/1128 rm0008 direct memory access controller (dma) 291 0x03c dma_cmar3 ma[31:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x040 reserved 0x044 dma_ccr4 reserved mem2me m pl [1:0] m si ze [1 :0] psi ze [1: 0 ] minc pi nc circ dir teie htie tcie e...

  • Page 291

    Direct memory access controller (dma) rm0008 291/1128 docid13902 rev 15 refer to table 3 on page 51 for the register boundary addresses. 0x084 dma_cndtr7 reserved ndt[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x088 dma_cpar7 pa[31:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

  • Page 292: 14 Advanced-Control

    Docid13902 rev 15 292/1128 rm0008 advanced-control timers (tim1&tim8) 359 14 advanced-control timers (tim1&tim8) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, s...

  • Page 293: 14.2

    Advanced-control timers (tim1&tim8) rm0008 293/1128 docid13902 rev 15 14.2 tim1&tim8 main features tim1&tim8 timer features include: • 16-bit up, down, up/down auto-reload counter. • 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock frequency either by any factor ...

  • Page 294

    Docid13902 rev 15 294/1128 rm0008 advanced-control timers (tim1&tim8) 359 figure 52. Advanced-control timer block diagram prescaler autoreload register counter capture/compare 1 register capture/compare 2 register u u u cc1i cc2i etr trigger controller +/- stop, clear or up/down ti1fp1 ti2fp2 itr0 i...

  • Page 295: 14.3

    Advanced-control timers (tim1&tim8) rm0008 295/1128 docid13902 rev 15 14.3 tim1&tim8 functional description 14.3.1 time-base unit the main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. T...

  • Page 296

    Docid13902 rev 15 296/1128 rm0008 advanced-control timers (tim1&tim8) 359 figure 53. Counter timing diagram with prescaler division change from 1 to 2 figure 54. Counter timing diagram with prescaler division change from 1 to 4 14.3.2 counter modes upcounting mode in upcounting mode, the counter cou...

  • Page 297

    Advanced-control timers (tim1&tim8) rm0008 297/1128 docid13902 rev 15 preload registers. Then no update event occurs until the udis bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the ur...

  • Page 298

    Docid13902 rev 15 298/1128 rm0008 advanced-control timers (tim1&tim8) 359 figure 57. Counter timing diagram, internal clock divided by 4 figure 58. Counter timing diagram, internal clock divided by n figure 59. Counter timing diagram, update event when arpe=0 (timx_arr not preloaded) ck_psc 0000 000...

  • Page 299

    Advanced-control timers (tim1&tim8) rm0008 299/1128 docid13902 rev 15 figure 60. Counter timing diagram, update event when arpe=1 (timx_arr preloaded) downcounting mode in downcounting mode, the counter counts from the auto-reload value (content of the timx_arr register) down to 0, then restarts fro...

  • Page 300

    Docid13902 rev 15 300/1128 rm0008 advanced-control timers (tim1&tim8) 359 the following figures show some examples of the counter behavior for different clock frequencies when timx_arr=0x36. Figure 61. Counter timing diagram, internal clock divided by 1 figure 62. Counter timing diagram, internal cl...

  • Page 301

    Advanced-control timers (tim1&tim8) rm0008 301/1128 docid13902 rev 15 figure 64. Counter timing diagram, internal clock divided by n figure 65. Counter timing diagram, update event when repetition counter is not used center-aligned mode (up/down counting) in center-aligned mode, the counter counts f...

  • Page 302

    Docid13902 rev 15 302/1128 rm0008 advanced-control timers (tim1&tim8) 359 the uev update event can be disabled by software by setting the udis bit in the timx_cr1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs u...

  • Page 303

    Advanced-control timers (tim1&tim8) rm0008 303/1128 docid13902 rev 15 figure 67. Counter timing diagram, internal clock divided by 2 figure 68. Counter timing diagram, internal clock divided by 4, timx_arr=0x36 1. Center-aligned mode 2 or 3 is used with an uif on overflow. Figure 69. Counter timing ...

  • Page 304

    Docid13902 rev 15 304/1128 rm0008 advanced-control timers (tim1&tim8) 359 figure 70. Counter timing diagram, update event with arpe=1 (counter underflow) figure 71. Counter timing diagram, update event with arpe=1 (counter overflow) 14.3.3 repetition counter section 14.3.1: time-base unit describes ...

  • Page 305

    Advanced-control timers (tim1&tim8) rm0008 305/1128 docid13902 rev 15 the repetition counter is decremented: • at each counter overflow in upcounting mode, • at each counter underflow in downcounting mode, • at each counter overflow and at each counter underflow in center-aligned mode. Although this...

  • Page 306

    Docid13902 rev 15 306/1128 rm0008 advanced-control timers (tim1&tim8) 359 14.3.4 clock selection the counter clock can be provided by the following clock sources: • internal clock (ck_int) • external clock mode1: external input pin • external clock mode2: external trigger input etr • internal trigge...

  • Page 307

    Advanced-control timers (tim1&tim8) rm0008 307/1128 docid13902 rev 15 for example, to configure the upcounter to count in response to a rising edge on the ti2 input, use the following procedure: 1. Configure channel 2 to detect rising edges on the ti2 input by writing cc2s = ‘01’ in the timx_ccmr1 r...

  • Page 308

    Docid13902 rev 15 308/1128 rm0008 advanced-control timers (tim1&tim8) 359 for example, to configure the upcounter to count each 2 rising edges on etr, use the following procedure: 1. As no filter is needed in this example, write etf[3:0]=0000 in the timx_smcr register. 2. Set the prescaler by writin...

  • Page 309

    Advanced-control timers (tim1&tim8) rm0008 309/1128 docid13902 rev 15 figure 78. Capture/compare channel (example: channel 1 input stage) the output stage generates an intermediate waveform which is then used for reference: ocxref (active high). The polarity acts at the end of the chain. Figure 79. ...

  • Page 310

    Docid13902 rev 15 310/1128 rm0008 advanced-control timers (tim1&tim8) 359 figure 80. Output stage of capture/compare channel (channel 1 to 3) figure 81. Output stage of capture/compare channel (channel 4) the capture/compare block is made of one preload register and one shadow register. Write and re...

  • Page 311

    Advanced-control timers (tim1&tim8) rm0008 311/1128 docid13902 rev 15 the following example shows how to capture the counter value in timx_ccr1 when ti1 input rises. To do this, use the following procedure: • select the active input: timx_ccr1 must be linked to the ti1 input, so write the cc1s bits ...

  • Page 312

    Docid13902 rev 15 312/1128 rm0008 advanced-control timers (tim1&tim8) 359 for example, you can measure the period (in timx_ccr1 register) and the duty cycle (in timx_ccr2 register) of the pwm applied on ti1 using the following procedure (depending on ck_int frequency and prescaler value): • select t...

  • Page 313

    Advanced-control timers (tim1&tim8) rm0008 313/1128 docid13902 rev 15 anyway, the comparison between the timx_ccrx shadow register and the counter is still performed and allows the flag to be set. Interrupt and dma requests can be sent accordingly. This is described in the output compare mode sectio...

  • Page 314

    Docid13902 rev 15 314/1128 rm0008 advanced-control timers (tim1&tim8) 359 figure 83. Output compare mode, toggle on oc1. 14.3.10 pwm mode pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the timx_arr register and a duty cycle determined by the v...

  • Page 315

    Advanced-control timers (tim1&tim8) rm0008 315/1128 docid13902 rev 15 pwm edge-aligned mode • upcounting configuration upcounting is active when the dir bit in the timx_cr1 register is low. Refer to section : upcounting mode on page 296 . In the following example, we consider pwm mode 1. The referen...

  • Page 316

    Docid13902 rev 15 316/1128 rm0008 advanced-control timers (tim1&tim8) 359 figure 85. Center-aligned pwm waveforms (arr=8) hints on using center-aligned mode: • when starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on th...

  • Page 317

    Advanced-control timers (tim1&tim8) rm0008 317/1128 docid13902 rev 15 14.3.11 complementary outputs and dead-time insertion the advanced-control timers (tim1&tim8) can output two complementary signals and manage the switching-off and the switching-on instants of the outputs. This time is generally k...

  • Page 318

    Docid13902 rev 15 318/1128 rm0008 advanced-control timers (tim1&tim8) 359 figure 88. Dead-time waveforms with delay greater than the positive pulse. The dead-time delay is the same for each of the channels and is programmable with the dtg bits in the timx_bdtr register. Refer to section 14.4.18: tim...

  • Page 319

    Advanced-control timers (tim1&tim8) rm0008 319/1128 docid13902 rev 15 must insert a delay (dummy instruction) before reading it correctly. This is because you write the asynchronous signal and read the synchronous signal. When a break occurs (selected level on the break input): • the moe bit is clea...

  • Page 320

    Docid13902 rev 15 320/1128 rm0008 advanced-control timers (tim1&tim8) 359 figure 89. Output behavior in response to a break. Delay ocxref break (moe ocx (ocxn not implemented, ccxp=0, oisx=1) ocx (ocxn not implemented, ccxp=0, oisx=0) ocx (ocxn not implemented, ccxp=1, oisx=1) ocx (ocxn not implemen...

  • Page 321

    Advanced-control timers (tim1&tim8) rm0008 321/1128 docid13902 rev 15 14.3.13 clearing the ocxref signal on an external event the ocxref signal for a given channel can be driven low by applying a high level to the etrf input (ocxce enable bit of the corresponding timx_ccmrx register set to ‘1’). The...

  • Page 322

    Docid13902 rev 15 322/1128 rm0008 advanced-control timers (tim1&tim8) 359 14.3.14 6-step pwm generation when complementary outputs are used on a channel, preload bits are available on the ocxm, ccxe and ccxne bits. The preload bits are transferred to the shadow bits at the com commutation event. Thu...

  • Page 323

    Advanced-control timers (tim1&tim8) rm0008 323/1128 docid13902 rev 15 14.3.15 one-pulse mode one-pulse mode (opm) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. S...

  • Page 324

    Docid13902 rev 15 324/1128 rm0008 advanced-control timers (tim1&tim8) 359 the opm waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • the t delay is defined by the value written in the timx_ccr1 register. • the t pulse is define...

  • Page 325

    Advanced-control timers (tim1&tim8) rm0008 325/1128 docid13902 rev 15 repetition counter, trigger output features continue to work as normal. Encoder mode and external clock mode 2 are not compatible and must not be selected together. In this mode, the counter is modified automatically following the...

  • Page 326

    Docid13902 rev 15 326/1128 rm0008 advanced-control timers (tim1&tim8) 359 figure 93. Example of counter operation in encoder interface mode. Figure 94 gives an example of counter behavior when ti1fp1 polarity is inverted (same configuration as above except cc1p=’1’). Figure 94. Example of encoder in...

  • Page 327

    Advanced-control timers (tim1&tim8) rm0008 327/1128 docid13902 rev 15 14.3.17 timer input xor function the ti1s bit in the timx_cr2 register, allows the input filter of channel 1 to be connected to the output of a xor gate, combining the three input pins timx_ch1, timx_ch2 and timx_ch3. The xor outp...

  • Page 328

    Docid13902 rev 15 328/1128 rm0008 advanced-control timers (tim1&tim8) 359 written after a com event for the next step (this can be done in an interrupt subroutine generated by the rising edge of oc2ref). Figure 95 describes this example. Figure 95. Example of hall sensor interface counter (cnt) trgo...

  • Page 329

    Advanced-control timers (tim1&tim8) rm0008 329/1128 docid13902 rev 15 14.3.19 timx and external trigger synchronization the timx timer can be synchronized with an external trigger in several modes: reset mode, gated mode and trigger mode. Slave mode: reset mode the counter and its prescaler can be r...

  • Page 330

    Docid13902 rev 15 330/1128 rm0008 advanced-control timers (tim1&tim8) 359 slave mode: gated mode the counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when ti1 input is low: • configure the channel 1 to detect low levels on ti1. Co...

  • Page 331

    Advanced-control timers (tim1&tim8) rm0008 331/1128 docid13902 rev 15 slave mode: trigger mode the counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on ti2 input: • configure the channel 2 to detect rising edges...

  • Page 332

    Docid13902 rev 15 332/1128 rm0008 advanced-control timers (tim1&tim8) 359 2. Configure the channel 1 as follows, to detect rising edges on ti: – ic1f=0000: no filter. – the capture prescaler is not used for triggering and does not need to be configured. – cc1s=01 in timx_ccmr1 register to select onl...

  • Page 333: 14.4 Tim1&tim8

    Advanced-control timers (tim1&tim8) rm0008 333/1128 docid13902 rev 15 14.4 tim1&tim8 registers refer to section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 14.4.1 tim1&tim8 control regist...

  • Page 334

    Docid13902 rev 15 334/1128 rm0008 advanced-control timers (tim1&tim8) 359 14.4.2 tim1&tim8 control register 2 (timx_cr2) address offset: 0x04 reset value: 0x0000 bit 2 urs:update request source this bit is set and cleared by software to select the uev event sources. 0: any of the following events ge...

  • Page 335

    Advanced-control timers (tim1&tim8) rm0008 335/1128 docid13902 rev 15 bit 10 ois2: output idle state 2 (oc2 output) refer to ois1 bit bit 9 ois1n: output idle state 1 (oc1n output) 0: oc1n=0 after a dead-time when moe=0 1: oc1n=1 after a dead-time when moe=0 note: this bit can not be modified as lon...

  • Page 336

    Docid13902 rev 15 336/1128 rm0008 advanced-control timers (tim1&tim8) 359 bit 2 ccus:capture/compare control update selection 0: when capture/compare control bits are preloaded (ccpc=1), they are updated by setting the comg bit only 1: when capture/compare control bits are preloaded (ccpc=1), they a...

  • Page 337

    Advanced-control timers (tim1&tim8) rm0008 337/1128 docid13902 rev 15 14.4.3 tim1&tim8 slave mode control register (timx_smcr) address offset: 0x08 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 etp ece etps[1:0] etf[3:0] msm ts[2:0] res. Sms[2:0] rw rw rw rw rw rw rw rw rw rw rw rw res. ...

  • Page 338

    Docid13902 rev 15 338/1128 rm0008 advanced-control timers (tim1&tim8) 359 bits 11:8 etf[3:0]: external trigger filter this bit-field then defines the frequency used to sample etrp signal and the length of the digital filter applied to etrp. The digital filter is made of an event counter in which n e...

  • Page 339

    Advanced-control timers (tim1&tim8) rm0008 339/1128 docid13902 rev 15 14.4.4 tim1&tim8 dma/interrupt enable register (timx_dier) address offset: 0x0c reset value: 0x0000 bits 2:0 sms: slave mode selection when external signals are selected the active edge of the trigger signal (trgi) is linked to th...

  • Page 340

    Docid13902 rev 15 340/1128 rm0008 advanced-control timers (tim1&tim8) 359 bit 12 cc4de: capture/compare 4 dma request enable 0: cc4 dma request disabled 1: cc4 dma request enabled bit 11 cc3de: capture/compare 3 dma request enable 0: cc3 dma request disabled 1: cc3 dma request enabled bit 10 cc2de: ...

  • Page 341

    Advanced-control timers (tim1&tim8) rm0008 341/1128 docid13902 rev 15 14.4.5 tim1&tim8 status register (timx_sr) address offset: 0x10 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved cc4of cc3of cc2of cc1of res. Bif tif comif cc4if cc3if cc2if cc1if uif rc_w0 rc_w0 rc_w0 rc_w0 res....

  • Page 342

    Docid13902 rev 15 342/1128 rm0008 advanced-control timers (tim1&tim8) 359 14.4.6 tim1&tim8 event generation register (timx_egr) address offset: 0x14 reset value: 0x0000 bit 2 cc2if: capture/compare 2 interrupt flag refer to cc1if description bit 1 cc1if: capture/compare 1 interrupt flag if channel c...

  • Page 343

    Advanced-control timers (tim1&tim8) rm0008 343/1128 docid13902 rev 15 bit 6 tg: trigger generation this bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: no action 1: the tif flag is set in timx_sr register. Related interrupt or dma transfer can occur ...

  • Page 344

    Docid13902 rev 15 344/1128 rm0008 advanced-control timers (tim1&tim8) 359 14.4.7 tim1&tim8 capture/compare mode register 1 (timx_ccmr1) address offset: 0x18 reset value: 0x0000 the channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by conf...

  • Page 345

    Advanced-control timers (tim1&tim8) rm0008 345/1128 docid13902 rev 15 bits 6:4 oc1m: output compare 1 mode these bits define the behavior of the output reference signal oc1ref from which oc1 and oc1n are derived. Oc1ref is active high whereas oc1 and oc1n active level depends on cc1p and cc1np bits....

  • Page 346

    Docid13902 rev 15 346/1128 rm0008 advanced-control timers (tim1&tim8) 359 input capture mode bits 15:12 ic2f:input capture 2 filter bits 11:10 ic2psc[1:0]: input capture 2 prescaler bits 9:8 cc2s: capture/compare 2 selection this bit-field defines the direction of the channel (input/output) as well ...

  • Page 347

    Advanced-control timers (tim1&tim8) rm0008 347/1128 docid13902 rev 15 14.4.8 tim1&tim8 capture/compare mode register 2 (timx_ccmr2) address offset: 0x1c reset value: 0x0000 refer to the above ccmr1 register description. Output compare mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 oc4 ce oc4m[2:0] oc4 p...

  • Page 348

    Docid13902 rev 15 348/1128 rm0008 advanced-control timers (tim1&tim8) 359 input capture mode 14.4.9 tim1&tim8 capture/compare enable register (timx_ccer) address offset: 0x20 reset value: 0x0000 bits 15:12 ic4f:input capture 4 filter bits 11:10 ic4psc:input capture 4 prescaler bits 9:8 cc4s: capture...

  • Page 349

    Advanced-control timers (tim1&tim8) rm0008 349/1128 docid13902 rev 15 bit 7 cc2np: capture/compare 2 complementary output polarity refer to cc1np description bit 6 cc2ne: capture/compare 2 complementary output enable refer to cc1ne description bit 5 cc2p: capture/compare 2 output polarity refer to c...

  • Page 350

    Docid13902 rev 15 350/1128 rm0008 advanced-control timers (tim1&tim8) 359 note: the state of the external i/o pins connected to the complementary ocx and ocxn channels depends on the ocx and ocxn channel state and the gpioand afio registers. Table 83. Output control bits for complementary ocx and oc...

  • Page 351

    Advanced-control timers (tim1&tim8) rm0008 351/1128 docid13902 rev 15 14.4.10 tim1&tim8 counter (timx_cnt) address offset: 0x24 reset value: 0x0000 14.4.11 tim1&tim8 prescaler (timx_psc) address offset: 0x28 reset value: 0x0000 14.4.12 tim1&tim8 auto-reload register (timx_arr) address offset: 0x2c r...

  • Page 352

    Docid13902 rev 15 352/1128 rm0008 advanced-control timers (tim1&tim8) 359 14.4.13 tim1&tim8 repetition counter register (timx_rcr) address offset: 0x30 reset value: 0x0000 14.4.14 tim1&tim8 capture/compare register 1 (timx_ccr1) address offset: 0x34 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 ...

  • Page 353

    Advanced-control timers (tim1&tim8) rm0008 353/1128 docid13902 rev 15 14.4.15 tim1&tim8 capture/compare register 2 (timx_ccr2) address offset: 0x38 reset value: 0x0000 14.4.16 tim1&tim8 capture/compare register 3 (timx_ccr3) address offset: 0x3c reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ...

  • Page 354

    Docid13902 rev 15 354/1128 rm0008 advanced-control timers (tim1&tim8) 359 14.4.17 tim1&tim8 capture/compare register 4 (timx_ccr4) address offset: 0x40 reset value: 0x0000 14.4.18 tim1&tim8 break and dead-time register (timx_bdtr) address offset: 0x44 reset value: 0x0000 note: as the bits aoe, bkp, ...

  • Page 355

    Advanced-control timers (tim1&tim8) rm0008 355/1128 docid13902 rev 15 bit 13 bkp: break polarity 0: break input brk is active low 1: break input brk is active high note: this bit can not be modified as long as lock level 1 has been programmed (lock bits in timx_bdtr register). Note: any write operat...

  • Page 356

    Docid13902 rev 15 356/1128 rm0008 advanced-control timers (tim1&tim8) 359 14.4.19 tim1&tim8 dma control register (timx_dcr) address offset: 0x48 reset value: 0x0000 bits 7:0 dtg[7:0]: dead-time generator setup this bit-field defines the duration of the dead-time inserted between the complementary ou...

  • Page 357

    Advanced-control timers (tim1&tim8) rm0008 357/1128 docid13902 rev 15 14.4.20 tim1&tim8 dma address for full transfer (timx_dmar) address offset: 0x4c reset value: 0x0000 example of how to use the dma burst feature in this example the timer dma burst feature is used to update the contents of the ccr...

  • Page 358

    Docid13902 rev 15 358/1128 rm0008 advanced-control timers (tim1&tim8) 359 14.4.21 tim1&tim8 register map tim1&tim8 registers are mapped as 16-bit addressable registers as described in the table below: table 84. Tim1&tim8 register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 ...

  • Page 359

    Advanced-control timers (tim1&tim8) rm0008 359/1128 docid13902 rev 15 refer to table 3 on page 51 for the register boundary addresses. 0x34 timx_ccr1 reserved ccr1[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x38 timx_ccr2 reserved ccr2[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x3c ti...

  • Page 360: 15.1

    Docid13902 rev 15 360/1128 rm0008 general-purpose timers (tim2 to tim5) 417 15 general-purpose timers (tim2 to tim5) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101x...

  • Page 361: 15.2

    General-purpose timers (tim2 to tim5) rm0008 361/1128 docid13902 rev 15 15.2 timx main features general-purpose timx timer features include: • 16-bit up, down, up/down auto-reload counter. • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor be...

  • Page 362: 15.3

    Docid13902 rev 15 362/1128 rm0008 general-purpose timers (tim2 to tim5) 417 figure 100. General-purpose timer block diagram 15.3 timx functional description 15.3.1 time-base unit the main block of the programmable timer is a 16-bit counter with its related auto-reload register. The counter can count...

  • Page 363

    General-purpose timers (tim2 to tim5) rm0008 363/1128 docid13902 rev 15 the auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update...

  • Page 364

    Docid13902 rev 15 364/1128 rm0008 general-purpose timers (tim2 to tim5) 417 figure 102. Counter timing diagram with prescaler division change from 1 to 4 15.3.2 counter modes upcounting mode in upcounting mode, the counter counts from 0 to the auto-reload value (content of the timx_arr register), th...

  • Page 365

    General-purpose timers (tim2 to tim5) rm0008 365/1128 docid13902 rev 15 figure 103. Counter timing diagram, internal clock divided by 1 figure 104. Counter timing diagram, internal clock divided by 2 figure 105. Counter timing diagram, internal clock divided by 4 ck_int 00 cnt_en timer clock = ck_cn...

  • Page 366

    Docid13902 rev 15 366/1128 rm0008 general-purpose timers (tim2 to tim5) 417 figure 106. Counter timing diagram, internal clock divided by n figure 107. Counter timing diagram, update event when arpe=0 (timx_arr not preloaded) timer clock = ck_cnt counter register 00 1f 20 update interrupt flag (uif)...

  • Page 367

    General-purpose timers (tim2 to tim5) rm0008 367/1128 docid13902 rev 15 figure 108. Counter timing diagram, update event when arpe=1 (timx_arr preloaded) downcounting mode in downcounting mode, the counter counts from the auto-reload value (content of the timx_arr register) down to 0, then restarts ...

  • Page 368

    Docid13902 rev 15 368/1128 rm0008 general-purpose timers (tim2 to tim5) 417 figure 109. Counter timing diagram, internal clock divided by 1 figure 110. Counter timing diagram, internal clock divided by 2 figure 111. Counter timing diagram, internal clock divided by 4 ck_int 36 cnt_en timer clock = c...

  • Page 369

    General-purpose timers (tim2 to tim5) rm0008 369/1128 docid13902 rev 15 figure 112. Counter timing diagram, internal clock divided by n figure 113. Counter timing diagram, update event center-aligned mode (up/down counting) in center-aligned mode, the counter counts from 0 to the auto-reload value (...

  • Page 370

    Docid13902 rev 15 370/1128 rm0008 general-purpose timers (tim2 to tim5) 417 the uev update event can be disabled by software by setting the udis bit in timx_cr1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs unt...

  • Page 371

    General-purpose timers (tim2 to tim5) rm0008 371/1128 docid13902 rev 15 figure 115. Counter timing diagram, internal clock divided by 2 figure 116. Counter timing diagram, internal clock divided by 4, timx_arr=0x36 1. Center-aligned mode 2 or 3 is used with an uif on overflow. Figure 117. Counter ti...

  • Page 372

    Docid13902 rev 15 372/1128 rm0008 general-purpose timers (tim2 to tim5) 417 figure 118. Counter timing diagram, update event with arpe=1 (counter underflow) figure 119. Counter timing diagram, update event with arpe=1 (counter overflow) 15.3.3 clock selection the counter clock can be provided by the...

  • Page 373

    General-purpose timers (tim2 to tim5) rm0008 373/1128 docid13902 rev 15 internal clock source (ck_int) if the slave mode controller is disabled (sms=000 in the timx_smcr register), then the cen, dir (in the timx_cr1 register) and ug bits (in the timx_egr register) are actual control bits and can be ...

  • Page 374

    Docid13902 rev 15 374/1128 rm0008 general-purpose timers (tim2 to tim5) 417 note: the capture prescaler is not used for triggering, so you don’t need to configure it. 3. Select rising edge polarity by writing cc2p=0 in the timx_ccer register. 4. Configure the timer in external clock mode 1 by writin...

  • Page 375

    General-purpose timers (tim2 to tim5) rm0008 375/1128 docid13902 rev 15 1. As no filter is needed in this example, write etf[3:0]=0000 in the timx_smcr register. 2. Set the prescaler by writing etps[1:0]=01 in the timx_smcr register 3. Select rising edge detection on the etr pin by writing etp=0 in ...

  • Page 376

    Docid13902 rev 15 376/1128 rm0008 general-purpose timers (tim2 to tim5) 417 the output stage generates an intermediate waveform which is then used for reference: ocxref (active high). The polarity acts at the end of the chain. Figure 126. Capture/compare channel 1 main circuit figure 127. Output sta...

  • Page 377

    General-purpose timers (tim2 to tim5) rm0008 377/1128 docid13902 rev 15 15.3.5 input capture mode in input capture mode, the capture/compare registers (timx_ccrx) are used to latch the value of the counter after a transition detected by the corresponding icx signal. When a capture occurs, the corres...

  • Page 378

    Docid13902 rev 15 378/1128 rm0008 general-purpose timers (tim2 to tim5) 417 15.3.6 pwm input mode this mode is a particular case of input capture mode. The procedure is the same except: • two icx signals are mapped on the same tix input. • these 2 icx signals are active on edges with opposite polari...

  • Page 379

    General-purpose timers (tim2 to tim5) rm0008 379/1128 docid13902 rev 15 15.3.7 forced output mode in output mode (ccxs bits = 00 in the timx_ccmrx register), each output compare signal (ocxref and then ocx) can be forced to active or inactive level directly by software, independently of any comparis...

  • Page 380

    Docid13902 rev 15 380/1128 rm0008 general-purpose timers (tim2 to tim5) 417 the timx_ccrx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (ocxpe=0, else timx_ccrx shadow register is updated only at the next update even...

  • Page 381

    General-purpose timers (tim2 to tim5) rm0008 381/1128 docid13902 rev 15 this forces the pwm by software while the timer is running. The timer is able to generate pwm in edge-aligned mode or center-aligned mode depending on the cms bits in the timx_cr1 register. Pwm edge-aligned mode upcounting confi...

  • Page 382

    Docid13902 rev 15 382/1128 rm0008 general-purpose timers (tim2 to tim5) 417 figure 131 shows some center-aligned pwm waveforms in an example where: • timx_arr=8, • pwm mode is the pwm mode 1, • the flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for cms=0...

  • Page 383

    General-purpose timers (tim2 to tim5) rm0008 383/1128 docid13902 rev 15 in the timx_cr1 register. Moreover, the dir and cms bits must not be changed at the same time by the software. • writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results...

  • Page 384

    Docid13902 rev 15 384/1128 rm0008 general-purpose timers (tim2 to tim5) 417 let’s use ti2fp2 as trigger 1: • map ti2fp2 on ti2 by writing cc2s=01 in the timx_ccmr1 register. • ti2fp2 must detect a rising edge, write cc2p=0 in the timx_ccer register. • configure ti2fp2 as trigger for the slave mode c...

  • Page 385

    General-purpose timers (tim2 to tim5) rm0008 385/1128 docid13902 rev 15 1. The external trigger prescaler should be kept off: bits etps[1:0] in the timx_smcr register are cleared to 00. 2. The external clock mode 2 must be disabled: bit ece in the tim1_smcr register is cleared to 0. 3. The external ...

  • Page 386

    Docid13902 rev 15 386/1128 rm0008 general-purpose timers (tim2 to tim5) 417 in this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position. The count direction correspond to the...

  • Page 387

    General-purpose timers (tim2 to tim5) rm0008 387/1128 docid13902 rev 15 figure 134. Example of counter operation in encoder interface mode figure 135 gives an example of counter behavior when ti1fp1 polarity is inverted (same configuration as above except cc1p=1). Figure 135. Example of encoder inte...

  • Page 388

    Docid13902 rev 15 388/1128 rm0008 general-purpose timers (tim2 to tim5) 417 15.3.13 timer input xor function the ti1s bit in the tim1_cr2 register, allows the input filter of channel 1 to be connected to the output of a xor gate, combining the three input pins timx_ch1 to timx_ch3. The xor output ca...

  • Page 389

    General-purpose timers (tim2 to tim5) rm0008 389/1128 docid13902 rev 15 slave mode: gated mode the counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when ti1 input is low: • configure the channel 1 to detect low levels on ti1. Conf...

  • Page 390

    Docid13902 rev 15 390/1128 rm0008 general-purpose timers (tim2 to tim5) 417 figure 138. Control circuit in trigger mode slave mode: external clock mode 2 + trigger mode the external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). In this ca...

  • Page 391

    General-purpose timers (tim2 to tim5) rm0008 391/1128 docid13902 rev 15 figure 139. Control circuit in external clock mode 2 + trigger mode 15.3.15 timer synchronization the timx timers are linked together internally for timer synchronization or chaining. When one timer is configured in master mode,...

  • Page 392

    Docid13902 rev 15 392/1128 rm0008 general-purpose timers (tim2 to tim5) 417 using one timer to enable another timer in this example, we control the enable of timer 2 with the output compare 1 of timer 1. Refer to figure 140 for connections. Timer 2 counts on the divided internal clock only when oc1r...

  • Page 393

    General-purpose timers (tim2 to tim5) rm0008 393/1128 docid13902 rev 15 timers. Timer 2 stops when timer 1 is disabled by writing ‘0 to the cen bit in the tim1_cr1 register: • configure timer 1 master mode to send its output compare 1 reference (oc1ref) signal as trigger output (mms=100 in the tim1_...

  • Page 394

    Docid13902 rev 15 394/1128 rm0008 general-purpose timers (tim2 to tim5) 417 figure 143. Triggering timer 2 with update of timer 1 as in the previous example, you can initialize both counters before starting counting. Figure 144 shows the behavior with the same configuration as in figure 141 but in t...

  • Page 395

    General-purpose timers (tim2 to tim5) rm0008 395/1128 docid13902 rev 15 using one timer as prescaler for another timer for example, you can configure timer 1 to act as a prescaler for timer 2. Refer to figure 140 for connections. To do this: • configure timer 1 master mode to send its update event (...

  • Page 396

    Docid13902 rev 15 396/1128 rm0008 general-purpose timers (tim2 to tim5) 417 figure 145. Triggering timer 1 and 2 with timer 1 ti1 input 15.3.16 debug mode when the microcontroller enters debug mode (cortex ® -m3 core - halted), the timx counter either continues to work normally or stops, depending o...

  • Page 397: 15.4

    General-purpose timers (tim2 to tim5) rm0008 397/1128 docid13902 rev 15 15.4 timx2 to tim5 registers refer to section 2.1 on page 47 for a list of abbreviations used in register descriptions. The 32-bit peripheral registers have to be written by words (32 bits). All other peripheral registers have t...

  • Page 398

    Docid13902 rev 15 398/1128 rm0008 general-purpose timers (tim2 to tim5) 417 bit 2 urs:update request source this bit is set and cleared by software to select the uev event sources. 0: any of the following events generate an update interrupt or dma request if enabled. These events can be: – counter o...

  • Page 399

    General-purpose timers (tim2 to tim5) rm0008 399/1128 docid13902 rev 15 15.4.2 timx control register 2 (timx_cr2) address offset: 0x04 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ti1s mms[2:0] ccds reserved rw rw rw rw rw bits 15:8 reserved, must be kept at reset value. Bit 7 ...

  • Page 400

    Docid13902 rev 15 400/1128 rm0008 general-purpose timers (tim2 to tim5) 417 15.4.3 timx slave mode control register (timx_smcr) address offset: 0x08 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 etp ece etps[1:0] etf[3:0] msm ts[2:0] res. Sms[2:0] rw rw rw rw rw rw rw rw rw rw rw rw rw r...

  • Page 401

    General-purpose timers (tim2 to tim5) rm0008 401/1128 docid13902 rev 15 bits 6:4 ts: trigger selection this bit-field selects the trigger input to be used to synchronize the counter. 000: internal trigger 0 (itr0). 001: internal trigger 1 (itr1). 010: internal trigger 2 (itr2). 011: internal trigger...

  • Page 402

    Docid13902 rev 15 402/1128 rm0008 general-purpose timers (tim2 to tim5) 417 15.4.4 timx dma/interrupt enable register (timx_dier) address offset: 0x0c reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res. Tde res cc4de cc3de cc2de cc1de ude res. Tie res cc4ie cc3ie cc2ie cc1ie uie rw rw rw ...

  • Page 403

    General-purpose timers (tim2 to tim5) rm0008 403/1128 docid13902 rev 15 15.4.5 timx status register (timx_sr) address offset: 0x10 reset value: 0x0000 bit 2 cc2ie: capture/compare 2 interrupt enable 0: cc2 interrupt disabled. 1: cc2 interrupt enabled. Bit 1 cc1ie: capture/compare 1 interrupt enable ...

  • Page 404

    Docid13902 rev 15 404/1128 rm0008 general-purpose timers (tim2 to tim5) 417 bit 2 cc2if: capture/compare 2 interrupt flag refer to cc1if description bit 1 cc1if: capture/compare 1 interrupt flag if channel cc1 is configured as output: this flag is set by hardware when the counter matches the compare...

  • Page 405

    General-purpose timers (tim2 to tim5) rm0008 405/1128 docid13902 rev 15 15.4.6 timx event generation register (timx_egr) address offset: 0x14 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved tg res. Cc4g cc3g cc2g cc1g ug w w w w w w bits 15:7 reserved, must be kept at reset value....

  • Page 406

    Docid13902 rev 15 406/1128 rm0008 general-purpose timers (tim2 to tim5) 417 15.4.7 timx capture/compare mode register 1 (timx_ccmr1) address offset: 0x18 reset value: 0x0000 the channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configu...

  • Page 407

    General-purpose timers (tim2 to tim5) rm0008 407/1128 docid13902 rev 15 bits 6:4 oc1m: output compare 1 mode these bits define the behavior of the output reference signal oc1ref from which oc1 and oc1n are derived. Oc1ref is active high whereas oc1 and oc1n active level depends on cc1p and cc1np bit...

  • Page 408

    Docid13902 rev 15 408/1128 rm0008 general-purpose timers (tim2 to tim5) 417 input capture mode bits 15:12 ic2f: input capture 2 filter bits 11:10 ic2psc[1:0]:input capture 2 prescaler bits 9:8 cc2s: capture/compare 2 selection this bit-field defines the direction of the channel (input/output) as wel...

  • Page 409

    General-purpose timers (tim2 to tim5) rm0008 409/1128 docid13902 rev 15 15.4.8 timx capture/compare mode register 2 (timx_ccmr2) address offset: 0x1c reset value: 0x0000 refer to the above ccmr1 register description. Output compare mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 oc4ce oc4m[2:0] oc4pe oc4...

  • Page 410

    Docid13902 rev 15 410/1128 rm0008 general-purpose timers (tim2 to tim5) 417 input capture mode 15.4.9 timx capture/compare enable register (timx_ccer) address offset: 0x20 reset value: 0x0000 bits 15:12 ic4f:input capture 4 filter bits 11:10 ic4psc: input capture 4 prescaler bits 9:8 cc4s: capture/c...

  • Page 411

    General-purpose timers (tim2 to tim5) rm0008 411/1128 docid13902 rev 15 note: the state of the external io pins connected to the standard ocx channels depends on the ocx channel state and the gpio and afio registers. 15.4.10 timx counter (timx_cnt) address offset: 0x24 reset value: 0x0000 bit 4 cc2e...

  • Page 412

    Docid13902 rev 15 412/1128 rm0008 general-purpose timers (tim2 to tim5) 417 15.4.11 timx prescaler (timx_psc) address offset: 0x28 reset value: 0x0000 15.4.12 timx auto-reload register (timx_arr) address offset: 0x2c reset value: 0x0000 15.4.13 timx capture/compare register 1 (timx_ccr1) address off...

  • Page 413

    General-purpose timers (tim2 to tim5) rm0008 413/1128 docid13902 rev 15 15.4.14 timx capture/compare register 2 (timx_ccr2) address offset: 0x38 reset value: 0x0000 15.4.15 timx capture/compare register 3 (timx_ccr3) address offset: 0x3c reset value: 0x0000 15.4.16 timx capture/compare register 4 (t...

  • Page 414

    Docid13902 rev 15 414/1128 rm0008 general-purpose timers (tim2 to tim5) 417 15.4.17 timx dma control register (timx_dcr) address offset: 0x48 reset value: 0x0000 15.4.18 timx dma address for full transfer (timx_dmar) address offset: 0x4c reset value: 0x0000 bits 15:0 ccr4[15:0]: capture/compare valu...

  • Page 415

    General-purpose timers (tim2 to tim5) rm0008 415/1128 docid13902 rev 15 example of how to use the dma burst feature in this example the timer dma burst feature is used to update the contents of the ccrx registers (x = 2, 3, 4) with the dma transferring half words into the ccrx registers. This is don...

  • Page 416

    Docid13902 rev 15 416/1128 rm0008 general-purpose timers (tim2 to tim5) 417 15.4.19 timx register map timx registers are mapped as described in the table below: table 88. Timx register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 ...

  • Page 417

    General-purpose timers (tim2 to tim5) rm0008 417/1128 docid13902 rev 15 refer to table 3 on page 51 for the register boundary addresses. 0x2c timx_arr reserved arr[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x30 reserved 0x34 timx_ccr1 reserved ccr1[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0...

  • Page 418: 16.1

    Docid13902 rev 15 418/1128 rm0008 general-purpose timers (tim9 to tim14) 460 16 general-purpose timers (tim9 to tim14) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f10...

  • Page 419: 16.2

    General-purpose timers (tim9 to tim14) rm0008 419/1128 docid13902 rev 15 16.2 tim9 to tim14 main features 16.2.1 tim9/tim12 main features the features of the tim9 to tim14 general-purpose timers include: • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide the counter clock ...

  • Page 420

    Docid13902 rev 15 420/1128 rm0008 general-purpose timers (tim9 to tim14) 460 16.2.2 tim10/tim11 and tim13/tim14 main features the features of general-purpose timers tim10/tim11 and tim13/tim14 include: • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide the counter clock fr...

  • Page 421: 16.3

    General-purpose timers (tim9 to tim14) rm0008 421/1128 docid13902 rev 15 16.3 tim9 to tim14 functional description 16.3.1 time-base unit the main block of the timer is a 16-bit counter with its related auto-reload register. The counters counts up. The counter clock can be divided by a prescaler. The...

  • Page 422

    Docid13902 rev 15 422/1128 rm0008 general-purpose timers (tim9 to tim14) 460 figure 148. Counter timing diagram with prescaler division change from 1 to 2 figure 149. Counter timing diagram with prescaler division change from 1 to 4 16.3.2 counter modes upcounting mode in upcounting mode, the counte...

  • Page 423

    General-purpose timers (tim9 to tim14) rm0008 423/1128 docid13902 rev 15 setting the uif flag (thus no interrupt is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the...

  • Page 424

    Docid13902 rev 15 424/1128 rm0008 general-purpose timers (tim9 to tim14) 460 figure 152. Counter timing diagram, internal clock divided by 4 figure 153. Counter timing diagram, internal clock divided by n figure 154. Counter timing diagram, update event when arpe=0 (timx_arr not preloaded) ck_psc 00...

  • Page 425

    General-purpose timers (tim9 to tim14) rm0008 425/1128 docid13902 rev 15 figure 155. Counter timing diagram, update event when arpe=1 (timx_arr preloaded) 16.3.3 clock selection the counter clock can be provided by the following clock sources: • internal clock (ck_int) • external clock mode1 (for ti...

  • Page 426

    Docid13902 rev 15 426/1128 rm0008 general-purpose timers (tim9 to tim14) 460 figure 156. Control circuit in normal mode, internal clock divided by 1 external clock source mode 1( tim9 and tim1 2 ) this mode is selected when sms=’111’ in the timx_smcr register. The counter can count at each rising or...

  • Page 427

    General-purpose timers (tim9 to tim14) rm0008 427/1128 docid13902 rev 15 figure 158. Control circuit in external clock mode 1 16.3.4 capture/compare channels each capture/compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital...

  • Page 428

    Docid13902 rev 15 428/1128 rm0008 general-purpose timers (tim9 to tim14) 460 figure 160. Capture/compare channel 1 main circuit figure 161. Output stage of capture/compare channel (channel 1) the capture/compare block is made of one preload register and one shadow register. Write and read always acc...

  • Page 429

    General-purpose timers (tim9 to tim14) rm0008 429/1128 docid13902 rev 15 cleared by software by writing it to ‘0’ or by reading the captured data stored in the timx_ccrx register. Ccxof is cleared when you write it to ‘0’. The following example shows how to capture the counter value in timx_ccr1 whe...

  • Page 430

    Docid13902 rev 15 430/1128 rm0008 general-purpose timers (tim9 to tim14) 460 1. Select the active input for timx_ccr1: write the cc1s bits to ‘01’ in the timx_ccmr1 register (ti1 selected). 2. Select the active polarity for ti1fp1 (used both for capture in timx_ccr1 and counter clear): program the c...

  • Page 431

    General-purpose timers (tim9 to tim14) rm0008 431/1128 docid13902 rev 15 16.3.8 output compare mode this function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare func...

  • Page 432

    Docid13902 rev 15 432/1128 rm0008 general-purpose timers (tim9 to tim14) 460 figure 163. Output compare mode, toggle on oc1. 16.3.9 pwm mode pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the timx_arr register and a duty cycle determined by th...

  • Page 433

    General-purpose timers (tim9 to tim14) rm0008 433/1128 docid13902 rev 15 figure 164. Edge-aligned pwm waveforms (arr=8) 16.3.10 one-pulse mode one-pulse mode (opm) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a...

  • Page 434

    Docid13902 rev 15 434/1128 rm0008 general-purpose timers (tim9 to tim14) 460 for example you may want to generate a positive pulse on oc1 with a length of t pulse and after a delay of t delay as soon as a positive edge is detected on the ti2 input pin. Use ti2fp2 as trigger 1: 1. Map ti2fp2 to ti2 b...

  • Page 435

    General-purpose timers (tim9 to tim14) rm0008 435/1128 docid13902 rev 15 slave mode: reset mode the counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the urs bit from the timx_cr1 register is low, an update event uev is generated. Then all the pr...

  • Page 436

    Docid13902 rev 15 436/1128 rm0008 general-purpose timers (tim9 to tim14) 460 the counter starts counting on the internal clock as long as ti1 is low and stops as soon as ti1 becomes high. The tif flag in the timx_sr register is set both when the counter starts or stops. The delay between the rising ...

  • Page 437: 16.4

    General-purpose timers (tim9 to tim14) rm0008 437/1128 docid13902 rev 15 16.3.12 timer synchronization (tim9/12) the tim timers are linked together internally for timer synchronization or chaining. Refer to section 15.3.15: timer synchronization on page 391 for details. 16.3.13 debug mode when the m...

  • Page 438

    Docid13902 rev 15 438/1128 rm0008 general-purpose timers (tim9 to tim14) 460 bit 2 urs:update request source this bit is set and cleared by software to select the uev event sources. 0: any of the following events generates an update interrupt if enabled: – counter overflow – setting the ug bit 1: on...

  • Page 439

    General-purpose timers (tim9 to tim14) rm0008 439/1128 docid13902 rev 15 16.4.2 9/12tim9/12 slave mode control register (timx_smcr) address offset: 0x08 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ts[2:0] res. Sms[2:0] rw rw rw rw rw rw bits 6:4 ts: trigger selection this bitf...

  • Page 440

    Docid13902 rev 15 440/1128 rm0008 general-purpose timers (tim9 to tim14) 460 16.4.3 tim9/12 interrupt enable register (timx_dier) address offset: 0x0c reset value: 0x0000 tim4 tim1 tim2 tim3 tim8 tim5 tim2 tim3 tim4 tim8 tim9 tim2 tim3 tim10 tim11 tim12 tim4 tim5 tim13 tim14 table 89. Timx internal ...

  • Page 441

    General-purpose timers (tim9 to tim14) rm0008 441/1128 docid13902 rev 15 16.4.4 tim9/12 status register (timx_sr) address offset: 0x10 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved cc2of cc1of reserved tif reserved cc2if cc1if uif rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 bits 15:11 r...

  • Page 442

    Docid13902 rev 15 442/1128 rm0008 general-purpose timers (tim9 to tim14) 460 16.4.5 tim9/12 event generation register (timx_egr) address offset: 0x14 reset value: 0x0000 bit 2 cc2if: capture/compare 2 interrupt flag refer to cc1if description bit 1 cc1if: capture/compare 1 interrupt flag if channel ...

  • Page 443

    General-purpose timers (tim9 to tim14) rm0008 443/1128 docid13902 rev 15 bit 2 cc2g: capture/compare 2 generation refer to cc1g description bit 1 cc1g: capture/compare 1 generation this bit is set by software to generate an event, it is automatically cleared by hardware. 0: no action 1: a capture/co...

  • Page 444

    Docid13902 rev 15 444/1128 rm0008 general-purpose timers (tim9 to tim14) 460 16.4.6 tim9/12 capture/compare mode register 1 (timx_ccmr1) address offset: 0x18 reset value: 0x0000 the channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by con...

  • Page 445

    General-purpose timers (tim9 to tim14) rm0008 445/1128 docid13902 rev 15 bits 6:4 oc1m: output compare 1 mode these bits define the behavior of the output reference signal oc1ref from which oc1 and oc1n are derived. Oc1ref is active high whereas the active levels of oc1 and oc1n depend on the cc1p a...

  • Page 446

    Docid13902 rev 15 446/1128 rm0008 general-purpose timers (tim9 to tim14) 460 input capture mode bits 15:12 ic2f: input capture 2 filter bits 11:10 ic2psc[1:0]:input capture 2 prescaler bits 9:8 cc2s: capture/compare 2 selection this bitfield defines the direction of the channel (input/output) as wel...

  • Page 447

    General-purpose timers (tim9 to tim14) rm0008 447/1128 docid13902 rev 15 16.4.7 tim9/12 capture/compare enable register (timx_ccer) address offset: 0x20 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved cc2np res. Cc2p cc2e cc1np res. Cc1p cc1e rw rw rw rw rw rw bits 15:8 reserved, ...

  • Page 448

    Docid13902 rev 15 448/1128 rm0008 general-purpose timers (tim9 to tim14) 460 note: the states of the external i/o pins connected to the standard ocx channels depend on the state of the ocx channel and on the gpio registers. 16.4.8 tim9/12 counter (timx_cnt) address offset: 0x24 reset value: 0x0000 0...

  • Page 449

    General-purpose timers (tim9 to tim14) rm0008 449/1128 docid13902 rev 15 16.4.11 tim9/12 capture/compare register 1 (timx_ccr1) address offset: 0x34 reset value: 0x0000 16.4.12 tim9/12 capture/compare register 2 (timx_ccr2) address offset: 0x38 reset value: 0x0000 16.4.13 tim9/12 register map tim9/1...

  • Page 450

    Docid13902 rev 15 450/1128 rm0008 general-purpose timers (tim9 to tim14) 460 table 91. Tim9/12 register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 timx_cr1 reserved ckd [1:0] arp e reserved op m urs ud is ce n reset...

  • Page 451

    General-purpose timers (tim9 to tim14) rm0008 451/1128 docid13902 rev 15 refer to table 3 on page 51 for the register boundary addresses. 0x38 timx_ccr2 reserved ccr2[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x3c to 0x4c reserved table 91. Tim9/12 register map and reset values (continued) o...

  • Page 452: 16.5 Tim10/11/13/14

    Docid13902 rev 15 452/1128 rm0008 general-purpose timers (tim9 to tim14) 460 16.5 tim10/11/13/14 registers the peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 16.5.1 tim10/11/13/...

  • Page 453

    General-purpose timers (tim9 to tim14) rm0008 453/1128 docid13902 rev 15 16.5.2 tim10/11/13/14 status register (timx_sr) address offset: 0x10 reset value: 0x0000 16.5.3 tim10/11/13/14 event generation register (timx_egr) address offset: 0x14 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...

  • Page 454

    Docid13902 rev 15 454/1128 rm0008 general-purpose timers (tim9 to tim14) 460 16.5.4 tim10/11/13/14 capture/compare mode register 1 (timx_ccmr1) address offset: 0x18 reset value: 0x0000 the channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined...

  • Page 455

    General-purpose timers (tim9 to tim14) rm0008 455/1128 docid13902 rev 15 output compare mode bits 15:7 reserved, must be kept at reset value. Bits 6:4 oc1m: output compare 1 mode these bits define the behavior of the output reference signal oc1ref from which oc1 is derived. Oc1ref is active high whe...

  • Page 456

    Docid13902 rev 15 456/1128 rm0008 general-purpose timers (tim9 to tim14) 460 input capture mode bits 15:8 reserved, must be kept at reset value. Bits 7:4 ic1f: input capture 1 filter this bit-field defines the frequency used to sample ti1 input and the length of the digital filter applied to ti1. Th...

  • Page 457

    General-purpose timers (tim9 to tim14) rm0008 457/1128 docid13902 rev 15 16.5.5 tim10/11/13/14 capture/compare enable register (timx_ccer) address offset: 0x20 reset value: 0x0000 note: the state of the external i/o pins connected to the standard ocx channels depends on the ocx channel state and the...

  • Page 458

    Docid13902 rev 15 458/1128 rm0008 general-purpose timers (tim9 to tim14) 460 16.5.6 tim10/11/13/14 counter (timx_cnt) address offset: 0x24 reset value: 0x0000 16.5.7 tim10/11/13/14 prescaler (timx_psc) address offset: 0x28 reset value: 0x0000 16.5.8 tim10/11/13/14 auto-reload register (timx_arr) add...

  • Page 459

    General-purpose timers (tim9 to tim14) rm0008 459/1128 docid13902 rev 15 16.5.9 tim10/11/13/14 capture/compare register 1 (timx_ccr1) address offset: 0x34 reset value: 0x0000 16.5.10 tim10/11/13/14 register map timx registers are mapped as 16-bit addressable registers as described in the tables belo...

  • Page 460

    Docid13902 rev 15 460/1128 rm0008 general-purpose timers (tim9 to tim14) 460 refer to table 3 on page 51 for the register boundary addresses. 0x18 timx_ccmr1 output compare mode reserved oc1m [2:0] oc1pe oc1 f e cc1s [1:0] reset value 0 0 0 0 0 0 0 timx_ccmr1 input capture mode reserved ic1f[3:0] ic...

  • Page 461: Basic Timers (Tim6&tim7)

    Basic timers (tim6&tim7) rm0008 461/1128 docid13902 rev 15 17 basic timers (tim6&tim7) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102xx and stm32f103xx...

  • Page 462: 17.3

    Docid13902 rev 15 462/1128 rm0008 basic timers (tim6&tim7) 472 figure 169. Basic timer block diagram 17.3 tim6&tim7 functional description 17.3.1 time-base unit the main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a...

  • Page 463

    Basic timers (tim6&tim7) rm0008 463/1128 docid13902 rev 15 prescaler description the prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the timx_psc register). It can be changed on the fly as th...

  • Page 464

    Docid13902 rev 15 464/1128 rm0008 basic timers (tim6&tim7) 472 17.3.2 counting mode the counter counts from 0 to the auto-reload value (contents of the timx_arr register), then restarts from 0 and generates a counter overflow event. An update event can be generate at each counter overflow or by sett...

  • Page 465

    Basic timers (tim6&tim7) rm0008 465/1128 docid13902 rev 15 figure 173. Counter timing diagram, internal clock divided by 2 figure 174. Counter timing diagram, internal clock divided by 4 figure 175. Counter timing diagram, internal clock divided by n ck_int 0035 0000 0001 0002 0003 cnt_en timer cloc...

  • Page 466

    Docid13902 rev 15 466/1128 rm0008 basic timers (tim6&tim7) 472 figure 176. Counter timing diagram, update event when arpe = 0 (timx_arr not preloaded) figure 177. Counter timing diagram, update event when arpe=1 (timx_arr preloaded) 17.3.3 clock source the counter clock is provided by the internal c...

  • Page 467: 17.4 Tim6&tim7

    Basic timers (tim6&tim7) rm0008 467/1128 docid13902 rev 15 figure 178. Control circuit in normal mode, internal clock divided by 1 17.3.4 debug mode when the microcontroller enters the debug mode (cortex ® -m3 core - halted), the timx counter either continues to work normally or stops, depending on ...

  • Page 468

    Docid13902 rev 15 468/1128 rm0008 basic timers (tim6&tim7) 472 bit 2 urs:update request source this bit is set and cleared by software to select the uev event sources. 0: any of the following events generates an update interrupt or dma request if enabled. These events can be: – counter overflow/unde...

  • Page 469

    Basic timers (tim6&tim7) rm0008 469/1128 docid13902 rev 15 17.4.2 tim6&tim7 control register 2 (timx_cr2) address offset: 0x04 reset value: 0x0000 17.4.3 tim6&tim7 dma/interrupt enable register (timx_dier) address offset: 0x0c reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved mms[2:...

  • Page 470

    Docid13902 rev 15 470/1128 rm0008 basic timers (tim6&tim7) 472 17.4.4 tim6&tim7 status register (timx_sr) address offset: 0x10 reset value: 0x0000 17.4.5 tim6&tim7 event generation register (timx_egr) address offset: 0x14 reset value: 0x0000 17.4.6 tim6&tim7 counter (timx_cnt) address offset: 0x24 r...

  • Page 471

    Basic timers (tim6&tim7) rm0008 471/1128 docid13902 rev 15 17.4.7 tim6&tim7 prescaler (timx_psc) address offset: 0x28 reset value: 0x0000 17.4.8 tim6&tim7 auto-reload register (timx_arr) address offset: 0x2c reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 psc[15:0] rw rw rw rw rw rw rw rw ...

  • Page 472

    Docid13902 rev 15 472/1128 rm0008 basic timers (tim6&tim7) 472 17.4.9 tim6&tim7 register map timx registers are mapped as 16-bit addressable registers as described in the table below: refer to table 3 on page 51 for the register boundary addresses. Table 94. Tim6&tim7 register map and reset values o...

  • Page 473: 18 Real-Time

    Real-time clock (rtc) rm0008 473/1128 docid13902 rev 15 18 real-time clock (rtc) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102xx and stm32f103xx micro...

  • Page 474: 18.2

    Docid13902 rev 15 474/1128 rm0008 real-time clock (rtc) 484 18.2 rtc main features • programmable prescaler: division factor up to 2 20 • 32-bit programmable counter for long-term measurement • two separate clocks: pclk1 for the apb1 interface and rtc clock (must be at least four times slower than t...

  • Page 475: 18.3

    Real-time clock (rtc) rm0008 475/1128 docid13902 rev 15 18.3 rtc functional description 18.3.1 overview the rtc consists of two main units (see figure 179 on page 475 ). The first one (apb1 interface) is used to interface with the apb1 bus. This unit also contains a set of 16-bit registers accessibl...

  • Page 476

    Docid13902 rev 15 476/1128 rm0008 real-time clock (rtc) 484 18.3.2 resetting rtc registers all system registers are asynchronously reset by a system reset or power reset, except for rtc_prl, rtc_alr, rtc_cnt, and rtc_div. The rtc_prl, rtc_alr, rtc_cnt, and rtc_div registers are reset only by a backu...

  • Page 477

    Real-time clock (rtc) rm0008 477/1128 docid13902 rev 15 18.3.5 rtc flag assertion the rtc second flag (secf) is asserted on each rtc core clock cycle before the update of the rtc counter. The rtc overflow flag (owf) is asserted on the last rtc core clock cycle before the counter reaches 0x0000. The ...

  • Page 478: 18.4 Rtc

    Docid13902 rev 15 478/1128 rm0008 real-time clock (rtc) 484 18.4 rtc registers refer to section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 18.4.1 rtc control register high (rtc_crh) addr...

  • Page 479

    Real-time clock (rtc) rm0008 479/1128 docid13902 rev 15 18.4.2 rtc control register low (rtc_crl) address offset: 0x04 reset value: 0x0020 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved rtoff cnf rsf owf alrf secf r rw rc_w0 rc_w0 rc_w0 rc_w0 bits 15:6 reserved, forced by hardware to 0. Bit 5 rtoff:...

  • Page 480

    Docid13902 rev 15 480/1128 rm0008 real-time clock (rtc) 484 the functions of the rtc are controlled by this control register. It is not possible to write to the rtc_cr register while the peripheral is completing a previous write operation (flagged by rtoff=0, see section 18.3.4 on page 476 ). Note: ...

  • Page 481

    Real-time clock (rtc) rm0008 481/1128 docid13902 rev 15 rtc prescaler load register low (rtc_prll) address offset: 0x0c write only (see section 18.3.4 on page 476 ) reset value: 0x8000 note: if the input clock frequency (f rtcclk ) is 32.768 khz, write 7fffh in this register to get a signal period o...

  • Page 482

    Docid13902 rev 15 482/1128 rm0008 real-time clock (rtc) 484 18.4.5 rtc counter register (rtc_cnth / rtc_cntl) the rtc core has one 32-bit programmable counter, accessed through two 16-bit registers; the count rate is based on the tr_clk time reference, generated by the prescaler. Rtc_cnt registers k...

  • Page 483

    Real-time clock (rtc) rm0008 483/1128 docid13902 rev 15 18.4.6 rtc alarm register high (rtc_alrh / rtc_alrl) when the programmable counter reaches the 32-bit value stored in the rtc_alr register, an alarm is triggered and the rtc_alarmit interrupt request is generated. This register is write-protect...

  • Page 484

    Docid13902 rev 15 484/1128 rm0008 real-time clock (rtc) 484 18.4.7 rtc register map rtc registers are mapped as 16-bit addressable registers as described in the table below: refer to table 3 on page 51 for the register boundary addresses. Table 95. Rtc register map and reset values offset register 3...

  • Page 485: Independent Watchdog (Iwdg)

    Independent watchdog (iwdg) rm0008 485/1128 docid13902 rev 15 19 independent watchdog (iwdg) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102xx and stm32...

  • Page 486

    Docid13902 rev 15 486/1128 rm0008 independent watchdog (iwdg) 490 whenever the key value 0xaaaa is written in the iwdg_kr register, the iwdg_rlr value is reloaded in the counter and the watchdog reset is prevented. 19.3.1 hardware watchdog if the “hardware watchdog” feature is enabled through the de...

  • Page 487: 19.4 Iwdg

    Independent watchdog (iwdg) rm0008 487/1128 docid13902 rev 15 the lsi can be calibrated so as to compute the iwdg timeout with an acceptable accuracy. For more details refer to lsi clock on page 96 . 19.4 iwdg registers refer to section 2.1 on page 47 for a list of abbreviations used in register des...

  • Page 488

    Docid13902 rev 15 488/1128 rm0008 independent watchdog (iwdg) 490 19.4.2 prescaler register (iwdg_pr) address offset: 0x04 reset value: 0x0000 0000 19.4.3 reload register (iwdg_rlr) address offset: 0x08 reset value: 0x0000 0fff (reset by standby mode) 19.4.4 status register (iwdg_sr) address offset:...

  • Page 489

    Independent watchdog (iwdg) rm0008 489/1128 docid13902 rev 15 reset value: 0x0000 0000 (not reset by standby mode) note: if several reload values or prescaler values are used by application, it is mandatory to wait until rvu bit is reset before changing the reload value and to wait until pvu bit is ...

  • Page 490

    Docid13902 rev 15 490/1128 rm0008 independent watchdog (iwdg) 490 19.4.5 iwdg register map the following table gives the iwdg register map and reset values. Refer to table 3 on page 51 for the register boundary addresses. Table 97. Iwdg register map and reset values offset register 31 30 29 28 27 26...

  • Page 491: Window Watchdog (Wwdg)

    Window watchdog (wwdg) rm0008 491/1128 docid13902 rev 15 20 window watchdog (wwdg) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102xx and stm32f103xx mic...

  • Page 492

    Docid13902 rev 15 492/1128 rm0008 window watchdog (wwdg) 497 figure 183. Watchdog block diagram the application program must write in the wwdg_cr register at regular intervals during normal operation to prevent an mcu reset. This operation must occur only when the counter value is lower than the win...

  • Page 493: 20.4

    Window watchdog (wwdg) rm0008 493/1128 docid13902 rev 15 case, the corresponding interrupt service routine (isr) should reload the wwdg counter to avoid the wwdg reset, then trigger the required actions. The ewi interrupt is cleared by writing '0' to the ewif bit in the wwdg_sr register. Note: when ...

  • Page 494: 20.5 Debug

    Docid13902 rev 15 494/1128 rm0008 window watchdog (wwdg) 497 20.5 debug mode when the microcontroller enters debug mode (cortex ® -m3 core halted), the wwdg counter either continues to work normally or stops, depending on dbg_wwdg_stop configuration bit in dbg module. For more details, refer to sect...

  • Page 495: 20.6 Wwdg

    Window watchdog (wwdg) rm0008 495/1128 docid13902 rev 15 20.6 wwdg registers refer to section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 20.6.1 control register (wwdg_cr) address o...

  • Page 496

    Docid13902 rev 15 496/1128 rm0008 window watchdog (wwdg) 497 20.6.2 configuration register (wwdg_cfr) address offset: 0x04 reset value: 0x0000 007f 20.6.3 status register (wwdg_sr) address offset: 0x08 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 1...

  • Page 497

    Window watchdog (wwdg) rm0008 497/1128 docid13902 rev 15 20.6.4 wwdg register map the following table gives the wwdg register map and reset values. Refer to table 3 on page 51 for the register boundary addresses. Table 99. Wwdg register map and reset values offset register 31 30 29 28 27 26 25 24 23...

  • Page 498: 21.1 Fsmc

    Docid13902 rev 15 498/1128 rm0008 flexible static memory controller (fsmc) 555 21 flexible static memory controller (fsmc) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm3...

  • Page 499: 21.2 Block

    Flexible static memory controller (fsmc) rm0008 499/1128 docid13902 rev 15 the fsmc has the following main features: • interfaces with static memory-mapped devices including: – static random access memory (sram) – nor flash memory – psram (4 memory banks) • two banks of nand flash with ecc hardware ...

  • Page 500: 21.3 Ahb

    Docid13902 rev 15 500/1128 rm0008 flexible static memory controller (fsmc) 555 figure 185. Fsmc block diagram 21.3 ahb interface the ahb slave interface enables internal cpus and other bus master peripherals to access the external static memories. Ahb transactions are translated into the external de...

  • Page 501

    Flexible static memory controller (fsmc) rm0008 501/1128 docid13902 rev 15 the effect of this ahb error depends on the ahb master which has attempted the r/w access: • if it is the cortex ® -m3 cpu, a hard fault interrupt is generated • if is a dma, a dma transfer error is generated and the correspo...

  • Page 502: 21.4

    Docid13902 rev 15 502/1128 rm0008 flexible static memory controller (fsmc) 555 21.4 external device address mapping from the fsmc point of view, the external memory is divided into 4 fixed-size banks of 256 mbytes each (refer to figure 186 ): • bank 1 used to address up to 4 nor flash or psram memor...

  • Page 503

    Flexible static memory controller (fsmc) rm0008 503/1128 docid13902 rev 15 haddr[25:0] contain the external memory address. Since haddr is a byte address whereas the memory is addressed in words, the address actually issued to the memory varies according to the memory data width, as shown in the fol...

  • Page 504: 21.5

    Docid13902 rev 15 504/1128 rm0008 flexible static memory controller (fsmc) 555 the application software uses the 3 sections to access the nand flash memory: • to send a command to nand flash memory: the software must write the command value to any memory location in the command section. • to specify...

  • Page 505

    Flexible static memory controller (fsmc) rm0008 505/1128 docid13902 rev 15 21.5.1 external memory interface signals table 105 , table 106 and table 107 list the signals that are typically used to interface nor flash, sram and psram. Note: prefix “n”. Specifies the associated signal as active low. No...

  • Page 506

    Docid13902 rev 15 506/1128 rm0008 flexible static memory controller (fsmc) 555 nor flash, multiplexed i/os nor-flash memories are addressed in 16-bit words. The maximum capacity is 512 mbit (26 address lines). Psram/sram psram memories are addressed in 16-bit words. The maximum capacity is 512 mbit ...

  • Page 507

    Flexible static memory controller (fsmc) rm0008 507/1128 docid13902 rev 15 table 108. Nor flash/psram controller: example of supported memories and transactions device mode r/w ahb data size memory data size allowed/ not allowed comments nor flash (muxed i/os and nonmuxed i/os) asynchronous r 8 16 y...

  • Page 508

    Docid13902 rev 15 508/1128 rm0008 flexible static memory controller (fsmc) 555 21.5.3 general timing rules signals synchronization • all controller output signals change on the rising edge of the internal clock (hclk) • in synchronous mode (read or write), all output signals change on the rising edg...

  • Page 509

    Flexible static memory controller (fsmc) rm0008 509/1128 docid13902 rev 15 figure 187. Mode1 read accesses 1. Nbl[1:0] are driven low during read access. Figure 188. Mode1 write accesses the one hclk cycle at the end of the write transaction helps guarantee the address and data hold time after the n...

  • Page 510

    Docid13902 rev 15 510/1128 rm0008 flexible static memory controller (fsmc) 555 table 109. Fsmc_bcrx bit fields bit number bit name value to set 31-20 reserved 0x000 19 cburstrw 0x0 (no effect on asynchronous mode) 18:16 reserved 0x0 15 asyncwait set to 1 if the memory supports this feature. Otherwis...

  • Page 511

    Flexible static memory controller (fsmc) rm0008 511/1128 docid13902 rev 15 mode a - sram/psram (cram) oe toggling figure 189. Modea read accesses 1. Nbl[1:0] are driven low during read access. Figure 190. Modea write accesses a[25:0] noe (addset +1) (datast + 1) memory transaction data strobe nex d[...

  • Page 512

    Docid13902 rev 15 512/1128 rm0008 flexible static memory controller (fsmc) 555 the differences compared with mode1 are the toggling of noe and the independent read and write timings. Table 111. Fsmc_bcrx bit fields bit number bit name value to set 31-20 reserved 0x000 19 cburstrw 0x0 (no effect on a...

  • Page 513

    Flexible static memory controller (fsmc) rm0008 513/1128 docid13902 rev 15 mode 2/b - nor flash figure 191. Mode2 and mode b read accesses table 113. Fsmc_bwtrx bit fields bit number bit name value to set 31:30 reserved 0x0 29-28 accmod 0x0 27-24 datlat don’t care 23-20 clkdiv don’t care 19-16 bustu...

  • Page 514

    Docid13902 rev 15 514/1128 rm0008 flexible static memory controller (fsmc) 555 figure 192. Mode2 write accesses figure 193. Mode b write accesses the differences with mode1 are the toggling of nwe and the independent read and write timings when extended mode is set (mode b). A[25:0] noe (addset +1) ...

  • Page 515

    Flexible static memory controller (fsmc) rm0008 515/1128 docid13902 rev 15 table 114. Fsmc_bcrx bit fields bit number bit name value to set 31-20 reserved 0x000 19 cburstrw 0x0 (no effect on asynchronous mode) 18:16 reserved 0x0 15 asyncwait set to 1 if the memory supports this feature. Otherwise ke...

  • Page 516

    Docid13902 rev 15 516/1128 rm0008 flexible static memory controller (fsmc) 555 note: the fsmc_bwtrx register is valid only if extended mode is set (mode b), otherwise all its content is don’t care. Mode c - nor flash - oe toggling figure 194. Mode c read accesses table 116. Fsmc_bwtrx bit fields bit...

  • Page 517

    Flexible static memory controller (fsmc) rm0008 517/1128 docid13902 rev 15 figure 195. Mode c write accesses the differences compared with mode1 are the toggling of noe and the independent read and write timings. Table 117. Fsmc_bcrx bit fields bit no. Bit name value to set 31-20 reserved 0x000 19 c...

  • Page 518

    Docid13902 rev 15 518/1128 rm0008 flexible static memory controller (fsmc) 555 1 muxen 0x0 0 mbken 0x1 table 118. Fsmc_btrx bit fields bit number bit name value to set 31:30 reserved 0x0 29-28 accmod 0x2 27-24 datlat 0x0 23-20 clkdiv 0x0 19-16 busturn time between nex high to nex low (busturn hclk) ...

  • Page 519

    Flexible static memory controller (fsmc) rm0008 519/1128 docid13902 rev 15 mode d - asynchronous access with extended address figure 196. Mode d read accesses mode d write accessesthe differences with mode1 are the toggling of noe that goes on toggling after nadv changes and the independent read and...

  • Page 520

    Docid13902 rev 15 520/1128 rm0008 flexible static memory controller (fsmc) 555 table 120. Fsmc_bcrx bit fields bit no. Bit name value to set 31-20 reserved 0x000 19 cburstrw 0x0 (no effect on asynchronous mode) 18:16 reserved 0x0 15 asyncwait set to 1 if the memory supports this feature. Otherwise k...

  • Page 521

    Flexible static memory controller (fsmc) rm0008 521/1128 docid13902 rev 15 muxed mode - multiplexed asynchronous access to nor flash memory figure 197. Multiplexed read accesses 1. The bus turnaround delay (busturn + 1) and the delay between side-by-side transactions overlap, so busturn ≤ 5 has not ...

  • Page 522

    Docid13902 rev 15 522/1128 rm0008 flexible static memory controller (fsmc) 555 figure 198. Multiplexed write accesses the difference with mode d is the drive of the lower address byte(s) on the databus. Table 123. Fsmc_bcrx bit fields bit no. Bit name value to set 31-21 reserved 0x000 19 cburstrw 0x...

  • Page 523

    Flexible static memory controller (fsmc) rm0008 523/1128 docid13902 rev 15 wait management in asynchronous accesses if the asynchronous memory asserts a wait signal to indicate that it is not yet ready to accept or to provide data, the asyncwait bit has to be set in fsmc_bcrx register. If the wait s...

  • Page 524

    Docid13902 rev 15 524/1128 rm0008 flexible static memory controller (fsmc) 555 1. Memory asserts the wait signal aligned to noe/nwe which toggles: 2. Memory asserts the wait signal aligned to nex (or noe/nwe not toggling): if then otherwise where max_wait_assertion_time is the maximum time taken by ...

  • Page 525

    Flexible static memory controller (fsmc) rm0008 525/1128 docid13902 rev 15 figure 200. Asynchronous wait during a write access 1. Nwait polarity depends on waitpol bit setting in fsmc_bcrx register. !;= .7% -emory .7!)4 $;= .%x data aic (#,+ address data (#,+ dont dont.

  • Page 526

    Docid13902 rev 15 526/1128 rm0008 flexible static memory controller (fsmc) 555 21.5.5 synchronous transactions the memory clock, clk, is a submultiple of hclk according to the value of parameter clkdiv. Nor flash memories specify a minimum time from nadv assertion to clk high. To meet this constrain...

  • Page 527

    Flexible static memory controller (fsmc) rm0008 527/1128 docid13902 rev 15 during wait-state insertion via the nwait signal, the controller continues to send clock pulses to the memory, keeping the chip select and output enable signals valid, and does not consider the data valid. There are two timin...

  • Page 528

    Docid13902 rev 15 528/1128 rm0008 flexible static memory controller (fsmc) 555 figure 202. Synchronous multiplexed read mode - nor, psram (cram) 1. Byte lane outputs bl are not shown; for nor access, they are held high, and, for psram (cram) access, they are held low. 2. Nwait polarity is set to 0. ...

  • Page 529

    Flexible static memory controller (fsmc) rm0008 529/1128 docid13902 rev 15 10 wrapmod 0x0 9 waitpol to be set according to memory 8 bursten 0x1 7 reserved 0x1 6 faccen set according to memory support (nor flash memory) 5-4 mwid as needed 3-2 mtyp 0x1 or 0x2 1 muxen as needed 0 mbken 0x1 table 126. F...

  • Page 530

    Docid13902 rev 15 530/1128 rm0008 flexible static memory controller (fsmc) 555 figure 203. Synchronous multiplexed write mode - psram (cram) 1. Memory must issue nwait signal one cycle in advance, accordingly waitcfg must be programmed to 0. 2. Nwait polarity is set to 0. 3. Byte lane (nbl) outputs ...

  • Page 531

    Flexible static memory controller (fsmc) rm0008 531/1128 docid13902 rev 15 9 waitpol to be set according to memory 8 bursten no effect on synchronous write 7 reserved 0x1 6 faccen set according to memory support 5-4 mwid as needed 3-2 mtyp 0x1 1 muxen as needed 0 mbken 0x1 table 128. Fsmc_btrx bit f...

  • Page 532

    Docid13902 rev 15 532/1128 rm0008 flexible static memory controller (fsmc) 555 21.5.6 nor/psram control registers the nor/psram control registers have to be accessed by words (32 bits). Sram/nor-flash chip-select control registers 1..4 (fsmc_bcr1..4) address offset: 0xa000 0000 + 8 * (x – 1), x = 1....

  • Page 533

    Flexible static memory controller (fsmc) rm0008 533/1128 docid13902 rev 15 bit 13 waiten: wait enable bit. This bit enables/disables wait-state insertion via the nwait signal when accessing the flash memory in synchronous mode. 0: nwait signal is disabled (its level not taken into account, no wait s...

  • Page 534

    Docid13902 rev 15 534/1128 rm0008 flexible static memory controller (fsmc) 555 bits 3:2 mtyp: memory type. Defines the type of external memory attached to the corresponding memory bank: 00: sram (default after reset for bank 2...4) 01: psram (cram) 10: nor flash(default after reset for bank 1) 11: r...

  • Page 535

    Flexible static memory controller (fsmc) rm0008 535/1128 docid13902 rev 15 sram/nor-flash chip-select timing registers 1..4 (fsmc_btr1..4) address offset: 0xa000 0000 + 0x04 + 8 * (x – 1), x = 1..4 reset value: 0x0fff ffff this register contains the control information of each memory bank, used for ...

  • Page 536

    Docid13902 rev 15 536/1128 rm0008 flexible static memory controller (fsmc) 555 note: psrams (crams) have a variable latency due to internal refresh. Therefore these memories issue the nwait signal during the whole latency phase to prolong the latency as needed. With psrams (crams) the datlat field m...

  • Page 537

    Flexible static memory controller (fsmc) rm0008 537/1128 docid13902 rev 15 sram/nor-flash write timing registers 1..4 (fsmc_bwtr1..4) address offset: 0xa000 0000 + 0x104 + 8 * (x – 1), x = 1...4 reset value: 0x0fff ffff this register contains the control information of each memory bank, used for sra...

  • Page 538: 21.6

    Docid13902 rev 15 538/1128 rm0008 flexible static memory controller (fsmc) 555 21.6 nand flash/pc card controller the fsmc generates the appropriate signal timings to drive the following types of device: • nand flash – 8-bit – 16-bit • 16-bit pc card compatible devices the nand/pc card controller ca...

  • Page 539

    Flexible static memory controller (fsmc) rm0008 539/1128 docid13902 rev 15 21.6.1 external memory interface signals the following tables list the signals that are typically used to interface nand flash and pc card. Caution: when using a pc card or a compactflash in i/o mode, the nios16 input pin mus...

  • Page 540

    Docid13902 rev 15 540/1128 rm0008 flexible static memory controller (fsmc) 555 16-bit nand flash there is no theoretical capacity limitation as the fsmc can manage as many address cycles as needed. 16-bit pc card table 131. 16-bit nand flash fsmc signal name i/o function a[17] o nand flash address l...

  • Page 541

    Flexible static memory controller (fsmc) rm0008 541/1128 docid13902 rev 15 21.6.2 nand flash / pc card supported memories and transactions table 133 below shows the supported devices, access modes and transactions. Transactions not allowed (or not supported) by the nand flash / pc card controller ap...

  • Page 542

    Docid13902 rev 15 542/1128 rm0008 flexible static memory controller (fsmc) 555 figure 204. Nand/pc card controller timing for common memory access 1. Noe remains high (inactive) during write access. Nwe remains high (inactive) during read access. 2. Ncex goes low as soon as nand access is requested ...

  • Page 543

    Flexible static memory controller (fsmc) rm0008 543/1128 docid13902 rev 15 the nand flash device is active during the write strobe (low pulse on nwe), thus the written bytes are interpreted as the start address for read operations. Using the attribute memory space makes it possible to use a differen...

  • Page 544

    Docid13902 rev 15 544/1128 rm0008 flexible static memory controller (fsmc) 555 timing definition, where atthold ≥ 7 (providing that (7+1) × hclk = 112 ns > t wb max). This guarantees that nce remains low until r/nb goes low and high again (only requested for nand flash memories where nce is not don’...

  • Page 545

    Flexible static memory controller (fsmc) rm0008 545/1128 docid13902 rev 15 1. Enable the eccen bit in the fsmc_pcr2/3 register. 2. Write data to the nand flash memory page. While the nand page is written, the ecc block computes the ecc value. 3. Read the ecc value available in the fsmc_eccr2/3 regis...

  • Page 546

    Docid13902 rev 15 546/1128 rm0008 flexible static memory controller (fsmc) 555 transfers at even addresses: nce1 will be asserted low, nce2 will be asserted high and only the even bytes will be valid. • accesses to i/o space can be performed either through ahb 8-bit or 16-bit accesses. The fsmc bank...

  • Page 547

    Flexible static memory controller (fsmc) rm0008 547/1128 docid13902 rev 15 xxwaitx >= 4 + max_wait_assertion_time/hclk where max_wait_assertion_time is the maximum time taken by nwait to go low once noe/nwe or niord/niowr is low. After the de-assertion of nwait, the fsmc extends the wait phase for 4...

  • Page 548

    Docid13902 rev 15 548/1128 rm0008 flexible static memory controller (fsmc) 555 fifo status and interrupt register 2..4 (fsmc_sr2..4) address offset: 0xa000 0000 + 0x44 + 0x20 * (x-1), x = 2..4 reset value: 0x0000 0040 this register contains information about fifo status and interrupt. The fsmc has a...

  • Page 549

    Flexible static memory controller (fsmc) rm0008 549/1128 docid13902 rev 15 common memory space timing register 2..4 (fsmc_pmem2..4) address offset: address: 0xa000 0000 + 0x48 + 0x20 * (x – 1), x = 2..4 reset value: 0xfcfc fcfc each fsmc_pmemx (x = 2..4) read/write register contains the timing infor...

  • Page 550

    Docid13902 rev 15 550/1128 rm0008 flexible static memory controller (fsmc) 555 attribute memory space timing registers 2..4 (fsmc_patt2..4) address offset: 0xa000 0000 + 0x4c + 0x20 * (x – 1), x = 2..4 reset value: 0xfcfc fcfc each fsmc_pattx (x = 2..4) read/write register contains the timing inform...

  • Page 551

    Flexible static memory controller (fsmc) rm0008 551/1128 docid13902 rev 15 i/o space timing register 4 (fsmc_pio4) address offset: 0xa000 0000 + 0xb0 reset value: 0xfcfcfcfc the fsmc_pio4 read/write registers contain the timing information used to gain access to the i/o space of the 16-bit pc card/c...

  • Page 552

    Docid13902 rev 15 552/1128 rm0008 flexible static memory controller (fsmc) 555 ecc result registers 2/3 (fsmc_eccr2/3) address offset: 0xa000 0000 + 0x54 + 0x20 * (x – 1), x = 2 or 3 reset value: 0x0000 0000 these registers contain the current error correction code value computed by the ecc computat...

  • Page 553

    Flexible static memory controller (fsmc) rm0008 553/1128 docid13902 rev 15 bits 31:0 eccx: ecc result this field provides the value computed by the ecc computation logic. Table 135 hereafter describes the contents of these bit fields. Table 135. Ecc result relevant bits eccps[2:0] page size in bytes...

  • Page 554

    Docid13902 rev 15 554/1128 rm0008 flexible static memory controller (fsmc) 555 21.6.9 fsmc register map the following table summarizes the fsmc registers. Table 136. Fsmc register map offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000 fsmc_bcr1...

  • Page 555

    Flexible static memory controller (fsmc) rm0008 555/1128 docid13902 rev 15 refer to table 3 on page 51 for the register boundary addresses. 0xa000 00a8 fsmc_pmem4 memhizx memholdx memwaitx memsetx 0xa000 006c fsmc_patt2 atthizx attholdx attwaitx attsetx 0xa000 008c fsmc_patt3 atthizx attholdx attwai...

  • Page 556: 22.1

    Docid13902 rev 15 556/1128 rm0008 secure digital input/output interface (sdio) 612 22 secure digital input/output interface (sdio) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices ...

  • Page 557: 22.2

    Secure digital input/output interface (sdio) rm0008 557/1128 docid13902 rev 15 interface using a protocol that utilizes the existing mmc access primitives. The interface electrical and signaling definition is as defined in the mmc reference. The multimediacard/sd bus connects cards to the controller...

  • Page 558

    Docid13902 rev 15 558/1128 rm0008 secure digital input/output interface (sdio) 612 figure 208. Sdio (multiple) block write operation note: the sdio will not send any data as long as the busy signal is asserted (sdio_d0 pulled low). Figure 209. Sdio sequential read operation figure 210. Sdio sequenti...

  • Page 559: 22.3

    Secure digital input/output interface (sdio) rm0008 559/1128 docid13902 rev 15 22.3 sdio functional description the sdio consists of two parts: • the sdio adapter block provides all functions specific to the mmc/sd/sd i/o card such as the clock generation unit, command and data transfer. • the ahb i...

  • Page 560

    Docid13902 rev 15 560/1128 rm0008 secure digital input/output interface (sdio) 612 22.3.1 sdio adapter figure 212 shows a simplified block diagram of an sdio adapter. Figure 212. Sdio adapter the sdio adapter is a multimedia/secure digital memory card bus master that provides an interface to a multi...

  • Page 561

    Secure digital input/output interface (sdio) rm0008 561/1128 docid13902 rev 15 control unit the control unit contains the power management functions and the clock divider for the memory card clock. There are three power phases: • power-off • power-up • power-on figure 213. Control unit the control u...

  • Page 562

    Docid13902 rev 15 562/1128 rm0008 secure digital input/output interface (sdio) 612 figure 214. Sdio adapter command path • command path state machine (cpsm) – when the command register is written to and the enable bit is set, command transfer starts. When the command has been sent, the command path ...

  • Page 563

    Secure digital input/output interface (sdio) rm0008 563/1128 docid13902 rev 15 figure 215. Command path state machine (cpsm) when the wait state is entered, the command timer starts running. If the timeout is reached before the cpsm moves to the receive state, the timeout flag is set and the idle st...

  • Page 564

    Docid13902 rev 15 564/1128 rm0008 secure digital input/output interface (sdio) 612 figure 216. Sdio command transfer • command format – command: a command is a token that starts an operation. Command are sent from the host either to a single card (addressed command) or to all connected cards (broadc...

  • Page 565

    Secure digital input/output interface (sdio) rm0008 565/1128 docid13902 rev 15 the command register contains the command index (six bits sent to a card) and the command type. These determine whether the command requires a response, and whether the response is 48 or 136 bits long (see section 22.9.4 ...

  • Page 566

    Docid13902 rev 15 566/1128 rm0008 secure digital input/output interface (sdio) 612 data path the data path subunit transfers data to and from cards. Figure 217 shows a block diagram of the data path. Figure 217. Data path the card databus width can be programmed using the clock control register. If ...

  • Page 567

    Secure digital input/output interface (sdio) rm0008 567/1128 docid13902 rev 15 figure 218. Data path state machine (dpsm) • idle: the data path is inactive, and the sdio_d[7:0] outputs are in hi-z. When the data control register is written and the enable bit is set, the dpsm loads the data counter w...

  • Page 568

    Docid13902 rev 15 568/1128 rm0008 secure digital input/output interface (sdio) 612 note: the dpsm remains in the wait_s state for at least two clock periods to meet the n wr timing requirements, where n wr is the number of clock cycles between the reception of the card response and the start of the ...

  • Page 569

    Secure digital input/output interface (sdio) rm0008 569/1128 docid13902 rev 15 depending on the txact and rxact flags, the fifo can be disabled, transmit enabled, or receive enabled. Txact and rxact are driven by the data path subunit and are mutually exclusive: – the transmit fifo refers to the tra...

  • Page 570

    Docid13902 rev 15 570/1128 rm0008 secure digital input/output interface (sdio) 612 22.3.2 sdio ahb interface the ahb interface generates the interrupt and dma requests, and accesses the sdio adapter registers and the data fifo. It consists of a data path, register decoder, and interrupt/dma logic. S...

  • Page 571: 22.4

    Secure digital input/output interface (sdio) rm0008 571/1128 docid13902 rev 15 1. Do the card identification process 2. Increase the sdio_ck frequency 3. Select the card by sending cmd7 4. Configure the dma2 as follows: a) enable dma2 controller and clear any pending interrupts b) program the dma2_c...

  • Page 572

    Docid13902 rev 15 572/1128 rm0008 secure digital input/output interface (sdio) 612 22.4.3 operating voltage range validation all cards can communicate with the sdio card host using any operating voltage within the specification range. The supported minimum and maximum v dd values are defined in the ...

  • Page 573

    Secure digital input/output interface (sdio) rm0008 573/1128 docid13902 rev 15 1. The bus is activated. 2. The sdio card host broadcasts sd_app_op_cond (acmd41). 3. The cards respond with the contents of their operation condition registers. 4. The incompatible cards are placed in the inactive state....

  • Page 574

    Docid13902 rev 15 574/1128 rm0008 secure digital input/output interface (sdio) 612 select a different card), which will place the card in the disconnect state and release the sdio_d line(s) without interrupting the write operation. When reselecting the card, it will reactivate busy indication by pul...

  • Page 575

    Secure digital input/output interface (sdio) rm0008 575/1128 docid13902 rev 15 the maximum clock frequency for a stream write operation is given by the following equation fields of the card-specific data register: • maximumspeed = maximum write frequency • transpeed = maximum data transfer rate • wr...

  • Page 576

    Docid13902 rev 15 576/1128 rm0008 secure digital input/output interface (sdio) 612 stream read (multimediacard only) read_dat_until_stop (cmd11) controls a stream-oriented data transfer. This command instructs the card to send its data, starting at a specified address, until the sdio card host sends...

  • Page 577

    Secure digital input/output interface (sdio) rm0008 577/1128 docid13902 rev 15 the card indicates that an erase is in progress by holding sdio_d low. The actual erase time may be quite long, and the host may issue cmd7 to deselect the card. 22.4.9 wide bus selection or deselection wide bus (4-bit bu...

  • Page 578

    Docid13902 rev 15 578/1128 rm0008 secure digital input/output interface (sdio) 612 the card must be selected before using it. The card lock/unlock commands have the structure and bus transaction types of a regular single-block write command. The transferred data block includes all of the required in...

  • Page 579

    Secure digital input/output interface (sdio) rm0008 579/1128 docid13902 rev 15 resetting the password 1. Select a card (select/deselect_card, cmd7), if none is already selected. 2. Define the block length (set_blocklen, cmd16) to send, given by the 8-bit card lock/unlock mode, the 8-bit pwd_len, and...

  • Page 580

    Docid13902 rev 15 580/1128 rm0008 secure digital input/output interface (sdio) 612 the unlocking function is only valid for the current power session. When the pwd field is not clear, the card is locked automatically on the next power-up. An attempt to unlock an unlocked card fails and the lock_unlo...

  • Page 581

    Secure digital input/output interface (sdio) rm0008 581/1128 docid13902 rev 15 table 145. Card status bits identifier type value description clear condition 31 address_ out_of_range e r x ’0’= no error ’1’= error the command address argument was out of the allowed range for this card. A multiple blo...

  • Page 582

    Docid13902 rev 15 582/1128 rm0008 secure digital input/output interface (sdio) 612 19 error e x ’0’= no error ’1’= error (undefined by the standard) a generic card error related to the (and detected during) execution of the last host command (e.G. Read or write failures). C 18 reserved 17 reserved 1...

  • Page 583

    Secure digital input/output interface (sdio) rm0008 583/1128 docid13902 rev 15 22.4.12 sd status register the sd status contains status bits that are related to the sd memory card proprietary features and may be used for future application-specific usage. The size of the sd status is one data block ...

  • Page 584

    Docid13902 rev 15 584/1128 rm0008 secure digital input/output interface (sdio) 612 size_of_protected_area setting this field differs between standard- and high-capacity cards. In the case of a standard-capacity card, the capacity of protected area is calculated as follows: protected area = size_of_p...

  • Page 585

    Secure digital input/output interface (sdio) rm0008 585/1128 docid13902 rev 15 performance_move this 8-bit field indicates pm (performance move) and the value can be set by 1 [mb/sec] steps. If the card does not move used rus (recording units), pm should be considered as infinity. Setting the field ...

  • Page 586

    Docid13902 rev 15 586/1128 rm0008 secure digital input/output interface (sdio) 612 the maximum au size, which depends on the card capacity, is defined in table 150 . The card can be set to any au size between ru size and maximum au size. Erase_size this 16-bit field indicates n erase . When n erase ...

  • Page 587

    Secure digital input/output interface (sdio) rm0008 587/1128 docid13902 rev 15 erase_offset this 2-bit field indicates t offset and one of four values can be selected. This field is meaningless if the erase_size and erase_timeout fields are set to 0. 22.4.13 sd i/o mode sd i/o interrupts to allow th...

  • Page 588

    Docid13902 rev 15 588/1128 rm0008 secure digital input/output interface (sdio) 612 suspend/resume operation on the mmc/sd bus, the mmc/sd module performs the following steps: 1. Determines the function currently using the sdio_d [3:0] line(s) 2. Requests the lower-priority or slower transaction to s...

  • Page 589

    Secure digital input/output interface (sdio) rm0008 589/1128 docid13902 rev 15 the bus transaction for a gen_cmd is the same as the single-block read or write commands (write_block, cmd24 or read_single_block,cmd17). In this case, the argument denotes the direction of the data transfer rather than t...

  • Page 590

    Docid13902 rev 15 590/1128 rm0008 secure digital input/output interface (sdio) 612 table 155. Block-oriented write protection commands cmd index type argument response format abbreviation description cmd28 ac [31:0] data address r1b set_write_prot if the card has write protection features, this comm...

  • Page 591: 22.5 Response

    Secure digital input/output interface (sdio) rm0008 591/1128 docid13902 rev 15 22.5 response formats all responses are sent via the mccmd command line sdio_cmd. The response transmission always starts with the left bit of the bit string corresponding to the response code word. The code length depend...

  • Page 592

    Docid13902 rev 15 592/1128 rm0008 secure digital input/output interface (sdio) 612 22.5.1 r1 (normal response command) code length = 48 bits. The 45:40 bits indicate the index of the command to be responded to, this value being interpreted as a binary-coded number (between 0 and 63). The status of t...

  • Page 593

    Secure digital input/output interface (sdio) rm0008 593/1128 docid13902 rev 15 22.5.5 r4 (fast i/o) code length: 48 bits. The argument field contains the rca of the addressed card, the register address to be read out or written to, and its content. 22.5.6 r4b for sd i/o only: an sdio card receiving ...

  • Page 594

    Docid13902 rev 15 594/1128 rm0008 secure digital input/output interface (sdio) 612 once an sd i/o card has received a cmd5, the i/o portion of that card is enabled to respond normally to all further commands. This i/o enable of the function within the i/o card will remain set until a reset, power cy...

  • Page 595: 22.6

    Secure digital input/output interface (sdio) rm0008 595/1128 docid13902 rev 15 the card [23:8] status bits are changed when cmd3 is sent to an i/o-only card. In this case, the 16 bits of response are the sd i/o-only values: • bit [15] com_crc_error • bit [14] illegal_command • bit [13] error • bits ...

  • Page 596: 22.7

    Docid13902 rev 15 596/1128 rm0008 secure digital input/output interface (sdio) 612 as sdio_ck is stopped, any command can be issued to the card. During a read/wait interval, the sdio can detect sdio interrupts on sdio_d1. 22.6.3 sdio suspend/resume operation while sending data to the card, the sdio ...

  • Page 597: 22.8 Hw

    Secure digital input/output interface (sdio) rm0008 597/1128 docid13902 rev 15 when ‘0’ is received on the cmd line, the cpsm enters the idle state. No new command can be sent for 7 bit cycles. Then, for the last 5 cycles (out of the 7) the cmd line is driven to ‘1’ in push-pull mode. 22.7.3 ce-ata ...

  • Page 598

    Docid13902 rev 15 598/1128 rm0008 secure digital input/output interface (sdio) 612 22.9.1 sdio power control register (sdio_power) address offset: 0x00 reset value: 0x0000 0000 note: at least seven hclk clock periods are needed between two write accesses to this register. 22.9.2 sdi clock control re...

  • Page 599

    Secure digital input/output interface (sdio) rm0008 599/1128 docid13902 rev 15 note: while the sd/sdio card or multimediacard is in identification mode, the sdio_ck frequency must be less than 400 khz. The clock frequency can be changed to the maximum card bus frequency when relative card addresses ...

  • Page 600

    Docid13902 rev 15 600/1128 rm0008 secure digital input/output interface (sdio) 612 22.9.4 sdio command register (sdio_cmd) address offset: 0x0c reset value: 0x0000 0000 the sdio_cmd register contains the command index and command type bits. The command index is sent to a card as part of a command me...

  • Page 601

    Secure digital input/output interface (sdio) rm0008 601/1128 docid13902 rev 15 argument can vary according to the type of response: the software will distinguish the type of response according to the sent command. Ce-ata devices send only short responses. 22.9.5 sdio command response register (sdio_...

  • Page 602

    Docid13902 rev 15 602/1128 rm0008 secure digital input/output interface (sdio) 612 22.9.7 sdio data timer register (sdio_dtimer) address offset: 0x24 reset value: 0x0000 0000 the sdio_dtimer register contains the data timeout period, in card bus clock periods. A counter loads the value from the sdio...

  • Page 603

    Secure digital input/output interface (sdio) rm0008 603/1128 docid13902 rev 15 22.9.9 sdio data control register (sdio_dctrl) address offset: 0x2c reset value: 0x0000 0000 the sdio_dctrl register control the data path state machine (dpsm). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 ...

  • Page 604

    Docid13902 rev 15 604/1128 rm0008 secure digital input/output interface (sdio) 612 note: at least seven hclk clock periods are needed between two write accesses to this register. 22.9.10 sdio data counter register (sdio_dcount) address offset: 0x30 reset value: 0x0000 0000 the sdio_dcount register l...

  • Page 605

    Secure digital input/output interface (sdio) rm0008 605/1128 docid13902 rev 15 22.9.11 sdio status register (sdio_sta) address offset: 0x34 reset value: 0x0000 0000 the sdio_sta register is a read-only register. It contains two types of flag: • static flags (bits [23:22,10:0]): these bits remain ass...

  • Page 606

    Docid13902 rev 15 606/1128 rm0008 secure digital input/output interface (sdio) 612 22.9.12 sdio interrupt clear register (sdio_icr) address offset: 0x38 reset value: 0x0000 0000 the sdio_icr register is a write-only register. Writing a bit with 1b clears the corresponding bit in the sdio_sta status ...

  • Page 607

    Secure digital input/output interface (sdio) rm0008 607/1128 docid13902 rev 15 bit 7 cmdsentc: cmdsent flag clear bit set by software to clear the cmdsent flag. 0: cmdsent not cleared 1: cmdsent cleared bit 6 cmdrendc: cmdrend flag clear bit set by software to clear the cmdrend flag. 0: cmdrend not ...

  • Page 608

    Docid13902 rev 15 608/1128 rm0008 secure digital input/output interface (sdio) 612 22.9.13 sdio mask register (sdio_mask) address offset: 0x3c reset value: 0x0000 0000 the interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1b. 31 3...

  • Page 609

    Secure digital input/output interface (sdio) rm0008 609/1128 docid13902 rev 15 bit 16 txfifofie: tx fifo full interrupt enable set and cleared by software to enable/disable interrupt caused by tx fifo full. 0: tx fifo full interrupt disabled 1: tx fifo full interrupt enabled bit 15 rxfifohfie: rx fi...

  • Page 610

    Docid13902 rev 15 610/1128 rm0008 secure digital input/output interface (sdio) 612 22.9.14 sdio fifo counter register (sdio_fifocnt) address offset: 0x48 reset value: 0x0000 0000 the sdio_fifocnt register contains the remaining number of words to be written to or read from the fifo. The fifo counter...

  • Page 611

    Secure digital input/output interface (sdio) rm0008 611/1128 docid13902 rev 15 22.9.15 sdio data fifo register (sdio_fifo) address offset: 0x80 reset value: 0x0000 0000 the receive and transmit fifos can be read or written as 32-bit wide registers. The fifos contain 32 entries on 32 sequential addre...

  • Page 612

    Docid13902 rev 15 612/1128 rm0008 secure digital input/output interface (sdio) 612 refer to table 3 on page 51 for the register boundary addresses. 0x30 sdio_d- count reserved datacount 0x34 sdio_sta reserved cea taend s d io it rx da vl txda vl rxfifo e txfi foe rxfif o f txf ifo f rxfif o hf txfi ...

  • Page 613: 23.1 Usb

    Universal serial bus full-speed device interface (usb) rm0008 613/1128 docid13902 rev 15 23 universal serial bus full-speed device interface (usb) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-...

  • Page 614

    Docid13902 rev 15 614/1128 rm0008 universal serial bus full-speed device interface (usb) 644 figure 219. Usb peripheral block diagram the usb peripheral provides an usb compliant connection between the host pc and the function implemented by the microcontroller. Data transfer between the host pc and...

  • Page 615

    Universal serial bus full-speed device interface (usb) rm0008 615/1128 docid13902 rev 15 each endpoint is associated with a buffer description block indicating where the endpoint related memory area is located, how large it is or how many bytes must be transmitted. When a token for a valid function/...

  • Page 616: 23.4 Programming

    Docid13902 rev 15 616/1128 rm0008 universal serial bus full-speed device interface (usb) 644 endpoints* in any combination. For example the usb peripheral can be programmed to have 4 double buffer endpoints and 8 single-buffer/mono-directional endpoints. • control registers: these are the registers ...

  • Page 617

    Universal serial bus full-speed device interface (usb) rm0008 617/1128 docid13902 rev 15 23.4.2 system and power-on reset upon system and power-on reset, the first operation the application software should perform is to provide all required clock signals to the usb peripheral and subsequently de-ass...

  • Page 618

    Docid13902 rev 15 618/1128 rm0008 universal serial bus full-speed device interface (usb) 644 back-to-back accesses. The usb peripheral logic uses a dedicated clock. The frequency of this dedicated clock is fixed by the requirements of the usb standard at 48 mhz, and this can be different from the cl...

  • Page 619

    Universal serial bus full-speed device interface (usb) rm0008 619/1128 docid13902 rev 15 each packet buffer is used either during reception or transmission starting from the bottom. The usb peripheral will never change the contents of memory locations adjacent to the allocated memory buffers; if a p...

  • Page 620

    Docid13902 rev 15 620/1128 rm0008 universal serial bus full-speed device interface (usb) 644 indicating a flow control condition: the usb host will retry the transaction until it succeeds. It is mandatory to execute the sequence of operations in the above mentioned order to avoid losing the notifica...

  • Page 621

    Universal serial bus full-speed device interface (usb) rm0008 621/1128 docid13902 rev 15 processed. After the received data is processed, the application software should set the stat_rx bits to ‘11 (valid) in the usb_epnr, enabling further transactions. While the stat_rx bits are equal to ‘10 (nak),...

  • Page 622

    Docid13902 rev 15 622/1128 rm0008 universal serial bus full-speed device interface (usb) 644 bulk endpoint type is the most suited model. This is because the host schedules bulk transactions so as to fill all the available bandwidth in the frame, maximizing the actual transfer rate as long as the us...

  • Page 623

    Universal serial bus full-speed device interface (usb) rm0008 623/1128 docid13902 rev 15 since the swapped buffer management requires the usage of all 4 buffer description table locations hosting the address pointer and the length of the allocated memory buffers, the usb_epnr registers used to imple...

  • Page 624

    Docid13902 rev 15 624/1128 rm0008 universal serial bus full-speed device interface (usb) 644 double-buffering feature for a bulk endpoint is activated by: • writing ep_type bit field at ‘00 in its usb_epnr register, to define the endpoint as a bulk, and • setting ep_kind bit at ‘1 (dbl_buf), in the ...

  • Page 625

    Universal serial bus full-speed device interface (usb) rm0008 625/1128 docid13902 rev 15 the application software can always override the special flow control implemented for double-buffered bulk endpoints, writing an explicit status different from ‘11 (valid) into the stat bit pair of the related u...

  • Page 626

    Docid13902 rev 15 626/1128 rm0008 universal serial bus full-speed device interface (usb) 644 as it happens with double-buffered bulk endpoints, the usb_epnr registers used to implement isochronous endpoints are forced to be used as unidirectional ones. In case it is required to have isochronous endp...

  • Page 627

    Universal serial bus full-speed device interface (usb) rm0008 627/1128 docid13902 rev 15 when an usb event occurs while the device is in suspend mode, the resume procedure must be invoked to restore nominal clocks and regain normal usb behavior. Particular care must be taken to insure that this proc...

  • Page 628: 23.5 Usb

    Docid13902 rev 15 628/1128 rm0008 universal serial bus full-speed device interface (usb) 644 23.5 usb registers the usb peripheral registers can be divided into the following groups: • common registers: interrupt and control registers • endpoint registers: endpoint configuration and status • buffer ...

  • Page 629

    Universal serial bus full-speed device interface (usb) rm0008 629/1128 docid13902 rev 15 bit 11 suspm: suspend mode interrupt mask 0: suspend mode request (susp) interrupt disabled. 1: susp interrupt enabled, an interrupt request is generated when the corresponding bit in the usb_istr register is se...

  • Page 630

    Docid13902 rev 15 630/1128 rm0008 universal serial bus full-speed device interface (usb) 644 usb interrupt status register (usb_istr) address offset: 0x44 reset value: 0x0000 0000 this register contains the status of all the interrupt sources allowing application software to determine, which events ...

  • Page 631

    Universal serial bus full-speed device interface (usb) rm0008 631/1128 docid13902 rev 15 the following describes each bit in detail: bit 15 ctr: correct transfer this bit is set by the hardware to indicate that an endpoint has successfully completed a transaction; using dir and ep_id bits software c...

  • Page 632

    Docid13902 rev 15 632/1128 rm0008 universal serial bus full-speed device interface (usb) 644 bit 10 reset: usb reset request set when the usb peripheral detects an active usb reset signal at its inputs. The usb peripheral, in response to a reset, just resets its internal protocol state machine, gene...

  • Page 633

    Universal serial bus full-speed device interface (usb) rm0008 633/1128 docid13902 rev 15 usb frame number register (usb_fnr) address offset: 0x48 reset value: 0x0xxx where x is undefined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rxdp rxdm lck lsof[1:0] fn[10:0] r r r r r r r r r r r r r r r r bit 15 rxd...

  • Page 634

    Docid13902 rev 15 634/1128 rm0008 universal serial bus full-speed device interface (usb) 644 usb device address (usb_daddr) address offset: 0x4c reset value: 0x0000 buffer table address (usb_btable) address offset: 0x50 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ef add6 add5 ...

  • Page 635

    Universal serial bus full-speed device interface (usb) rm0008 635/1128 docid13902 rev 15 23.5.2 endpoint-specific registers the number of these registers varies according to the number of endpoints that the usb peripheral is designed to handle. The usb peripheral supports up to 8 bidirectional endpo...

  • Page 636

    Docid13902 rev 15 636/1128 rm0008 universal serial bus full-speed device interface (usb) 644 bit 15 ctr_rx: correct transfer for reception this bit is set by the hardware when an out/setup transaction is successfully completed on this endpoint; the software can only clear this bit. If the ctrm bit i...

  • Page 637

    Universal serial bus full-speed device interface (usb) rm0008 637/1128 docid13902 rev 15 bits 10:9 ep_type[1:0]: endpoint type these bits configure the behavior of this endpoint as described in table 174: endpoint type encoding on page 638 . Endpoint 0 must always be a control endpoint and each usb ...

  • Page 638

    Docid13902 rev 15 638/1128 rm0008 universal serial bus full-speed device interface (usb) 644 bit 6 dtog_tx: data toggle, for transmission transfers if the endpoint is non-isochronous, this bit contains the required value of the data toggle bit (0=data0, 1=data1) for the next data packet to be transm...

  • Page 639

    Universal serial bus full-speed device interface (usb) rm0008 639/1128 docid13902 rev 15 10 iso 11 interrupt table 175. Endpoint kind meaning ep_type[1:0] ep_kind meaning 00 bulk dbl_buf 01 control status_out 10 iso not used 11 interrupt not used table 176. Transmission status encoding stat_tx[1:0] ...

  • Page 640

    Docid13902 rev 15 640/1128 rm0008 universal serial bus full-speed device interface (usb) 644 23.5.3 buffer descriptor table although the buffer descriptor table is located inside the packet buffer memory, its entries can be considered as additional registers used to configure the location and size o...

  • Page 641

    Universal serial bus full-speed device interface (usb) rm0008 641/1128 docid13902 rev 15 transmission byte count n (usb_countn_tx) address offset: [usb_btable] + n*16 + 4 usb local address: [usb_btable] + n*8 + 2 note: double-buffered and isochronous in endpoints have two usb_countn_tx registers: na...

  • Page 642

    Docid13902 rev 15 642/1128 rm0008 universal serial bus full-speed device interface (usb) 644 reception byte count n (usb_countn_rx) address offset: [usb_btable] + n*16 + 12 usb local address: [usb_btable] + n*8 + 6 this table location is used to store two different values, both required during packe...

  • Page 643

    Universal serial bus full-speed device interface (usb) rm0008 643/1128 docid13902 rev 15 23.5.4 usb register map the table below provides the usb register map and reset values. Table 177. Definition of allocated buffer memory value of num_block[4:0] memory allocated when bl_size=0 memory allocated w...

  • Page 644

    Docid13902 rev 15 644/1128 rm0008 universal serial bus full-speed device interface (usb) 644 refer to table 3 on page 51 for the register boundary addresses. 0x10 usb_ep4r reserved ctr_rx dt og_ rx stat_ rx [1:0] se tu p ep type [1:0] ep _ k in d ct r _ t x dt og_tx stat_ tx [1:0] ea[3:0] reset valu...

  • Page 645: 24.1 Bxcan

    Controller area network (bxcan) rm0008 645/1128 docid13902 rev 15 24 controller area network (bxcan) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102xx a...

  • Page 646: 24.3

    Docid13902 rev 15 646/1128 rm0008 controller area network (bxcan) 689 time-triggered communication option • disable automatic retransmission mode • 16-bit free running timer • time stamp sent in last two data bytes management • maskable interrupts • software-efficient mailbox mapping at a unique add...

  • Page 647

    Controller area network (bxcan) rm0008 647/1128 docid13902 rev 15 figure 221. Can network topology 24.3.1 can 2.0b active core the bxcan module handles the transmission and the reception of can messages fully autonomously. Standard identifiers (11-bit) and extended identifiers (29-bit) are fully sup...

  • Page 648: 24.4

    Docid13902 rev 15 648/1128 rm0008 controller area network (bxcan) 689 figure 222. Dual can block diagram (connectivity devices) 24.4 bxcan operating modes bxcan has three main operating modes: initialization, normal and sleep. After a hardware reset, bxcan is in sleep mode to reduce power consumptio...

  • Page 649

    Controller area network (bxcan) rm0008 649/1128 docid13902 rev 15 mode. Before entering normal mode bxcan always has to synchronize on the can bus. To synchronize, bxcan waits until the can bus is idle, this means 11 consecutive recessive bits have been monitored on canrx. 24.4.1 initialization mode...

  • Page 650: 24.5 Test

    Docid13902 rev 15 650/1128 rm0008 controller area network (bxcan) 689 bxcan can be woken up (exit sleep mode) either by software clearing the sleep bit or on detection of can bus activity. On can bus activity detection, hardware automatically performs the wakeup sequence by clearing the sleep bit if...

  • Page 651

    Controller area network (bxcan) rm0008 651/1128 docid13902 rev 15 remain in recessive state. Silent mode can be used to analyze the traffic on a can bus without affecting it by the transmission of dominant bits (acknowledge bits, error frames). Figure 224. Bxcan in silent mode 24.5.2 loop back mode ...

  • Page 652: 24.6 Debug

    Docid13902 rev 15 652/1128 rm0008 controller area network (bxcan) 689 figure 226. Bxcan in combined mode 24.6 debug mode when the microcontroller enters the debug mode (cortex ® -m3 core halted), the bxcan continues to work normally or stops, depending on: • the dbg_can1_stop bit for can1 or the dbg...

  • Page 653

    Controller area network (bxcan) rm0008 653/1128 docid13902 rev 15 the transmit mailboxes can be configured as a transmit fifo by setting the txfp bit in the can_mcr register. In this mode the priority order is given by the transmit request order. This mode is very useful for segmented transmission. ...

  • Page 654

    Docid13902 rev 15 654/1128 rm0008 controller area network (bxcan) 689 24.7.2 time triggered communication mode in this mode, the internal counter of the can hardware is activated and used to generate the time stamp value stored in the can_rdtxr/can_tdtxr registers, respectively (for rx and tx mailbo...

  • Page 655

    Controller area network (bxcan) rm0008 655/1128 docid13902 rev 15 fifo management starting from the empty state, the first valid message received is stored in the fifo which becomes pending_1. The hardware signals the event setting the fmp[1:0] bits in the can_rfr register to the value 01b. The mess...

  • Page 656

    Docid13902 rev 15 656/1128 rm0008 controller area network (bxcan) 689 otherwise needed to perform filtering by software. Each filter bankx consists of two 32-bit registers, can_fxr0 and can_fxr1. Scalable width to optimize and adapt the filters to the application needs, each filter bank can be scale...

  • Page 657

    Controller area network (bxcan) rm0008 657/1128 docid13902 rev 15 figure 229. Filter bank scale configuration - register organization filter match index once a message has been received in the fifo it is available to the application. Typically, application data is copied into sram locations. To copy...

  • Page 658

    Docid13902 rev 15 658/1128 rm0008 controller area network (bxcan) 689 figure 230. Example of filter numbering filter priority rules depending on the filter combination it may occur that an identifier passes successfully through several filters. In this case the filter match value stored in the recei...

  • Page 659

    Controller area network (bxcan) rm0008 659/1128 docid13902 rev 15 figure 231. Filtering mechanism - example the example above shows the filtering principle of the bxcan. On reception of a message, the identifier is compared first with the filters configured in identifier list mode. If there is a mat...

  • Page 660

    Docid13902 rev 15 660/1128 rm0008 controller area network (bxcan) 689 receive mailbox when a message has been received, it is available to the software in the fifo output mailbox. Once the software has handled the message (e.G. Read it) the software must release the fifo output mailbox by means of t...

  • Page 661

    Controller area network (bxcan) rm0008 661/1128 docid13902 rev 15 24.7.6 error management the error management as described in the can protocol is handled entirely by hardware using a transmit error counter (tec value, in can_esr register) and a receive error counter (rec value, in the can_esr regis...

  • Page 662

    Docid13902 rev 15 662/1128 rm0008 controller area network (bxcan) 689 a valid edge is defined as the first transition in a bit time from dominant to recessive bus level provided the controller itself does not send a recessive bit. If a valid edge is detected in bs1 instead of sync_seg, bs1 is extend...

  • Page 663: 24.8 Bxcan

    Controller area network (bxcan) rm0008 663/1128 docid13902 rev 15 figure 234. Can frames 24.8 bxcan interrupts four interrupt vectors are dedicated to bxcan. Each interrupt source can be independently enabled or disabled by means of the can interrupt enable register (can_ier). Data frame or remote f...

  • Page 664

    Docid13902 rev 15 664/1128 rm0008 controller area network (bxcan) 689 figure 235. Event flags and interrupt generation • the transmit interrupt can be generated by the following events: – transmit mailbox 0 becomes empty, rqcp0 bit in the can_tsr register set. – transmit mailbox 1 becomes empty, rqc...

  • Page 665: 24.9 Can

    Controller area network (bxcan) rm0008 665/1128 docid13902 rev 15 – wakeup condition, sof monitored on the can rx signal. – entry into sleep mode. 24.9 can registers the peripheral registers have to be accessed by words (32 bits). 24.9.1 register access protection erroneous access to certain configu...

  • Page 666

    Docid13902 rev 15 666/1128 rm0008 controller area network (bxcan) 689 bit 7 ttcm: time triggered communication mode 0: time triggered communication mode disabled. 1: time triggered communication mode enabled note: for more information on time triggered communication mode, please refer to section 24....

  • Page 667

    Controller area network (bxcan) rm0008 667/1128 docid13902 rev 15 can master status register (can_msr) address offset: 0x04 reset value: 0x0000 0c02 bit 0 inrq : initialization request the software clears this bit to switch the hardware into normal mode. Once 11 consecutive recessive bits have been ...

  • Page 668

    Docid13902 rev 15 668/1128 rm0008 controller area network (bxcan) 689 can transmit status register (can_tsr) address offset: 0x08 reset value: 0x1c00 0000 bit 2 erri : error interrupt this bit is set by hardware when a bit of the can_esr has been set on error detection and the corresponding interrup...

  • Page 669

    Controller area network (bxcan) rm0008 669/1128 docid13902 rev 15 bit 26 tme0 : transmit mailbox 0 empty this bit is set by hardware when no transmit request is pending for mailbox 0. Bits 25:24 code[1:0] : mailbox code in case at least one transmit mailbox is free, the code value is equal to the nu...

  • Page 670

    Docid13902 rev 15 670/1128 rm0008 controller area network (bxcan) 689 can receive fifo 0 register (can_rf0r) address offset: 0x0c reset value: 0x0000 0000 bit 7 abrq0 : abort request for mailbox0 set by software to abort the transmission request for the corresponding mailbox. Cleared by hardware whe...

  • Page 671

    Controller area network (bxcan) rm0008 671/1128 docid13902 rev 15 can receive fifo 1 register (can_rf1r) address offset: 0x10 reset value: 0x0000 0000 can interrupt enable register (can_ier) address offset: 0x14 reset value: 0x0000 0000 bits 1:0 fmp0[1:0] : fifo 0 message pending these bits indicate...

  • Page 672

    Docid13902 rev 15 672/1128 rm0008 controller area network (bxcan) 689 bits 31:18 reserved, must be kept at reset value. Bit 17 slkie : sleep interrupt enable 0: no interrupt when slaki bit is set. 1: interrupt generated when slaki bit is set. Bit 16 wkuie : wakeup interrupt enable 0: no interrupt wh...

  • Page 673

    Controller area network (bxcan) rm0008 673/1128 docid13902 rev 15 can error status register (can_esr) address offset: 0x18 reset value: 0x0000 0000 bit 2 ffie0 : fifo full interrupt enable 0: no interrupt when full bit is set. 1: interrupt generated when full bit is set. Bit 1 fmpie0 : fifo message ...

  • Page 674

    Docid13902 rev 15 674/1128 rm0008 controller area network (bxcan) 689 can bit timing register (can_btr) address offset: 0x1c reset value: 0x0123 0000 this register can only be accessed by the software when the can hardware is in initialization mode. Bit 2 boff : bus-off flag this bit is set by hardw...

  • Page 675

    Controller area network (bxcan) rm0008 675/1128 docid13902 rev 15 24.9.3 can mailbox registers this chapter describes the registers of the transmit and receive mailboxes. Refer to section 24.7.5: message storage on page 659 for detailed register mapping. Transmit and receive mailboxes have the same ...

  • Page 676

    Docid13902 rev 15 676/1128 rm0008 controller area network (bxcan) 689 can tx mailbox identifier register (can_tixr) (x=0..2) address offsets: 0x180, 0x190, 0x1a0 reset value: 0xxxxx xxxx (except bit 0, txrq = 0) all tx registers are write protected when the mailbox is pending transmission (tmex rese...

  • Page 677

    Controller area network (bxcan) rm0008 677/1128 docid13902 rev 15 can mailbox data length control and time stamp register (can_tdtxr) (x=0..2) all bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x184, 0x194, 0x1a4 reset value: 0xxxxx xxxx 31 30 29 ...

  • Page 678

    Docid13902 rev 15 678/1128 rm0008 controller area network (bxcan) 689 can mailbox data low register (can_tdlxr) (x=0..2) all bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x188, 0x198, 0x1a8 reset value: 0xxxxx xxxx can mailbox data high register ...

  • Page 679

    Controller area network (bxcan) rm0008 679/1128 docid13902 rev 15 can receive fifo mailbox identifier register (can_rixr) (x=0..1) address offsets: 0x1b0, 0x1c0 reset value: 0xxxxx xxxx all rx registers are write protected. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 stid[10:0]/exid[28:18] exid[...

  • Page 680

    Docid13902 rev 15 680/1128 rm0008 controller area network (bxcan) 689 can receive fifo mailbox data length control and time stamp register (can_rdtxr) (x=0..1) address offsets: 0x1b4, 0x1c4 reset value: 0xxxxx xxxx all rx registers are write protected. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

  • Page 681

    Controller area network (bxcan) rm0008 681/1128 docid13902 rev 15 can receive fifo mailbox data low register (can_rdlxr) (x=0..1) all bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x1b8, 0x1c8 reset value: 0xxxxx xxxx all rx registers are write pr...

  • Page 682

    Docid13902 rev 15 682/1128 rm0008 controller area network (bxcan) 689 24.9.4 can filter registers can filter master register (can_fmr) address offset: 0x200 reset value: 0x2a1c 0e01 all bits of this register are set and cleared by software. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15...

  • Page 683

    Controller area network (bxcan) rm0008 683/1128 docid13902 rev 15 can filter mode register (can_fm1r) address offset: 0x204 reset value: 0x0000 0000 this register can be written only when the filter initialization mode is set (finit=1) in the can_fmr register. Note: please refer to figure 229: filte...

  • Page 684

    Docid13902 rev 15 684/1128 rm0008 controller area network (bxcan) 689 note: please refer to figure 229: filter bank scale configuration - register organization on page 657 . Can filter fifo assignment register (can_ffa1r) address offset: 0x214 reset value: 0x0000 0000 this register can be written on...

  • Page 685

    Controller area network (bxcan) rm0008 685/1128 docid13902 rev 15 filter bank i register x (can_firx) (i=0..27, x=1, 2) address offsets: 0x240..0x31c reset value: 0xxxxx xxxx n connectivity line devices there are 28 filter banks, i=0 .. 27, in other devices there are 14 filter banks i = 0 ..13. Each...

  • Page 686

    Docid13902 rev 15 686/1128 rm0008 controller area network (bxcan) 689 24.9.5 bxcan register map refer to table 3 on page 51 for the register boundary addresses. In connectivity line devices, the registers from offset 0x200 to 31c are present only in can1. Table 181. Bxcan register map and reset valu...

  • Page 687

    Controller area network (bxcan) rm0008 687/1128 docid13902 rev 15 0x188 can_tdl0r data3[7:0] data2[7:0] data1[7:0] data0[7:0] reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0x18c can_tdh0r data7[7:0] data6[7:0] data5[7:0] data4[7:0] reset value x x x x x x x x x x x x x ...

  • Page 688

    Docid13902 rev 15 688/1128 rm0008 controller area network (bxcan) 689 0x1bc can_rdh0r data7[7:0] data6[7:0] data5[7:0] data4[7:0] reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0x1c0 can_ri1r stid[10:0]/exid[28:18] exid[17:0] ide rt r reser ve d reset value x x x x x x x...

  • Page 689

    Controller area network (bxcan) rm0008 689/1128 docid13902 rev 15 0x240 can_f0r1 fb[31:0] reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0x244 can_f0r2 fb[31:0] reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0x248 can_f1r1 fb[31:0] reset valu...

  • Page 690: 25.1 Spi

    Docid13902 rev 15 690/1128 rm0008 serial peripheral interface (spi) 742 25 serial peripheral interface (spi) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32...

  • Page 691: 25.2

    Serial peripheral interface (spi) rm0008 691/1128 docid13902 rev 15 25.2 spi and i 2 s main features 25.2.1 spi features • full-duplex synchronous transfers on three lines • simplex synchronous transfers on two lines with or without a bidirectional data line • 8- or 16-bit transfer frame format sele...

  • Page 692

    Docid13902 rev 15 692/1128 rm0008 serial peripheral interface (spi) 742 25.2.2 i 2 s features • half-duplex communication (only transmitter or receiver) • master or slave operations • 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from 8 khz to 192 khz) • data format...

  • Page 693: 25.3

    Serial peripheral interface (spi) rm0008 693/1128 docid13902 rev 15 25.3 spi functional description 25.3.1 general description the block diagram of the spi is shown in figure 237 . Figure 237. Spi block diagram usually, the spi is connected to external devices through 4 pins: • miso: master in / sla...

  • Page 694

    Docid13902 rev 15 694/1128 rm0008 serial peripheral interface (spi) 742 enters the master mode fault state: the mstr bit is automatically cleared and the device is configured in slave mode (refer to section 25.3.10: error flags on page 712 ). A basic example of interconnections between a single mast...

  • Page 695

    Serial peripheral interface (spi) rm0008 695/1128 docid13902 rev 15 clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits in the spi_cr1 register. The cpol (clock polarity) bit controls the steady state value of the clock when no da...

  • Page 696

    Docid13902 rev 15 696/1128 rm0008 serial peripheral interface (spi) 742 figure 239. Data clock timing diagram 1. These timings are shown with the lsbfirst bit reset in the spi_cr1 register. Data frame format data can be shifted out either msb-first or lsb-first depending on the value of the lsbfirst...

  • Page 697

    Serial peripheral interface (spi) rm0008 697/1128 docid13902 rev 15 procedure 1. Set the dff bit to define 8- or 16-bit data frame format 2. Select the cpol and cpha bits to define one of the four relationships between the data transfer and the serial clock (see figure 239 ). For correct data transf...

  • Page 698

    Docid13902 rev 15 698/1128 rm0008 serial peripheral interface (spi) 742 25.3.3 configuring the spi in master mode in the master configuration, the serial clock is generated on the sck pin. Procedure 1. Select the br[2:0] bits to define the serial clock baud rate (see spi_cr1 register). 2. Select the...

  • Page 699

    Serial peripheral interface (spi) rm0008 699/1128 docid13902 rev 15 25.3.4 configuring the spi for half-duplex communication the spi is capable of operating in half-duplex mode in 2 configurations. • 1 clock and 1 bidirectional data wire • 1 clock and 1 data wire (receive-only or transmit-only) 1 cl...

  • Page 700

    Docid13902 rev 15 700/1128 rm0008 serial peripheral interface (spi) 742 start sequence in master mode • in full-duplex (bidimode=0 and rxonly=0) – the sequence begins when data are written into the spi_dr register (tx buffer). – the data are then parallel loaded from the tx buffer into the 8-bit shi...

  • Page 701

    Serial peripheral interface (spi) rm0008 701/1128 docid13902 rev 15 software must have written the data to be sent before the spi master device initiates the transfer. – no data are received. • in bidirectional mode, when receiving (bidimode=1 and bidioe=0) – the sequence begins when the slave devic...

  • Page 702

    Docid13902 rev 15 702/1128 rm0008 serial peripheral interface (spi) 742 figure 240. Txe/rxne/bsy behavior in master / full-duplex mode (bidimode=0 and rxonly=0) in the case of continuous transfers figure 241. Txe/rxne/bsy behavior in slave / full-duplex mode (bidimode=0, rxonly=0) in the case of con...

  • Page 703

    Serial peripheral interface (spi) rm0008 703/1128 docid13902 rev 15 transmit-only procedure (bidimode=0 rxonly=0) in this mode, the procedure can be reduced as described below and the bsy bit can be used to wait until the completion of the transmission (see figure 242 and figure 243 ). 1. Enable the...

  • Page 704

    Docid13902 rev 15 704/1128 rm0008 serial peripheral interface (spi) 742 figure 243. Txe/bsy in slave transmit-only mode (bidimode=0 and rxonly=0) in the case of continuous transfers bidirectional transmit procedure (bidimode=1 and bidioe=1) in this mode, the procedure is similar to the procedure in ...

  • Page 705

    Serial peripheral interface (spi) rm0008 705/1128 docid13902 rev 15 figure 244. Rxne behavior in receive-only mode (bidirmode=0 and rxonly=1) in the case of continuous transfers bidirectional receive procedure (bidimode=1 and bidioe=0) in this mode, the procedure is similar to the receive-only mode ...

  • Page 706

    Docid13902 rev 15 706/1128 rm0008 serial peripheral interface (spi) 742 figure 245. Txe/bsy behavior when transmitting (bidirmode=0 and rxonly=0) in the case of discontinuous transfers 25.3.6 crc calculation a crc calculator has been implemented for communication reliability. Separate crc calculator...

  • Page 707

    Serial peripheral interface (spi) rm0008 707/1128 docid13902 rev 15 1. Program the cpol, cpha, lsbfirst, br, ssm, ssi and mstr values. 2. Program the polynomial in the spi_crcpr register. 3. Enable the crc calculation by setting the crcen bit in the spi_cr1 register. This also clears the spi_rxcrcr ...

  • Page 708

    Docid13902 rev 15 708/1128 rm0008 serial peripheral interface (spi) 742 25.3.7 status flags four status flags are provided for the application to completely monitor the state of the spi bus. Tx buffer empty flag (txe) when it is set, this flag indicates that the tx buffer is empty and the next data ...

  • Page 709

    Serial peripheral interface (spi) rm0008 709/1128 docid13902 rev 15 25.3.8 disabling the spi when a transfer is terminated, the application can stop the communication by disabling the spi peripheral. This is done by clearing the spe bit. For some configurations, disabling the spi and entering the ha...

  • Page 710

    Docid13902 rev 15 710/1128 rm0008 serial peripheral interface (spi) 742 25.3.9 spi communication using dma (direct memory addressing) to operate at its maximum speed, the spi needs to be fed with the data for transmission and the data received on the rx buffer should be read to avoid overrun. To fac...

  • Page 711

    Serial peripheral interface (spi) rm0008 711/1128 docid13902 rev 15 figure 246. Transmission using dma figure 247. Reception using dma 0xf1 tx buffer txe flag 0xf2 bsy flag 0xf3 set by hardware clear by dma write set by hardware cleared by dma write set by hardware set by hardware sck reset example ...

  • Page 712

    Docid13902 rev 15 712/1128 rm0008 serial peripheral interface (spi) 742 dma capability with crc when spi communication is enabled with crc communication and dma mode, the transmission and reception of the crc at the end of communication are automatic that is without using the bit crcnext. After the ...

  • Page 713

    Serial peripheral interface (spi) rm0008 713/1128 docid13902 rev 15 crc error this flag is used to verify the validity of the value received when the crcen bit in the spi_cr1 register is set. The crcerr flag in the spi_sr register is set if the value received in the shift register does not match the...

  • Page 714: 25.4 I

    Docid13902 rev 15 714/1128 rm0008 serial peripheral interface (spi) 742 25.4 i 2 s functional description the i 2 s audio protocol is not available in low- and medium-density devices. This section concerns only high-density, xl-density and connectivity line devices. 25.4.1 i 2 s general description ...

  • Page 715

    Serial peripheral interface (spi) rm0008 715/1128 docid13902 rev 15 the spi could function as an audio i 2 s interface when the i 2 s capability is enabled (by setting the i2smod bit in the spi_i2scfgr register). This interface uses almost the same pins, flags and interrupts as the spi. The i 2 s sh...

  • Page 716

    Docid13902 rev 15 716/1128 rm0008 serial peripheral interface (spi) 742 the 24-bit and 32-bit data frames need two cpu read or write operations to/from the spi_dr or two dma operations if the dma is preferred for the application. For 24-bit data frame specifically, the 8 nonsignificant bits are exte...

  • Page 717

    Serial peripheral interface (spi) rm0008 717/1128 docid13902 rev 15 figure 251. Transmitting 0x8eaa33 • in reception mode: if data 0x8eaa33 is received: figure 252. Receiving 0x8eaa33 figure 253. I 2 s philips standard (16-bit extended to 32-bit packet frame with cpol = 0) when 16-bit data frame ext...

  • Page 718

    Docid13902 rev 15 718/1128 rm0008 serial peripheral interface (spi) 742 figure 254. Example for transmission, each time an msb is written to spi_dr, the txe flag is set and its interrupt, if allowed, is generated to load spi_dr with the new value to send. This takes place even if 0x0000 have not yet...

  • Page 719

    Serial peripheral interface (spi) rm0008 719/1128 docid13902 rev 15 figure 256. Msb justified 24-bit frame length with cpol = 0 figure 257. Msb justified 16-bit extended to 32-bit packet frame with cpol = 0 lsb justified standard this standard is similar to the msb justified standard (no difference ...

  • Page 720

    Docid13902 rev 15 720/1128 rm0008 serial peripheral interface (spi) 742 figure 259. Lsb justified 24-bit frame length with cpol = 0 • in transmission mode: if data 0x3478ae have to be transmitted, two write operations to the spi_dr register are required from software or by dma. The operations are sh...

  • Page 721

    Serial peripheral interface (spi) rm0008 721/1128 docid13902 rev 15 figure 262. Lsb justified 16-bit extended to 32-bit packet frame with cpol = 0 when 16-bit data frame extended to 32-bit channel frame is selected during the i 2 s configuration phase, only one access to spi_dr is required. The 16 r...

  • Page 722

    Docid13902 rev 15 722/1128 rm0008 serial peripheral interface (spi) 742 figure 264. Pcm standard waveforms (16-bit) for long frame synchronization, the ws signal assertion time is fixed 13 bits in master mode. For short frame synchronization, the ws synchronization signal is only one cycle long. Fig...

  • Page 723

    Serial peripheral interface (spi) rm0008 723/1128 docid13902 rev 15 it will be: i 2 s bitrate = 32 x 2 x f s if the packet length is 32-bit wide. Figure 266. Audio sampling frequency definition when the master mode is configured, a specific action needs to be taken to properly program the linear div...

  • Page 724

    Docid13902 rev 15 724/1128 rm0008 serial peripheral interface (spi) 742 table 183 , table 184 and table 185 provide example precision values for different clock configurations. Note: other configurations are possible that allow optimum clock precision. Table 183. Audio-frequency precision using stan...

  • Page 725

    Serial peripheral interface (spi) rm0008 725/1128 docid13902 rev 15 table 184. Audio-frequency precision using standard 25 mhz and pll3 (connectivity line devices only) data length prediv2 pll3mul i2sdiv i2sodd mclk target fs(hz) real fs (khz) error 32 6 14 9 1 no 96000 95942.9825 0.0594% 16 6 14 38...

  • Page 726

    Docid13902 rev 15 726/1128 rm0008 serial peripheral interface (spi) 742 table 185. Audio-frequency precision using standard 14.7456 mhz and pll3 (connectivity line devices only) data length prediv2 pll3mul i2sdiv i2sodd mclk target fs(hz) real fs (khz) error 16 3 10 16 0 no 96000 96000 0.0000% 32 3 ...

  • Page 727

    Serial peripheral interface (spi) rm0008 727/1128 docid13902 rev 15 25.4.4 i 2 s master mode the i 2 s can be configured in master mode for transmission and reception. This means that the serial clock is generated on the ck pin as well as the word select signal ws. Master clock (mck) may be output o...

  • Page 728

    Docid13902 rev 15 728/1128 rm0008 serial peripheral interface (spi) 742 reception sequence the operating mode is the same as for the transmission mode except for the point 3 (refer to the procedure described in section 25.4.4: i2s master mode ), where the configuration should set the master receptio...

  • Page 729

    Serial peripheral interface (spi) rm0008 729/1128 docid13902 rev 15 signals are input from the external master connected to the i 2 s interface. There is then no need, for the user, to configure the clock. The configuration steps to follow are listed below: 1. Set the i2smod bit in the spi_i2scfgr r...

  • Page 730

    Docid13902 rev 15 730/1128 rm0008 serial peripheral interface (spi) 742 reception sequence the operating mode is the same as for the transmission mode except for the point 1 (refer to the procedure described in section 25.4.5: i2s slave mode ), where the configuration should set the master reception...

  • Page 731

    Serial peripheral interface (spi) rm0008 731/1128 docid13902 rev 15 tx buffer empty flag (txe) when set, this flag indicates that the tx buffer is empty and the next data to be transmitted can then be loaded into it. The txe flag is reset when the tx buffer already contains data to be transmitted. I...

  • Page 732

    Docid13902 rev 15 732/1128 rm0008 serial peripheral interface (spi) 742 25.4.8 i 2 s interrupts table 186 provides the list of i 2 s interrupts. 25.4.9 dma features dma is working in exactly the same way as for the spi mode. There is no difference on the i 2 s. Only the crc feature is not available ...

  • Page 733: 25.5

    Serial peripheral interface (spi) rm0008 733/1128 docid13902 rev 15 25.5 spi and i 2 s registers refer to section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 25.5.1 spi control regi...

  • Page 734

    Docid13902 rev 15 734/1128 rm0008 serial peripheral interface (spi) 742 bit 10 rxonly: receive only this bit combined with the bidimode bit selects the direction of transfer in 2-line unidirectional mode. This bit is also useful in a multislave system in which this particular slave is not accessed, ...

  • Page 735

    Serial peripheral interface (spi) rm0008 735/1128 docid13902 rev 15 25.5.2 spi control register 2 (spi_cr2) address offset: 0x04 reset value: 0x0000 bit 2 mstr: master selection 0: slave configuration 1: master configuration note: this bit should not be changed when communication is ongoing. It is n...

  • Page 736

    Docid13902 rev 15 736/1128 rm0008 serial peripheral interface (spi) 742 25.5.3 spi status register (spi_sr) address offset: 0x08 reset value: 0x0002 note: this bit is not used in i 2 s mode bit 1 txdmaen: tx buffer dma enable when this bit is set, the dma request is made whenever the txe flag is set...

  • Page 737

    Serial peripheral interface (spi) rm0008 737/1128 docid13902 rev 15 25.5.4 spi data register (spi_dr) address offset: 0x0c reset value: 0x0000 bit 3 udr: underrun flag 0: no underrun occurred 1: underrun occurred this flag is set by hardware and reset by a software sequence. Refer to section 25.4.7 ...

  • Page 738

    Docid13902 rev 15 738/1128 rm0008 serial peripheral interface (spi) 742 25.5.5 spi crc polynomial register (spi_crcpr) (not used in i 2 s mode) address offset: 0x10 reset value: 0x0007 25.5.6 spi rx crc register (spi_rxcrcr) (not used in i 2 s mode) address offset: 0x14 reset value: 0x0000 25.5.7 sp...

  • Page 739

    Serial peripheral interface (spi) rm0008 739/1128 docid13902 rev 15 25.5.8 spi_i 2 s configuration register (spi_i2scfgr) address offset: 0x1c reset value: 0x0000 bits 15:0 txcrc[15:0]: tx crc register when crc calculation is enabled, the txcrc[7:0] bits contain the computed crc value of the subsequ...

  • Page 740

    Docid13902 rev 15 740/1128 rm0008 serial peripheral interface (spi) 742 25.5.9 spi_i 2 s prescaler register (spi_i2spr) address offset: 0x20 reset value: 0000 0010 (0x0002) bits 5:4 i2sstd: i2s standard selection 00: i 2 s philips standard. 01: msb justified standard (left justified) 10: lsb justifi...

  • Page 741

    Serial peripheral interface (spi) rm0008 741/1128 docid13902 rev 15 bits 15:10 reserved, must be kept at reset value. Bit 9 mckoe: master clock output enable 0: master clock output is disabled 1: master clock output is enabled note: this bit should be configured when the i 2 s is disabled. It is use...

  • Page 742

    Docid13902 rev 15 742/1128 rm0008 serial peripheral interface (spi) 742 25.5.10 spi register map the table provides shows the spi register map and reset values. Refer to table 3 on page 51 for the register boundary addresses. Table 187. Spi register map and reset values offset register 31 30 29 28 2...

  • Page 743: 26 Inter-Integrated

    Inter-integrated circuit (i 2 c) interface rm0008 743/1128 docid13902 rev 15 26 inter-integrated circuit (i 2 c) interface low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm3...

  • Page 744: 26.2 I

    Docid13902 rev 15 744/1128 rm0008 inter-integrated circuit (i 2 c) interface 777 26.2 i 2 c main features • parallel-bus/i 2 c protocol converter • multimaster capability: the same interface can act as master or slave • i 2 c master features: – clock generation – start and stop generation • i 2 c sl...

  • Page 745: 26.3 I

    Inter-integrated circuit (i 2 c) interface rm0008 745/1128 docid13902 rev 15 26.3 i 2 c functional description in addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa. The interrupts are enabled or disabled by software. The interface i...

  • Page 746

    Docid13902 rev 15 746/1128 rm0008 inter-integrated circuit (i 2 c) interface 777 figure 269. I 2 c block diagram 1. Smba is an optional signal in smbus mode. This signal is not applicable if smbus is disabled. 26.3.2 i 2 c slave mode by default the i 2 c interface operates in slave mode. To switch f...

  • Page 747

    Inter-integrated circuit (i 2 c) interface rm0008 747/1128 docid13902 rev 15 header or address not matched: the interface ignores it and waits for another start condition. Header matched (10-bit mode only): the interface generates an acknowledge pulse if the ack bit is set and waits for the 8-bit sl...

  • Page 748

    Docid13902 rev 15 748/1128 rm0008 inter-integrated circuit (i 2 c) interface 777 figure 270. Transfer sequence diagram for slave transmitter 2. Slave receiver following the address reception and after clearing addr, the slave receives bytes from the sda line into the dr register via the internal shi...

  • Page 749

    Inter-integrated circuit (i 2 c) interface rm0008 749/1128 docid13902 rev 15 figure 271. Transfer sequence diagram for slave receiver 1. The ev1 event stretches scl low until the end of the corresponding software sequence. 2. The ev2 software sequence must be completed before the end of the current ...

  • Page 750

    Docid13902 rev 15 750/1128 rm0008 inter-integrated circuit (i 2 c) interface 777 scl master clock generation the ccr bits are used to generate the high and low level of the scl clock, starting from the generation of the rising and falling edge (respectively). As a slave may stretch the scl line, the...

  • Page 751

    Inter-integrated circuit (i 2 c) interface rm0008 751/1128 docid13902 rev 15 the master can decide to enter transmitter or receiver mode depending on the lsb of the slave address sent. • in 7-bit addressing mode, – to enter transmitter mode, a master sends the slave address with lsb reset. – to ente...

  • Page 752

    Docid13902 rev 15 752/1128 rm0008 inter-integrated circuit (i 2 c) interface 777 figure 272. Transfer sequence diagram for master transmitter 7-bit master transmitter 10-bit master transmitter legend: s= start, s r = repeated start, p= stop, a= acknowledge, evx= event (with interrupt if itevfen = 1)...

  • Page 753

    Inter-integrated circuit (i 2 c) interface rm0008 753/1128 docid13902 rev 15 master receiver following the address transmission and after clearing addr, the i 2 c interface enters master receiver mode. In this mode the interface receives bytes from the sda line into the dr register via the internal ...

  • Page 754

    Docid13902 rev 15 754/1128 rm0008 inter-integrated circuit (i 2 c) interface 777 figure 273. Method 1: transfer sequence diagram for master receiver 1. If a single byte is received, it is na. 2. The ev5, ev6 and ev9 events stretch scl low until the end of the corresponding software sequence. 3. The ...

  • Page 755

    Inter-integrated circuit (i 2 c) interface rm0008 755/1128 docid13902 rev 15 figure 274. Method 2: transfer sequence diagram for master receiver when n>2 1. The ev5, ev6 and ev9 events stretch scl low until the end of the corresponding software sequence. 2. The ev7 software sequence must complete be...

  • Page 756

    Docid13902 rev 15 756/1128 rm0008 inter-integrated circuit (i 2 c) interface 777 the procedure described above is valid for n>2. The cases where a single byte or two bytes are to be received should be handled differently, as described below: • case of a single byte to be received: – in the addr even...

  • Page 757

    Inter-integrated circuit (i 2 c) interface rm0008 757/1128 docid13902 rev 15 figure 276. Method 2: transfer sequence diagram for master receiver when n=1 1. The ev5, ev6 and ev9 events stretch scl low until the end of the corresponding software sequence. 26.3.4 error conditions the following are the...

  • Page 758

    Docid13902 rev 15 758/1128 rm0008 inter-integrated circuit (i 2 c) interface 777 arbitration lost (arlo) this error occurs when the i 2 c interface detects an arbitration lost condition. In this case, • the arlo bit is set by hardware (and an interrupt is generated if the iterren bit is set) • the i...

  • Page 759

    Inter-integrated circuit (i 2 c) interface rm0008 759/1128 docid13902 rev 15 26.3.6 smbus introduction the system management bus (smbus) is a two-wire interface through which various devices can communicate with each other and with the rest of the system. It is based on i 2 c principles of operation...

  • Page 760

    Docid13902 rev 15 760/1128 rm0008 inter-integrated circuit (i 2 c) interface 777 bus protocols the smbus specification supports up to 9 bus protocols. For more details of these protocols and smbus address types, refer to smbus specification version. 2.0 ( http://smbus.Org/ ). These protocols should ...

  • Page 761

    Inter-integrated circuit (i 2 c) interface rm0008 761/1128 docid13902 rev 15 timeout error there are differences in the timing specifications between i 2 c and smbus. Smbus defines a clock low timeout, timeout of 35 ms. Also smbus specifies tlow: sext as the cumulative clock low extend time for a sl...

  • Page 762

    Docid13902 rev 15 762/1128 rm0008 inter-integrated circuit (i 2 c) interface 777 1. Set the i2c_dr register address in the dma_sxpar register. The data will be moved to this address from the memory after each txe event. 2. Set the memory address in the dma_sxma0r register (and in dma_sxma1r register...

  • Page 763: 26.4 I

    Inter-integrated circuit (i 2 c) interface rm0008 763/1128 docid13902 rev 15 26.3.8 packet error checking a pec calculator has been implemented to improve the reliability of communication. The pec is calculated by using the c(x) = x 8 + x 2 + x + 1 crc-8 polynomial serially on each bit. • pec calcul...

  • Page 764

    Docid13902 rev 15 764/1128 rm0008 inter-integrated circuit (i 2 c) interface 777 note: sb, addr, add10, stopf, btf, rxne and txe are logically ored on the same interrupt channel. Berr, arlo, af, ovr, pecerr, timeout and smbalert are logically ored on the same interrupt channel. Figure 277. I 2 c int...

  • Page 765: 26.5 I

    Inter-integrated circuit (i 2 c) interface rm0008 765/1128 docid13902 rev 15 26.5 i 2 c debug mode when the microcontroller enters the debug mode (cortex ® -m3 core halted), the smbus timeout either continues to work normally or stops, depending on the dbg_i2cx_smbus_timeout configuration bits in th...

  • Page 766

    Docid13902 rev 15 766/1128 rm0008 inter-integrated circuit (i 2 c) interface 777 bit 11 pos: acknowledge/pec position (for data reception) this bit is set and cleared by software and cleared by hardware when pe=0. 0: ack bit controls the (n)ack of the current byte being received in the shift registe...

  • Page 767

    Inter-integrated circuit (i 2 c) interface rm0008 767/1128 docid13902 rev 15 note: when the stop, start or pec bit is set, the software must not perform any write access to i2c_cr1 before this bit is cleared by hardware. Otherwise there is a risk of setting a second stop, start or pec request. 26.6....

  • Page 768

    Docid13902 rev 15 768/1128 rm0008 inter-integrated circuit (i 2 c) interface 777 bit 9 itevten:event interrupt enable 0: event interrupt disabled 1: event interrupt enabled this interrupt is generated when: – sb = 1 (master) – addr = 1 (master/slave) – add10= 1 (master) – stopf = 1 (slave) – btf = 1...

  • Page 769

    Inter-integrated circuit (i 2 c) interface rm0008 769/1128 docid13902 rev 15 26.6.3 i 2 c own address register 1 (i2c_oar1) address offset: 0x08 reset value: 0x0000 26.6.4 i 2 c own address register 2 (i2c_oar2) address offset: 0x0c reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 add mode ...

  • Page 770

    Docid13902 rev 15 770/1128 rm0008 inter-integrated circuit (i 2 c) interface 777 26.6.5 i 2 c data register (i2c_dr) address offset: 0x10 reset value: 0x0000 26.6.6 i 2 c status register 1 (i2c_sr1) address offset: 0x14 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved dr[7:0] rw rw...

  • Page 771

    Inter-integrated circuit (i 2 c) interface rm0008 771/1128 docid13902 rev 15 bit 15 smbalert: smbus alert in smbus host mode: 0: no smbalert 1: smbalert event occurred on pin in smbus slave mode: 0: no smbalert response address header 1: smbalert response address header to smbalert low received – cl...

  • Page 772

    Docid13902 rev 15 772/1128 rm0008 inter-integrated circuit (i 2 c) interface 777 bit 9 arlo:arbitration lost (master mode) 0: no arbitration lost detected 1: arbitration lost detected set by hardware when the interface loses the arbitration of the bus to another master – cleared by software writing ...

  • Page 773

    Inter-integrated circuit (i 2 c) interface rm0008 773/1128 docid13902 rev 15 bit 3 add10:10-bit header sent (master mode) 0: no add10 event occurred. 1: master has sent first address byte (header). – set by hardware when the master has sent the first byte in 10-bit address mode. – cleared by softwar...

  • Page 774

    Docid13902 rev 15 774/1128 rm0008 inter-integrated circuit (i 2 c) interface 777 26.6.7 i 2 c status register 2 (i2c_sr2) address offset: 0x18 reset value: 0x0000 note: reading i2c_sr2 after reading i2c_sr1 clears the addr flag, even if the addr flag was set after reading i2c_sr1. Consequently, i2c_...

  • Page 775

    Inter-integrated circuit (i 2 c) interface rm0008 775/1128 docid13902 rev 15 note: reading i2c_sr2 after reading i2c_sr1 clears the addr flag, even if the addr flag was set after reading i2c_sr1. Consequently, i2c_sr2 must be read only when addr is found set in i2c_sr1 or when the stopf bit is clear...

  • Page 776

    Docid13902 rev 15 776/1128 rm0008 inter-integrated circuit (i 2 c) interface 777 26.6.9 i 2 c trise register (i2c_trise) address offset: 0x20 reset value: 0x0002 bit 14 duty: fm mode duty cycle 0: fm mode t low /t high = 2 1: fm mode t low /t high = 16/9 (see ccr) bits 13:12 reserved, must be kept a...

  • Page 777

    Inter-integrated circuit (i 2 c) interface rm0008 777/1128 docid13902 rev 15 26.6.10 i 2 c register map the table below provides the i 2 c register map and reset values. Refer to table 3 on page 51 for the register boundary addresses table. Table 190. I 2 c register map and reset values offset regis...

  • Page 778: Transmitter (Usart)

    Docid13902 rev 15 778/1128 rm0008 universal synchronous asynchronous receiver transmitter (usart) 820 27 universal synchronous asynchronous receiver transmitter (usart) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 ...

  • Page 779: 27.2

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 779/1128 docid13902 rev 15 27.2 usart main features • full duplex, asynchronous communications • nrz standard format (mark/space) • fractional baud rate generator systems – a common programmable transmit and receive baud rates up...

  • Page 780: 27.3

    Docid13902 rev 15 780/1128 rm0008 universal synchronous asynchronous receiver transmitter (usart) 820 • transfer detection flags: – receive buffer full – transmit buffer empty – end of transmission flags • parity control: – transmits parity bit – checks parity of received data byte • four error dete...

  • Page 781

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 781/1128 docid13902 rev 15 through these pins, serial data is transmitted and received in normal usart mode as frames comprising: • an idle line prior to transmission or reception • a start bit • a data word (8 or 9 bits) least s...

  • Page 782

    Docid13902 rev 15 782/1128 rm0008 universal synchronous asynchronous receiver transmitter (usart) 820 figure 278. Usart block diagram wake up unit receiver control sr transmit control txe tc rxne idle ore ne fe usart control interrupt cr1 m wake receive data register (rdr) receive shift register rea...

  • Page 783

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 783/1128 docid13902 rev 15 27.3.1 usart character description word length may be selected as being either 8 or 9 bits by programming the m bit in the usart_cr1 register (see figure 279 ). The tx pin is in low state during the sta...

  • Page 784

    Docid13902 rev 15 784/1128 rm0008 universal synchronous asynchronous receiver transmitter (usart) 820 27.3.2 transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. When the transmit enable bit (te) is set, the data in the transmit shift register is outpu...

  • Page 785

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 785/1128 docid13902 rev 15 figure 280. Configurable stop bits procedure: 1. Enable the usart by writing the ue bit in usart_cr1 register to 1. 2. Program the m bit in usart_cr1 to define the word length. 3. Program the number of ...

  • Page 786

    Docid13902 rev 15 786/1128 rm0008 universal synchronous asynchronous receiver transmitter (usart) 820 when a transmission is taking place, a write instruction to the usart_dr register stores the data in the tdr register and which is copied in the shift register at the end of the current transmission...

  • Page 787

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 787/1128 docid13902 rev 15 27.3.3 receiver the usart can receive data words of either 8 or 9 bits depending on the m bit in the usart_cr1 register. Start bit detection in the usart, the start bit is detected when a specific seque...

  • Page 788

    Docid13902 rev 15 788/1128 rm0008 universal synchronous asynchronous receiver transmitter (usart) 820 character reception during a usart reception, data shifts in least significant bit first through the rx pin. In this mode, the usart_dr register consists of a buffer (rdr) between the internal bus a...

  • Page 789

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 789/1128 docid13902 rev 15 the rxne flag is set after every byte received. An overrun error occurs if rxne flag is set when the next data is received or the previous dma request has not been serviced. When an overrun error occurs...

  • Page 790

    Docid13902 rev 15 790/1128 rm0008 universal synchronous asynchronous receiver transmitter (usart) 820 when noise is detected in a frame: • the ne is set at the rising edge of the rxne bit. • the invalid data is transferred from the shift register to the usart_dr register. • no interrupt is generated...

  • Page 791

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 791/1128 docid13902 rev 15 configurable stop bits during reception the number of stop bits to be received can be configured through the control bits of control register 2 - it can be either 1 or 2 in normal mode and 0.5 or 1.5 in...

  • Page 792

    Docid13902 rev 15 792/1128 rm0008 universal synchronous asynchronous receiver transmitter (usart) 820 example 2: to program usartdiv = 0d25.62 this leads to: div_fraction = 16*0d0.62 = 0d9.92 the nearest real number is 0d10 = 0xa div_mantissa = mantissa (0d25.620) = 0d25 = 0x19 then, usart_brr = 0x1...

  • Page 793

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 793/1128 docid13902 rev 15 27.3.5 usart receiver’s tolerance to clock deviation the usart’s asynchronous receiver works correctly only if the total clock system deviation is smaller than the usart receiver’s tolerance. The causes...

  • Page 794

    Docid13902 rev 15 794/1128 rm0008 universal synchronous asynchronous receiver transmitter (usart) 820 the non addressed devices may be placed in mute mode by means of the muting function. In mute mode: • none of the reception status bits can be set. • all the receive interrupts are inhibited. • the ...

  • Page 795

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 795/1128 docid13902 rev 15 figure 285. Mute mode using address mark detection 27.3.7 parity control parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the pce bit ...

  • Page 796

    Docid13902 rev 15 796/1128 rm0008 universal synchronous asynchronous receiver transmitter (usart) 820 27.3.8 lin (local interconnection network) mode the lin mode is selected by setting the linen bit in the usart_cr2 register. In lin mode, the following bits must be kept cleared: • clken in the usar...

  • Page 797

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 797/1128 docid13902 rev 15 figure 286. Break detection in lin mode (11-bit break length - lbdl bit is set) case 1: break signal not long enough => break discarded, lbd is not set break frame rx line break state machine capture st...

  • Page 798

    Docid13902 rev 15 798/1128 rm0008 universal synchronous asynchronous receiver transmitter (usart) 820 figure 287. Break detection in lin mode vs. Framing error detection 27.3.9 usart synchronous mode the synchronous mode is selected by writing the clken bit in the usart_cr2 register to 1. In synchro...

  • Page 799

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 799/1128 docid13902 rev 15 has been written). This means that it is not possible to receive a synchronous data without transmitting data. The lbcl, cpol and cpha bits have to be selected when both the transmitter and the receiver...

  • Page 800

    Docid13902 rev 15 800/1128 rm0008 universal synchronous asynchronous receiver transmitter (usart) 820 figure 290. Usart data clock timing diagram (m=1) figure 291. Rx data setup/hold time note: the function of ck is different in smartcard mode. Refer to the smartcard mode chapter for more details. 2...

  • Page 801

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 801/1128 docid13902 rev 15 apart from this, the communications are similar to what is done in normal usart mode. The conflicts on the line must be managed by the software (by the use of a centralized arbiter, for instance). In pa...

  • Page 802

    Docid13902 rev 15 802/1128 rm0008 universal synchronous asynchronous receiver transmitter (usart) 820 smartcard is a single wire half duplex communication protocol. • transmission of data from the transmit shift register is guaranteed to be delayed by a minimum of 1/2 baud clock. In normal operation...

  • Page 803

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 803/1128 docid13902 rev 15 figure 293. Parity error detection using the 1.5 stop bits the usart can provide a clock to the smartcard through the ck output. In smartcard mode, ck is not associated to the communication but is simpl...

  • Page 804

    Docid13902 rev 15 804/1128 rm0008 universal synchronous asynchronous receiver transmitter (usart) 820 • irda is a half duplex communication protocol. If the transmitter is busy (i.E. The usartsends data to the irda encoder), any data on the irda receive line is ignored by the irda decoder and if the...

  • Page 805

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 805/1128 docid13902 rev 15 figure 294. Irda sir endec- block diagram figure 295. Irda data modulation (3/16) -normal mode 27.3.13 continuous communication using dma the usart is capable of continuing communication using the dma. ...

  • Page 806

    Docid13902 rev 15 806/1128 rm0008 universal synchronous asynchronous receiver transmitter (usart) 820 1. Write the usart_dr register address in the dma control register to configure it as the destination of the transfer. The data will be moved to this address from memory after each txe event. 2. Wri...

  • Page 807

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 807/1128 docid13902 rev 15 reception using dma dma mode can be enabled for reception by setting the dmar bit in usart_cr3 register. Data is loaded from the usart_dr register to a sram area configured using the dma peripheral (ref...

  • Page 808

    Docid13902 rev 15 808/1128 rm0008 universal synchronous asynchronous receiver transmitter (usart) 820 27.3.14 hardware flow control it is possible to control the serial data flow between 2 devices by using the ncts input and the nrts output. Figure 298 shows how to connect 2 devices in this mode: fi...

  • Page 809: 27.4 Usart

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 809/1128 docid13902 rev 15 figure 300. Cts flow control 27.4 usart interrupts the usart interrupt events are connected to the same interrupt vector (see figure 301 ). • during transmission: transmission complete, clear to send or...

  • Page 810: 27.5

    Docid13902 rev 15 810/1128 rm0008 universal synchronous asynchronous receiver transmitter (usart) 820 figure 301. Usart interrupt mapping diagram 27.5 usart mode configuration 27.6 usart registers refer to section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripher...

  • Page 811

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 811/1128 docid13902 rev 15 27.6.1 status register (usart_sr) address offset: 0x00 reset value: 0x00c0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved cts lbd txe tc rxne idl...

  • Page 812

    Docid13902 rev 15 812/1128 rm0008 universal synchronous asynchronous receiver transmitter (usart) 820 bit 4 idle: idle line detected this bit is set by hardware when an idle line is detected. An interrupt is generated if the idleie=1 in the usart_cr1 register. It is cleared by a software sequence (a...

  • Page 813

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 813/1128 docid13902 rev 15 27.6.2 data register (usart_dr) address offset: 0x04 reset value: undefined 27.6.3 baud rate register (usart_brr) note: the baud counters stop counting if the te or re bits are disabled respectively. Ad...

  • Page 814

    Docid13902 rev 15 814/1128 rm0008 universal synchronous asynchronous receiver transmitter (usart) 820 27.6.4 control register 1 (usart_cr1) address offset: 0x0c reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ue m wake pce p...

  • Page 815

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 815/1128 docid13902 rev 15 bit 6 tcie: transmission complete interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: a usart interrupt is generated whenever tc=1 in the usart_sr register bit 5 rxnei...

  • Page 816

    Docid13902 rev 15 816/1128 rm0008 universal synchronous asynchronous receiver transmitter (usart) 820 27.6.5 control register 2 (usart_cr2) address offset: 0x10 reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res. Linen stop[1:0] clk...

  • Page 817

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 817/1128 docid13902 rev 15 note: these 3 bits (cpol, cpha, lbcl) should not be written while the transmitter is enabled. 27.6.6 control register 3 (usart_cr3) address offset: 0x14 reset value: 0x0000 bit 8 lbcl: last bit clock pu...

  • Page 818

    Docid13902 rev 15 818/1128 rm0008 universal synchronous asynchronous receiver transmitter (usart) 820 bit 8 rtse: rts enable 0: rts hardware flow control disabled 1: rts interrupt enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease...

  • Page 819

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 819/1128 docid13902 rev 15 27.6.7 guard time and prescaler register (usart_gtpr) address offset: 0x18 reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gt[7:0] psc[...

  • Page 820

    Docid13902 rev 15 820/1128 rm0008 universal synchronous asynchronous receiver transmitter (usart) 820 27.6.8 usart register map the table below gives the usart register map and reset values. Refer to table 3 on page 51 for the register boundary addresses. Table 200. Usart register map and reset valu...

  • Page 821: 28.1 Otg_Fs

    Usb on-the-go full-speed (otg_fs) rm0008 821/1128 docid13902 rev 15 28 usb on-the-go full-speed (otg_fs) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102...

  • Page 822: 28.2

    Docid13902 rev 15 822/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 28.2 otg_fs main features the main features can be divided into three categories: general, host-mode and device- mode features. 28.2.1 general features the otg_fs interface general features are the following: • it is usb-if cert...

  • Page 823

    Usb on-the-go full-speed (otg_fs) rm0008 823/1128 docid13902 rev 15 28.2.2 host-mode features the otg_fs interface main features and requirements in host-mode are the following: • external charge pump for v bus voltage generation. • up to 8 host channels (pipes): each channel is dynamically reconfig...

  • Page 824: 28.3

    Docid13902 rev 15 824/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 28.3 otg_fs functional description figure 302. Otg full-speed block diagram 28.3.1 otg full-speed core the usb otg fs receives the 48 mhz ±0.25% clock from the reset and clock controller (rcc), via an external quartz. The usb cl...

  • Page 825: 28.4

    Usb on-the-go full-speed (otg_fs) rm0008 825/1128 docid13902 rev 15 the physical support to usb connectivity. The full-speed otg phy includes the following components: • fs/ls transceiver module used by both host and device. It directly drives transmission and reception on the single-ended usb lines...

  • Page 826

    Docid13902 rev 15 826/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 28.4.1 id line detection the host or peripheral (the default) role is assumed depending on the id input pin. The id line status is determined on plugging in the usb, depending on which side of the usb cable is connected to the m...

  • Page 827: 28.5 Usb

    Usb on-the-go full-speed (otg_fs) rm0008 827/1128 docid13902 rev 15 28.5 usb peripheral this section gives the functional description of the otg_fs in the usb peripheral mode. The otg_fs works as an usb peripheral in the following circumstances: • otg b-peripheral – otg b-device default state if b-s...

  • Page 828

    Docid13902 rev 15 828/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 28.5.2 peripheral states powered state the v bus input detects the b-session valid voltage by which the usb peripheral is allowed to enter the powered state (see usb2.0 par9.1). The otg_fs then automatically connects the dp pull...

  • Page 829

    Usb on-the-go full-speed (otg_fs) rm0008 829/1128 docid13902 rev 15 28.5.3 peripheral endpoints the otg_fs core instantiates the following usb endpoints: • control endpoint 0: – bidirectional and handles control messages only – separate set of registers to handle in and out transactions – proper con...

  • Page 830

    Docid13902 rev 15 830/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 endpoint control • the following endpoint controls are available to the application through the device endpoint-x in/out control register (diepctlx/doepctlx): – endpoint enable/disable – endpoint activate in current configuratio...

  • Page 831: 28.6 Usb

    Usb on-the-go full-speed (otg_fs) rm0008 831/1128 docid13902 rev 15 the peripheral core provides the following status checks and interrupt generation: • transfer completed interrupt, indicating that data transfer was completed on both the application (ahb) and usb sides • setup stage has been done (...

  • Page 832

    Docid13902 rev 15 832/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 figure 305. Usb host-only connection 1. Stmps2141str needed only if the application has to support a v bus powered device. A basic power switch can be used if 5 v are available on the application board. 28.6.1 srp-capable host s...

  • Page 833

    Usb on-the-go full-speed (otg_fs) rm0008 833/1128 docid13902 rev 15 host detection of a peripheral connection if srp or hnp are enabled, even if usb peripherals or b-devices can be attached at any time, the otg_fs will not detect any bus connection until the end of the v bus sensing (v bus over 4.75...

  • Page 834

    Docid13902 rev 15 834/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 28.6.3 host channels the otg_fs core instantiates 8 host channels. Each host channel supports an usb host transfer (usb pipe). The host is not able to support more than 8 transfer requests at the same time. If more than 8 transf...

  • Page 835

    Usb on-the-go full-speed (otg_fs) rm0008 835/1128 docid13902 rev 15 corresponding bits in the haint and gintsts registers. The mask bits for each interrupt source of each channel are also available in the otg_fs_hcintmsk-x register. • the host core provides the following status checks and interrupt ...

  • Page 836: 28.7 Sof

    Docid13902 rev 15 836/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 ptxqsav bits in the otg_fs_hnptxsts register or nptqxsav bits in the otg_fs_hnptxsts register. 28.7 sof trigger figure 306. Sof connectivity the otg fs core provides means to monitor, track and configure sof framing in the host ...

  • Page 837: 28.8 Power

    Usb on-the-go full-speed (otg_fs) rm0008 837/1128 docid13902 rev 15 register (sofouten bit in otg_fs_gccfg). The sof pulse signal is also internally connected to the tim2 input trigger, so that the input capture feature, the output compare feature and the timer can be triggered by the sof pulse. The...

  • Page 838: 28.9 Dynamic

    Docid13902 rev 15 838/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 to save dynamic power, the usb data fifo is clocked only when accessed by the otg_fs core. 28.9 dynamic update of the otg_fs_hfir register the usb core embeds a dynamic trimming capability of micro-sof framing period in host mod...

  • Page 839: 28.11 Peripheral

    Usb on-the-go full-speed (otg_fs) rm0008 839/1128 docid13902 rev 15 28.11 peripheral fifo architecture figure 308. Device-mode fifo address mapping and ahb fifo access mapping 28.11.1 peripheral rx fifo the otg peripheral uses a single receive fifo that receives the data directed to all out endpoint...

  • Page 840: 28.12

    Docid13902 rev 15 840/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 28.11.2 peripheral tx fifos the core has a dedicated fifo for each in endpoint. The application configures fifo sizes by writing the non periodic transmit fifo size register (otg_fs_tx0fsiz) for in endpoint0 and the device in en...

  • Page 841: 28.13

    Usb on-the-go full-speed (otg_fs) rm0008 841/1128 docid13902 rev 15 28.12.2 host tx fifos the host uses one transmit fifo for all non-periodic (control and bulk) out transactions and one transmit fifo for all periodic (isochronous and interrupt) out transactions. Fifos are used as transmit buffers t...

  • Page 842: 28.14 Usb

    Docid13902 rev 15 842/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 transmit fifo ram allocation: the minimum ram space required for each in endpoint transmit fifo is the maximum packet size for that particular in endpoint. Note: more space allocated in the transmit in endpoint fifo results in b...

  • Page 843: 28.15 Otg_Fs

    Usb on-the-go full-speed (otg_fs) rm0008 843/1128 docid13902 rev 15 otg_fs to fill in the available ram space at best regardless of the current usb sequence. With these features: • the application gains good margins to calibrate its intervention in order to optimize the cpu bandwidth usage: – it can...

  • Page 844: 28.16

    Docid13902 rev 15 844/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 figure 310. Interrupt hierarchy 1. The core interrupt register bits are shown in otg_fs core interrupt register (otg_fs_gintsts) on page 859 . 28.16 otg_fs control and status registers by reading from and writing to the control ...

  • Page 845

    Usb on-the-go full-speed (otg_fs) rm0008 845/1128 docid13902 rev 15 csrs are classified as follows: • core global registers • host-mode registers • host global registers • host port csrs • host channel-specific registers • device-mode registers • device global registers • device endpoint-specific re...

  • Page 846

    Docid13902 rev 15 846/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 figure 311. Csr memory map 1. X = 3 in device mode and x = 7 in host mode. Global csr map these registers are available in both host and device modes. 0000h core global csrs (1 kbyte) 0400h host mode csrs (1 kbyte) 0800h device ...

  • Page 847

    Usb on-the-go full-speed (otg_fs) rm0008 847/1128 docid13902 rev 15 host-mode csr map these registers must be programmed every time the core changes to host mode. Otg_fs_grxstsr 0x01c otg_fs receive status debug read/otg status read and pop registers (otg_fs_grxstsr/otg_fs_grxstsp) on page 866 otg_f...

  • Page 848

    Docid13902 rev 15 848/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 device-mode csr map these registers must be programmed every time the core changes to device mode. Otg_fs_hccharx 0x500 0x520 ... 0x6e0h otg_fs host channel-x characteristics register (otg_fs_hccharx) (x = 0..7, where x = channe...

  • Page 849

    Usb on-the-go full-speed (otg_fs) rm0008 849/1128 docid13902 rev 15 data fifo (dfifo) access register map these registers, available in both host and device modes, are used to read or write the fifo space for a specific endpoint or a channel, in a given direction. If a host channel is of type in, th...

  • Page 850

    Docid13902 rev 15 850/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 power and clock gating csr map there is a single register for power and clock gating. It is available in both host and device modes. 28.16.2 otg_fs global registers these registers are available in both host and device modes, an...

  • Page 851

    Usb on-the-go full-speed (otg_fs) rm0008 851/1128 docid13902 rev 15 bits 31:20 reserved, must be kept at reset value. Bit 19 bsvld: b-session valid indicates the device mode transceiver status. 0: b-session is not valid. 1: b-session is valid. In otg mode, you can use this bit to determine if the de...

  • Page 852

    Docid13902 rev 15 852/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 otg_fs interrupt register (otg_fs_gotgint) address offset: 0x04 reset value: 0x0000 0000 the application reads this register whenever there is an otg interrupt and clears the bits in this register to clear the otg interrupt. Bit...

  • Page 853

    Usb on-the-go full-speed (otg_fs) rm0008 853/1128 docid13902 rev 15 bit 18 adtochg: a-device timeout change the core sets this bit to indicate that the a-device has timed out while waiting for the b-device to connect. Note: accessible in both device and host modes. Bit 17 hngdet: host negotiation de...

  • Page 854

    Docid13902 rev 15 854/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 otg_fs ahb configuration register (otg_fs_gahbcfg) address offset: 0x008 reset value: 0x0000 0000 this register can be used to configure the core after power-on or a change in mode. This register mainly contains ahb system-relat...

  • Page 855

    Usb on-the-go full-speed (otg_fs) rm0008 855/1128 docid13902 rev 15 otg_fs usb configuration register (otg_fs_gusbcfg) address offset: 0x00c reset value: 0x0000 0a00 this register can be used to configure the core after power-on or a changing to host mode or device mode. It contains usb and usb-phy ...

  • Page 856

    Docid13902 rev 15 856/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 bit 9 hnpcap: hnp-capable the application uses this bit to control the otg_fs controller’s hnp capabilities. 0: hnp capability is not enabled. 1: hnp capability is enabled. Note: accessible in both device and host modes. Bit 8 s...

  • Page 857

    Usb on-the-go full-speed (otg_fs) rm0008 857/1128 docid13902 rev 15 otg_fs reset register (otg_fs_grstctl) address offset: 0x10 reset value: 0x2000 0000 the application uses this register to reset various hardware features inside the core. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 ...

  • Page 858

    Docid13902 rev 15 858/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 bit 2 fcrst: host frame counter reset the application writes this bit to reset the frame number counter inside the core. When the frame counter is reset, the subsequent sof sent out by the core has a frame number of 0. Note: onl...

  • Page 859

    Usb on-the-go full-speed (otg_fs) rm0008 859/1128 docid13902 rev 15 otg_fs core interrupt register (otg_fs_gintsts) address offset: 0x014 reset value: 0x0400 0020 this register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this...

  • Page 860

    Docid13902 rev 15 860/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 bit 25 hcint: host channels interrupt the core sets this bit to indicate that an interrupt is pending on one of the channels of the core (in host mode). The application must read the otg_fs_haint register to determine the exact ...

  • Page 861

    Usb on-the-go full-speed (otg_fs) rm0008 861/1128 docid13902 rev 15 bit 14 isoodrp: isochronous out packet dropped interrupt the core sets this bit when it fails to write an isochronous out packet into the rxfifo because the rxfifo does not have enough space to accommodate a maximum size packet for ...

  • Page 862

    Docid13902 rev 15 862/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 bit 3 sof: start of frame in host mode, the core sets this bit to indicate that an sof (fs), or keep-alive (ls) is transmitted on the usb. The application must write a 1 to this bit to clear the interrupt. In device mode, in the...

  • Page 863

    Usb on-the-go full-speed (otg_fs) rm0008 863/1128 docid13902 rev 15 otg_fs interrupt mask register (otg_fs_gintmsk) address offset: 0x018 reset value: 0x0000 0000 this register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associa...

  • Page 864

    Docid13902 rev 15 864/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 bits 23:22 reserved, must be kept at reset value. Bit 21 ipxfrm: incomplete periodic transfer mask 0: masked interrupt 1: unmasked interrupt note: only accessible in host mode. Iisooxfrm: incomplete isochronous out transfer mask...

  • Page 865

    Usb on-the-go full-speed (otg_fs) rm0008 865/1128 docid13902 rev 15 bit 11 usbsuspm: usb suspend mask 0: masked interrupt 1: unmasked interrupt note: only accessible in device mode. Bit 10 esuspm: early suspend mask 0: masked interrupt 1: unmasked interrupt note: only accessible in device mode. Bits...

  • Page 866

    Docid13902 rev 15 866/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 otg_fs receive status debug read/otg status read and pop registers (otg_fs_grxstsr/otg_fs_grxstsp) address offset for read: 0x01c address offset for pop: 0x020 reset value: 0x0000 0000 a read to the receive status debug read reg...

  • Page 867

    Usb on-the-go full-speed (otg_fs) rm0008 867/1128 docid13902 rev 15 otg_fs receive fifo size register (otg_fs_grxfsiz) address offset: 0x024 reset value: 0x0000 0200 the application can program the ram size that must be allocated to the rxfifo. Bits 31:25 reserved, must be kept at reset value. Bits ...

  • Page 868

    Docid13902 rev 15 868/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 otg_fs host non-periodic transmit fifo size register (otg_fs_hnptxfsiz)/endpoint 0 transmit fifo size (otg_fs_dieptxf0) address offset: 0x028 reset value: 0x0000 0200 host mode device mode otg_fs non-periodic transmit fifo/queue...

  • Page 869

    Usb on-the-go full-speed (otg_fs) rm0008 869/1128 docid13902 rev 15 otg_fs general core configuration register (otg_fs_gccfg) address offset: 0x038 reset value: 0x0000 0000 bit 31 reserved, must be kept at reset value. Bits 30:24 nptxqtop: top of the non-periodic transmit request queue entry in the ...

  • Page 870

    Docid13902 rev 15 870/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 otg_fs core id register (otg_fs_cid) address offset: 0x03c reset value:0x0000 1100 this is a read only register containing the product id. Otg_fs host periodic transmit fifo size register (otg_fs_hptxfsiz) address offset: 0x100 ...

  • Page 871

    Usb on-the-go full-speed (otg_fs) rm0008 871/1128 docid13902 rev 15 otg_fs device in endpoint transmit fifo size register (otg_fs_dieptxfx) (x = 1..3, where x is the fifo_number) address offset: 0x104 + (fifo_number – 1) × 0x04 reset value: 0x02000400 28.16.3 host-mode registers bit values in the re...

  • Page 872

    Docid13902 rev 15 872/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 otg_fs host frame interval register (otg_fs_hfir) address offset: 0x404 reset value: 0x0000 ea60 this register stores the frame interval information for the current speed to which the otg_fs controller has enumerated. Bits 1:0 f...

  • Page 873

    Usb on-the-go full-speed (otg_fs) rm0008 873/1128 docid13902 rev 15 otg_fs host frame number/frame time remaining register (otg_fs_hfnum) address offset: 0x408 reset value: 0x0000 3fff this register indicates the current frame number. It also indicates the time remaining (in terms of the number of p...

  • Page 874

    Docid13902 rev 15 874/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 otg_fs host all channels interrupt register (otg_fs_haint) address offset: 0x414 reset value: 0x0000 000 when a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the...

  • Page 875

    Usb on-the-go full-speed (otg_fs) rm0008 875/1128 docid13902 rev 15 otg_fs host all channels interrupt mask register (otg_fs_haintmsk) address offset: 0x418 reset value: 0x0000 0000 the host all channel interrupt mask register works with the host all channel interrupt register to interrupt the appli...

  • Page 876

    Docid13902 rev 15 876/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 bits 16:13 ptctl: port test control the application writes a nonzero value to this field to put the port into a test mode, and the corresponding pattern is signaled on the port. 0000: test mode disabled 0001: test_j mode 0010: t...

  • Page 877

    Usb on-the-go full-speed (otg_fs) rm0008 877/1128 docid13902 rev 15 bit 5 pocchng: port overcurrent change the core sets this bit when the status of the port overcurrent active bit (bit 4) in this register changes. Bit 4 poca: port overcurrent active indicates the overcurrent condition of the port. ...

  • Page 878

    Docid13902 rev 15 878/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 otg_fs host channel-x characteristics register (otg_fs_hccharx) (x = 0..7, where x = channel_number) address offset: 0x500 + (channel_number × 0x20) reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 ...

  • Page 879

    Usb on-the-go full-speed (otg_fs) rm0008 879/1128 docid13902 rev 15 otg_fs host channel-x interrupt register (otg_fs_hcintx) (x = 0..7, where x = channel_number) address offset: 0x508 + (channel_number × 0x20) reset value: 0x0000 0000 this register indicates the status of a channel with respect to u...

  • Page 880

    Docid13902 rev 15 880/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 otg_fs host channel-x interrupt mask register (otg_fs_hcintmskx) (x = 0..7, where x = channel_number) address offset: 0x50c + (channel_number × 0x20) reset value: 0x0000 0000 this register reflects the mask for each channel stat...

  • Page 881

    Usb on-the-go full-speed (otg_fs) rm0008 881/1128 docid13902 rev 15 otg_fs host channel-x transfer size register (otg_fs_hctsizx) (x = 0..7, where x = channel_number) address offset: 0x510 + (channel_number × 0x20) reset value: 0x0000 0000 bit 2 reserved, must be kept at reset value. Bit 1 chhm: cha...

  • Page 882

    Docid13902 rev 15 882/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 28.16.4 device-mode registers otg_fs device configuration register (otg_fs_dcfg) address offset: 0x800 reset value: 0x0220 0000 this register configures the core in device mode after power-on or after certain control commands or...

  • Page 883

    Usb on-the-go full-speed (otg_fs) rm0008 883/1128 docid13902 rev 15 otg_fs device control register (otg_fs_dctl) address offset: 0x804 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved pop r gdne cgona k sgo n ak cginak sgi n ak t...

  • Page 884

    Docid13902 rev 15 884/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 table 206 contains the minimum duration (according to device state) for which the soft disconnect (sdis) bit must be set for the usb host to detect a device disconnect. To accommodate clock jitter, it is recommended that the app...

  • Page 885

    Usb on-the-go full-speed (otg_fs) rm0008 885/1128 docid13902 rev 15 otg_fs device in endpoint common interrupt mask register (otg_fs_diepmsk) address offset: 0x810 reset value: 0x0000 0000 this register works with each of the otg_fs_diepintx registers for all endpoints to generate an interrupt per i...

  • Page 886

    Docid13902 rev 15 886/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 otg_fs device out endpoint common interrupt mask register (otg_fs_doepmsk) address offset: 0x814 reset value: 0x0000 0000 this register works with each of the otg_fs_doepintx registers for all endpoints to generate an interrupt ...

  • Page 887

    Usb on-the-go full-speed (otg_fs) rm0008 887/1128 docid13902 rev 15 otg_fs device all endpoints interrupt register (otg_fs_daint) address offset: 0x818 reset value: 0x0000 0000 when a significant event occurs on an endpoint, a otg_fs_daint register interrupts the application using the device out end...

  • Page 888

    Docid13902 rev 15 888/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 otg_fs all endpoints interrupt mask register (otg_fs_daintmsk) address offset: 0x81c reset value: 0x0000 0000 the otg_fs_daintmsk register works with the device endpoint interrupt register to interrupt the application when an ev...

  • Page 889

    Usb on-the-go full-speed (otg_fs) rm0008 889/1128 docid13902 rev 15 otg_fs device v bus pulsing time register (otg_fs_dvbuspulse) address offset: 0x082c reset value: 0x0000 05b8 this register specifies the v bus pulsing time during srp. Otg_fs device in endpoint fifo empty interrupt mask register: (...

  • Page 890

    Docid13902 rev 15 890/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 otg_fs device control in endpoint 0 control register (otg_fs_diepctl0) address offset: 0x900 reset value: 0x0000 0000 this section describes the otg_fs_diepctl0 register. Nonzero control endpoints use registers for endpoints 1–3...

  • Page 891

    Usb on-the-go full-speed (otg_fs) rm0008 891/1128 docid13902 rev 15 otg device endpoint-x control register (otg_fs_diepctlx) (x = 1..3, where x = endpoint_number) address offset: 0x900 + (endpoint_number × 0x20) reset value: 0x0000 0000 the application uses this register to control the behavior of e...

  • Page 892

    Docid13902 rev 15 892/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 bit 30 epdis: endpoint disable the application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interru...

  • Page 893

    Usb on-the-go full-speed (otg_fs) rm0008 893/1128 docid13902 rev 15 bit 17 naksts: nak status it indicates the following: 0: the core is transmitting non-nak handshakes based on the fifo status. 1: the core is transmitting nak handshakes on this endpoint. When either the application or the core sets...

  • Page 894

    Docid13902 rev 15 894/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 otg_fs device control out endpoint 0 control register (otg_fs_doepctl0) address offset: 0xb00 reset value: 0x0000 8000 this section describes the otg_fs_doepctl0 register. Nonzero control endpoints use registers for endpoints 1–...

  • Page 895

    Usb on-the-go full-speed (otg_fs) rm0008 895/1128 docid13902 rev 15 otg_fs device endpoint-x control register (otg_fs_doepctlx) (x = 1..3, where x = endpoint_number) address offset for out endpoints: 0xb00 + (endpoint_number × 0x20) reset value: 0x0000 0000 the application uses this register to cont...

  • Page 896

    Docid13902 rev 15 896/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 bit 30 epdis: endpoint disable the application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interru...

  • Page 897

    Usb on-the-go full-speed (otg_fs) rm0008 897/1128 docid13902 rev 15 bit 17 naksts: nak status indicates the following: 0: the core is transmitting non-nak handshakes based on the fifo status. 1: the core is transmitting nak handshakes on this endpoint. When either the application or the core sets th...

  • Page 898

    Docid13902 rev 15 898/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 otg_fs device endpoint-x interrupt register (otg_fs_diepintx) (x = 0..3, where x = endpoint_number) address offset: 0x908 + (endpoint_number × 0x20) reset value: 0x0000 0080 this register indicates the status of an endpoint with...

  • Page 899

    Usb on-the-go full-speed (otg_fs) rm0008 899/1128 docid13902 rev 15 otg_fs device endpoint-x interrupt register (otg_fs_doepintx) (x = 0..3, where x = endpoint_number) address offset: 0xb08 + (endpoint_number × 0x20) reset value: 0x0000 0080 this register indicates the status of an endpoint with res...

  • Page 900

    Docid13902 rev 15 900/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 otg_fs device in endpoint 0 transfer size register (otg_fs_dieptsiz0) address offset: 0x910 reset value: 0x0000 0000 the application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using the endp...

  • Page 901

    Usb on-the-go full-speed (otg_fs) rm0008 901/1128 docid13902 rev 15 otg_fs device out endpoint 0 transfer size register (otg_fs_doeptsiz0) address offset: 0xb10 reset value: 0x0000 0000 the application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using the endpoin...

  • Page 902

    Docid13902 rev 15 902/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 otg_fs device endpoint-x transfer size register (otg_fs_dieptsizx) (x = 1..3, where x = endpoint_number) address offset: 0x910 + (endpoint_number × 0x20) reset value: 0x0000 0000 the application must modify this register before ...

  • Page 903

    Usb on-the-go full-speed (otg_fs) rm0008 903/1128 docid13902 rev 15 otg_fs device in endpoint transmit fifo status register (otg_fs_dtxfstsx) (x = 0..3, where x = endpoint_number) address offset for in endpoints: 0x918 + (endpoint_number × 0x20) this read-only register contains the free space inform...

  • Page 904

    Docid13902 rev 15 904/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 28.16.5 otg_fs power and clock gating control register (otg_fs_pcgcctl) address offset: 0xe00 reset value: 0x0000 0000 this register is available in host and device modes. Stupcnt: setup packet count applies to control out endpo...

  • Page 905

    Usb on-the-go full-speed (otg_fs) rm0008 905/1128 docid13902 rev 15 28.16.6 otg_fs register map the table below gives the usb otg register map and reset values. Table 207. Otg_fs register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5...

  • Page 906

    Docid13902 rev 15 906/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 0x024 otg_fs_grxf siz reserved rxfd reset value 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0x028 otg_fs_hnpt xfsiz/ otg_fs_diep txf0 nptxfd/tx0fd nptxfsa/tx0fsa reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0x...

  • Page 907

    Usb on-the-go full-speed (otg_fs) rm0008 907/1128 docid13902 rev 15 0x540 otg_fs_hcc har2 chena ch dis oddfrm dad mcnt ep ty p ls d e v reserved ep d ir epnum mpsiz reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x560 otg_fs_hcc har3 chena chd is oddfrm dad mcnt ep ty p ls...

  • Page 908

    Docid13902 rev 15 908/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 0x52c otg_fs_hcin tmsk1 reserved dterrm frmo rm bb errm txerrm nye t ack m nak m st all m reserved chhm xfrcm reset value 0 0 0 0 0 0 0 0 0 0 0x54c otg_fs_hcin tmsk2 reserved dt e r r m fr m o r m bbe rr m tx errm nyet ackm nakm...

  • Page 909

    Usb on-the-go full-speed (otg_fs) rm0008 909/1128 docid13902 rev 15 0x800 otg_fs_dcfg reserved pfiv l dad reserved nz ls ohs k dspd reset value 0 0 0 0 0 0 0 0 0 0 0 0 0x804 otg_fs_dctl reserved pop r gdne cgonak sg o n ak cgina k sg in ak tct l go ns ts gi nst s sdi s rw u s ig reset value 0 0 0 0 ...

  • Page 910

    Docid13902 rev 15 910/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 0x940 otg_fs_diep ctl2 e pena epdi s s o ddfr m s d 0p id /s ev nfrm sn a k cn a k txfnum st a ll reserved epty p naks ts eonu m/dpid usb aep reserved mpsiz reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x958...

  • Page 911

    Usb on-the-go full-speed (otg_fs) rm0008 911/1128 docid13902 rev 15 refer to table 3 on page 51 for the register boundary addresses. 0x968 otg_fs_diepi nt3 reserved txfe in epne re se rv ed ittxfe to c re se rv ed ep disd xfrc reset value 1 0 0 0 0 0 0xb08 otg_fs_doep int0 reserved re se rved b2bs t...

  • Page 912: 28.17

    Docid13902 rev 15 912/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 28.17 otg_fs programming model 28.17.1 core initialization the application must perform the core initialization sequence. If the cable is connected during power-up, the current mode of operation bit in the otg_fs_gintsts (cmod b...

  • Page 913

    Usb on-the-go full-speed (otg_fs) rm0008 913/1128 docid13902 rev 15 28.17.2 host initialization to initialize the core as host, the application must perform the following steps: 1. Program the hprtint in the otg_fs_gintmsk register to unmask 2. Program the otg_fs_hcfg register to select full-speed h...

  • Page 914

    Docid13902 rev 15 914/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 register to determine the enumeration speed and perform the steps listed in endpoint initialization on enumeration completion on page 931 . At this point, the device is ready to accept sof packets and perform control transfers o...

  • Page 915

    Usb on-the-go full-speed (otg_fs) rm0008 915/1128 docid13902 rev 15 1. When an stall, txerr, bberr or dterr interrupt in otg_fs_hcintx is received for an in or out channel. The application must be able to receive other interrupts (dterr, nak, data, txerr) for the same channel before receiving the ha...

  • Page 916

    Docid13902 rev 15 916/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 • reading the receive fifo the application must ignore all packet statuses other than in data packet (bx0010). Figure 313. Receive fifo read task • bulk and control out/setup transactions a typical bulk or control out/setup pipe...

  • Page 917

    Usb on-the-go full-speed (otg_fs) rm0008 917/1128 docid13902 rev 15 setup transaction operates in the same way but has only one packet. The assumptions are: – the application is attempting to send two maximum-packet-size packets (transfer size = 1, 024 bytes). – the non-periodic transmit fifo can ho...

  • Page 918

    Docid13902 rev 15 918/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 figure 314. Normal bulk/control out/setup and bulk/control in transactions the channel-specific interrupt service routine for bulk and control out/setup transactions is shown in the following code samples. • interrupt service ro...

  • Page 919

    Usb on-the-go full-speed (otg_fs) rm0008 919/1128 docid13902 rev 15 de-allocate channel } else if (stall) { transfer done = 1 unmask chh disable channel } else if (nak or txerr ) { rewind buffer pointers unmask chh disable channel if (txerr) { increment error count unmask ack } else { reset error co...

  • Page 920

    Docid13902 rev 15 920/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 reset error count mask ack } else if (txerr or bberr or stall) { unmask chh disable channel if (txerr) { increment error count unmask ack } } else if (chh) { mask chh if (transfer done or (error_count == 3)) { de-allocate channe...

  • Page 921

    Usb on-the-go full-speed (otg_fs) rm0008 921/1128 docid13902 rev 15 figure 315. Bulk/control in transactions the sequence of operations is as follows: a) initialize channel 2. B) set the chena bit in hcchar2 to write an in request to the non-periodic request queue. C) the core attempts to send an in...

  • Page 922

    Docid13902 rev 15 922/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 f) the core generates the rxflvl interrupt for the transfer completion status entry in the receive fifo. G) the application must read and ignore the receive packet status when the receive packet status is not an in data packet (...

  • Page 923

    Usb on-the-go full-speed (otg_fs) rm0008 923/1128 docid13902 rev 15 figure 316. Normal interrupt out/in transactions • interrupt service routine for interrupt out/in transactions a) interrupt out unmask (nak/txerr/stall/xfrc/frmor) if (xfrc) { reset error count mask ack de-allocate channel } else if...

  • Page 924

    Docid13902 rev 15 924/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 disable channel if (stall) { transfer done = 1 } } else if (nak or txerr) { rewind buffer pointers reset error count mask ack unmask chh disable channel } else if (chh) { mask chh if (transfer done or (error_count == 3)) { de-al...

  • Page 925

    Usb on-the-go full-speed (otg_fs) rm0008 925/1128 docid13902 rev 15 } } else if (stall or frmor or nak or dterr or bberr) { mask ack unmask chh disable channel if (stall or bberr) { reset error count transfer done = 1 } else if (!Frmor) { reset error count } } else if (txerr) { increment error count...

  • Page 926

    Docid13902 rev 15 926/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 • interrupt in transactions the assumptions are: – the application is attempting to receive one packet (up to 1 maximum packet size) in every frame, starting with odd (transfer size = 1 024 bytes). – the receive fifo can hold at...

  • Page 927

    Usb on-the-go full-speed (otg_fs) rm0008 927/1128 docid13902 rev 15 • isochronous out transactions a typical isochronous out operation is shown in figure 317 . The assumptions are: – the application is attempting to send one packet every frame (up to 1 maximum packet size), starting with an odd fram...

  • Page 928

    Docid13902 rev 15 928/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 figure 317. Normal isochronous out/in transactions • interrupt service routine for isochronous out/in transactions code sample: isochronous out unmask (frmor/xfrc) if (xfrc) { de-allocate channel } else if (frmor) { unmask chh d...

  • Page 929

    Usb on-the-go full-speed (otg_fs) rm0008 929/1128 docid13902 rev 15 else if (chh) { mask chh de-allocate channel } code sample: isochronous in unmask (txerr/xfrc/frmor/bberr) if (xfrc or frmor) { if (xfrc and (otg_fs_hctsizx.Pktcnt == 0)) { reset error count de-allocate channel } else { unmask chh d...

  • Page 930

    Docid13902 rev 15 930/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 • isochronous in transactions the assumptions are: – the application is attempting to receive one packet (up to 1 maximum packet size) in every frame starting with the next odd frame (transfer size = 1 024 bytes). – the receive ...

  • Page 931

    Usb on-the-go full-speed (otg_fs) rm0008 931/1128 docid13902 rev 15 the channel. Port babble occurs if the core continues to receive data from the device at eof2 (the end of frame 2, which is very close to sof). When otg_fs controller detects a packet babble, it stops writing data into the rx buffer...

  • Page 932

    Docid13902 rev 15 932/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 at this point, the device is ready to receive sof packets and is configured to perform control transfers on control endpoint 0. Endpoint initialization on setaddress command this section describes what the application must do wh...

  • Page 933

    Usb on-the-go full-speed (otg_fs) rm0008 933/1128 docid13902 rev 15 1. In the endpoint to be deactivated, clear the usb active endpoint bit in the otg_fs_diepctlx register (for in or bidirectional endpoints) or the otg_fs_doepctlx register (for out or bidirectional endpoints). 2. Once the endpoint i...

  • Page 934

    Docid13902 rev 15 934/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 completed. After this entry is popped from the receive fifo, the core asserts a transfer completed interrupt on the specified out endpoint. 5. After the data payload is popped from the receive fifo, the rxflvl interrupt (otg_fs_...

  • Page 935

    Usb on-the-go full-speed (otg_fs) rm0008 935/1128 docid13902 rev 15 determine the correct number of setup packets received in the setup stage of a control transfer. – stupcnt = 3 in otg_fs_doeptsizx 2. The application must always allocate some extra space in the receive data fifo, to be able to rece...

  • Page 936

    Docid13902 rev 15 936/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 figure 319. Processing a setup packet • handling more than three back-to-back setup packets per the usb 2.0 specification, normally, during a setup packet error, a host does not send more than three back-to-back setup packets to...

  • Page 937

    Usb on-the-go full-speed (otg_fs) rm0008 937/1128 docid13902 rev 15 1. To stop receiving any kind of data in the receive fifo, the application must set the global out nak bit by programming the following field: – sgonak = 1 in otg_fs_dctl 2. Wait for the assertion of the gonakeff interrupt in otg_fs...

  • Page 938

    Docid13902 rev 15 938/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 1. Before setting up an out transfer, the application must allocate a buffer in the memory to accommodate all data to be received as part of the out transfer. 2. For out transfers, the transfer size field in the endpoint’s trans...

  • Page 939

    Usb on-the-go full-speed (otg_fs) rm0008 939/1128 docid13902 rev 15 6. The out data transfer completed pattern for an out endpoint is written to the receive fifo on one of the following conditions: – the transfer size is 0 and the packet count is 0 – the last out data packet written to the receive f...

  • Page 940

    Docid13902 rev 15 940/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 otg_fs_doeptsizx with the data pid of the last isochronous out data packet read from the receive fifo. Application programming sequence: 1. Program the otg_fs_doeptsizx register for the transfer size and the corresponding packet...

  • Page 941

    Usb on-the-go full-speed (otg_fs) rm0008 941/1128 docid13902 rev 15 (iisooxfrm in otg_fs_gintsts), indicating that an xfrc interrupt (in otg_fs_doepintx) is not asserted on at least one of the isochronous out endpoints. At this point, the endpoint with the incomplete transfer remains enabled, but no...

  • Page 942

    Docid13902 rev 15 942/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 examples this section describes and depicts some fundamental transfer types and scenarios. • bulk out transaction figure 320 depicts the reception of a single bulk out data packet from the usb to the ahb and describes the events...

  • Page 943

    Usb on-the-go full-speed (otg_fs) rm0008 943/1128 docid13902 rev 15 in data transfers • packet write this section describes how the application writes data packets to the endpoint fifo when dedicated transmit fifos are enabled. 1. The application can either choose the polling or the interrupt mode. ...

  • Page 944

    Docid13902 rev 15 944/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 1. To stop transmitting any data on a particular in endpoint, the application must set the in nak bit. To set this bit, the following field must be programmed. – snak = 1 in otg_fs_diepctlx 2. Wait for assertion of the inepne in...

  • Page 945

    Usb on-the-go full-speed (otg_fs) rm0008 945/1128 docid13902 rev 15 • generic non-periodic in data transfers application requirements: 1. Before setting up an in transfer, the application must ensure that all data to be transmitted as part of the in transfer are part of a single buffer. 2. For in tr...

  • Page 946

    Docid13902 rev 15 946/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 handshake, the packet count for the endpoint is decremented by one, until the packet count is zero. The packet count is not decremented on a timeout. 5. For zero length packets (indicated by an internal zero length flag), the co...

  • Page 947

    Usb on-the-go full-speed (otg_fs) rm0008 947/1128 docid13902 rev 15 2. The application can only schedule data transfers one frame at a time. – (mcnt – 1) × mpsiz ≤ xfersiz ≤ mcnt × mpsiz – pktcnt = mcnt (in otg_fs_dieptsizx) – if xfersiz packet. – note that: mcnt is in otg_fs_dieptsizx, mpsiz is in ...

  • Page 948

    Docid13902 rev 15 948/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 application programming sequence: 1. Program the otg_fs_diepctlx register with the endpoint characteristics and set the cnak and epena bits. 2. Write the data to be transmitted in the next frame to the transmit fifo. 3. Assertin...

  • Page 949

    Usb on-the-go full-speed (otg_fs) rm0008 949/1128 docid13902 rev 15 application programming sequence: 1. The application can ignore the in token received when txfifo empty interrupt in otg_fs_diepintx on any isochronous in endpoint, as it eventually results in an incomplete isochronous in transfer i...

  • Page 950

    Docid13902 rev 15 950/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 application receives this interrupt, it must set the stall bit in the corresponding endpoint control register, and clear this interrupt. 28.17.7 worst case response time when the otg_fs controller acts as a device, there is a wo...

  • Page 951

    Usb on-the-go full-speed (otg_fs) rm0008 951/1128 docid13902 rev 15 figure 321. Trdt max timing case 28.17.8 otg programming model the otg_fs controller is an otg device supporting hnp and srp. When the core is connected to an “a” plug, it is referred to as an a-device. When the core is connected to...

  • Page 952

    Docid13902 rev 15 952/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 figure 322. A-device srp 1. Drv_vbus = v bus drive signal to the phy vbus_valid = v bus valid signal from phy a_valid = a-peripheral v bus level signal to phy d+ = data plus line d- = data minus line 1. To save power, the applic...

  • Page 953

    Usb on-the-go full-speed (otg_fs) rm0008 953/1128 docid13902 rev 15 b-device session request protocol the application must set the srp-capable bit in the core usb configuration register. This enables the otg_fs controller to initiate srp as a b-device. Srp is a means by which the otg_fs controller c...

  • Page 954

    Docid13902 rev 15 954/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 discharge time can be obtained from the transceiver vendor and varies from one transceiver to another. 3. The usb otg core informs the phy to speed up v bus discharge. 4. The application initiates srp by writing the session requ...

  • Page 955

    Usb on-the-go full-speed (otg_fs) rm0008 955/1128 docid13902 rev 15 and status register to indicate to the otg_fs controller that the b-device supports hnp. 2. When it has finished using the bus, the application suspends by writing the port suspend bit in the host port control and status register. 3...

  • Page 956

    Docid13902 rev 15 956/1128 rm0008 usb on-the-go full-speed (otg_fs) 957 figure 325. B-device hnp 1. Dppulldown = signal from core to phy to enable/disable the pull-down on the dp line inside the phy. Dmpulldown = signal from core to phy to enable/disable the pull-down on the dm line inside the phy. ...

  • Page 957

    Usb on-the-go full-speed (otg_fs) rm0008 957/1128 docid13902 rev 15 negotiation success. The application must read the current mode bit in the core interrupt register (otg_fs_gintsts) to determine host mode operation. 3. The application sets the reset bit (prst in otg_fs_hprt) and the otg_fs control...

  • Page 958: Dma Controller

    Docid13902 rev 15 958/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 29 ethernet (eth): media access control (mac) with dma controller low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 a...

  • Page 959

    Ethernet (eth): media access control (mac) with dma controller rm0008 959/1128 docid13902 rev 15 29.2.1 mac core features • supports 10/100 mbit/s data transfer rates with external phy interfaces • ieee 802.3-compliant mii interface to communicate with an external fast ethernet phy • supports both f...

  • Page 960

    Docid13902 rev 15 960/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 store-and-forward mode • option to forward under-sized good frames • supports statistics by generating pulses for frames dropped or corrupted (due to overflow) in the receive fifo • supports store a...

  • Page 961: 29.3 Ethernet

    Ethernet (eth): media access control (mac) with dma controller rm0008 961/1128 docid13902 rev 15 29.3 ethernet pins table 208 shows the mac signals and the corresponding mii/rmii default or remapped signals. It also indicates the pins onto which the signals are input or output, and the pin configura...

  • Page 962: 29.4

    Docid13902 rev 15 962/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 29.4 ethernet functional description: smi, mii and rmii the ethernet peripheral consists of a mac 802.3 (media access control) with a dedicated dma controller. It supports both default media-indepen...

  • Page 963

    Ethernet (eth): media access control (mac) with dma controller rm0008 963/1128 docid13902 rev 15 the application can select one of the 32 phys and one of the 32 registers within any phy and send control data or receive status information. Only one register in one phy can be addressed at any given ti...

  • Page 964

    Docid13902 rev 15 964/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 the management frame consists of eight fields: • preamble: each transaction (read or write) can be initiated with the preamble field that corresponds to 32 contiguous logic one bits on the mdio line...

  • Page 965

    Ethernet (eth): media access control (mac) with dma controller rm0008 965/1128 docid13902 rev 15 smi read operation when the user sets the mii busy bit in the ethernet mac mii address register (eth_macmiiar) with the mii write bit at 0, the smi initiates a read operation in the phy registers by tran...

  • Page 966

    Docid13902 rev 15 966/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 29.4.2 media-independent interface: mii the media-independent interface (mii) defines the interconnection between the mac sublayer and the phy for data transfer at 10 mbit/s and 100 mbit/s. Figure 3...

  • Page 967

    Ethernet (eth): media access control (mac) with dma controller rm0008 967/1128 docid13902 rev 15 deasserted and mii_rx_er is asserted, a specific mii_rxd[3:0] value is used to transfer specific information from the phy (see table 212 ). • mii_rx_dv: receive data valid indicates that the phy is prese...

  • Page 968

    Docid13902 rev 15 968/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 figure 331. Mii clock sources 29.4.3 reduced media-independent interface: rmii the reduced media-independent interface (rmii) specification reduces the pin count between the microcontroller ethernet...

  • Page 969

    Ethernet (eth): media access control (mac) with dma controller rm0008 969/1128 docid13902 rev 15 rmii clock sources as described in the rmii clock sources section, the stm32f10xxxstm32f107xx could provide this 50 mhz clock signal on its mco output pin and you then have to configure this output value...

  • Page 970: 29.5

    Docid13902 rev 15 970/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 to save a pin, the two input clock signals, rmii_ref_ck and mii_rx_clk, are multiplexed on the same gpio pin. 29.5 ethernet functional description: mac 802.3 the ieee 802.3 international standard fo...

  • Page 971

    Ethernet (eth): media access control (mac) with dma controller rm0008 971/1128 docid13902 rev 15 figure 336 and figure 337 describe the frame structure (untagged and tagged) that includes the following fields: • preamble: 7-byte field used for synchronization purposes (pls circuitry) hexadecimal val...

  • Page 972

    Docid13902 rev 15 972/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 hexadecimal). This constant field is used to distinguish tagged and untagged mac frames. – 2-byte field containing the tag control information field subdivided as follows: a 3- bit user priority, a ...

  • Page 973

    Ethernet (eth): media access control (mac) with dma controller rm0008 973/1128 docid13902 rev 15 figure 336. Mac frame format figure 337. Tagged mac frame format each byte of the mac frame, except the fcs field, is transmitted low-order bit first. An invalid mac frame is defined by one of the follow...

  • Page 974

    Docid13902 rev 15 974/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 29.5.2 mac frame transmission the dma controls all transactions for the transmit path. Ethernet frames read from the system memory are pushed into the fifo by the dma. The frames are then popped out...

  • Page 975

    Ethernet (eth): media access control (mac) with dma controller rm0008 975/1128 docid13902 rev 15 the crc generator calculates the 32-bit crc for the fcs field of the ethernet frame. The encoding is defined by the following polynomial. Transmit protocol the mac controls the operation of ethernet fram...

  • Page 976

    Docid13902 rev 15 976/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 configured for 96 bit times, the mac follows the rule of deference specified in section 4.2.3.2.1 of the ieee 802.3 specification. The mac resets its ifg counter if a carrier is detected during the ...

  • Page 977

    Ethernet (eth): media access control (mac) with dma controller rm0008 977/1128 docid13902 rev 15 frame is being transmitted. As soon as the first frame has been transferred and the status is received from the mac, it is pushed to the dma. If the dma has already completed sending the second packet to...

  • Page 978

    Docid13902 rev 15 978/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 is set in the eth_eth_dmaomr register). If the core is configured for threshold (cut- through) mode, the transmit checksum offload is bypassed. You must make sure the transmit fifo is deep enough to...

  • Page 979

    Ethernet (eth): media access control (mac) with dma controller rm0008 979/1128 docid13902 rev 15 error, it inserts an ipv4 header checksum if the ethernet type field indicates an ipv4 payload. • tcp/udp/icmp checksum the tcp/udp/icmp checksum processes the ipv4 or ipv6 header (including extension he...

  • Page 980

    Docid13902 rev 15 980/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 figure 338. Transmission bit order mii/rmii transmit timing diagrams figure 339. Transmission with no collision d0 d1 d2 d3 lsb mii_txd[3:0] msb d0 d1 lsb msb rmii_txd[1:0] bibit stream nibble strea...

  • Page 981

    Ethernet (eth): media access control (mac) with dma controller rm0008 981/1128 docid13902 rev 15 figure 340. Transmission with collision figure 341 shows a frame transmission in mii and rmii. Figure 341. Frame transmission in mmi and rmii modes 29.5.3 mac frame reception the mac received frames are ...

  • Page 982

    Docid13902 rev 15 982/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 packet has been transferred. Upon completion of the eof frame transfer, the status word is popped out and sent to the dma controller. In rx fifo store-and-forward mode (configured by the rsf bit in ...

  • Page 983

    Ethernet (eth): media access control (mac) with dma controller rm0008 983/1128 docid13902 rev 15 type (ethernet type field) and the ip header version, or when the received frame does not have enough bytes, as indicated by the ipv4 header’s length field (or when fewer than 20 bytes are available in a...

  • Page 984

    Docid13902 rev 15 984/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 the frame is dropped and the rx status word is immediately updated (with zero frame length, crc error and runt error bits set), indicating the filter fail. In ethernet power down mode, all received ...

  • Page 985

    Ethernet (eth): media access control (mac) with dma controller rm0008 985/1128 docid13902 rev 15 receive status word at the end of the ethernet frame reception, the mac outputs the receive status to the application (dma). The detailed description of the receive status is the same as for bits[31:0] i...

  • Page 986

    Docid13902 rev 15 986/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 figure 343. Reception with no error figure 344. Reception with errors figure 345. Reception with false carrier indication mii_rx_clk mii_rx_dv mii_rxd[3:0] preamble sfd mii_rx_err ai15634 fcs mii_rx...

  • Page 987

    Ethernet (eth): media access control (mac) with dma controller rm0008 987/1128 docid13902 rev 15 29.5.4 mac interrupts interrupts can be generated from the mac core as a result of various events. The eth_macsr register describes the events that can cause an interrupt from the mac core. You can preve...

  • Page 988

    Docid13902 rev 15 988/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 is set to 1, the unicast frame is said to have passed the hash filter; otherwise, the frame has failed the hash filter. Note: this crc is a 32-bit value coded by the following polynomial (for more d...

  • Page 989

    Ethernet (eth): media access control (mac) with dma controller rm0008 989/1128 docid13902 rev 15 inverse filtering operation for both destination and source address filtering, there is an option to invert the filter-match result at the final output. These are controlled by the daif and saif bits in ...

  • Page 990

    Docid13902 rev 15 990/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 29.5.6 mac loopback mode the mac supports loopback of transmitted frames onto its receiver. By default, the mac loopback function is disabled, but this feature can be enabled by programming the loop...

  • Page 991

    Ethernet (eth): media access control (mac) with dma controller rm0008 991/1128 docid13902 rev 15 received frames are considered “good” if none of the following errors exists: + crc error + runt frame (shorter than 64 bytes) + alignment error (in 10/ 100 mbit/s only) + length error (non-type frames o...

  • Page 992

    Docid13902 rev 15 992/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 figure 347. Wakeup frame filter register • filter i byte mask this register defines which bytes of the frame are examined by filter i (0, 1, 2, and 3) in order to determine whether or not the frame ...

  • Page 993

    Ethernet (eth): media access control (mac) with dma controller rm0008 993/1128 docid13902 rev 15 wakeup frame is more than 512 bytes long, if the frame has a valid crc value, it is considered valid. Wakeup frame detection is updated in the eth_macpmtcsr register for every remote wakeup frame receive...

  • Page 994

    Docid13902 rev 15 994/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 1. Disable the transmit dma and wait for any previous frame transmissions to complete. These transmissions can be detected when the transmit interrupt eth_dmasr register[0] is received. 2. Disable t...

  • Page 995

    Ethernet (eth): media access control (mac) with dma controller rm0008 995/1128 docid13902 rev 15 figure 348. Networked time synchronization 1. The master broadcasts ptp sync messages to all its nodes. The sync message contains the master’s reference time information. The time at which this message l...

  • Page 996

    Docid13902 rev 15 996/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 be greater than or equal to the resolution of time stamp counter. The synchronization accuracy target between the master node and the slaves is around 100 ns. The generation, update and modification...

  • Page 997

    Ethernet (eth): media access control (mac) with dma controller rm0008 997/1128 docid13902 rev 15 the accumulator and the addend are 32-bit registers. Here, the accumulator acts as a high- precision frequency multiplier or divider. Figure 349 shows this algorithm. Figure 349. System time update using...

  • Page 998

    Docid13902 rev 15 998/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 the algorithm is as follows: • at time mastersynctime (n) the master sends the slave clock a sync message. The slave receives this message when its local clock is slaveclocktime (n) and computes mas...

  • Page 999

    Ethernet (eth): media access control (mac) with dma controller rm0008 999/1128 docid13902 rev 15 programming steps for system time update in the coarse correction method to synchronize or update the system time in one process (coarse correction method), perform the following steps: 1. Write the offs...

  • Page 1000: 29.6

    Docid13902 rev 15 1000/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 ptp pulse-per-second output signal this ptp pulse output is used to check the synchronization between all nodes in the network. To be able to test the difference between the local slave clock and t...

  • Page 1001

    Ethernet (eth): media access control (mac) with dma controller rm0008 1001/1128 docid13902 rev 15 figure 352. Descriptor ring and chain structure 29.6.1 initialization of a transfer using dma initialization for the mac is as follows: 1. Write to eth_dmabmr to set stm32f107xx bus access parameters. 2...

  • Page 1002

    Docid13902 rev 15 1002/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 incr4, incr8, incr16 and single transactions. Otherwise (no fixed-length burst), it transfers data using incr (undefined length) and single transactions. The receive dma initiates a data transfer o...

  • Page 1003

    Ethernet (eth): media access control (mac) with dma controller rm0008 1003/1128 docid13902 rev 15 databus width. If a descriptor is marked as last, then the buffer may not be full (as indicated by the buffer size in rdes1). To compute the amount of valid data in this final buffer, the driver must re...

  • Page 1004

    Docid13902 rev 15 1004/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 unavailable (eth_dmasr register[2]) and normal interrupt summary (eth_dmasr register[16]) bits are set. The transmit engine proceeds to step 9. 4. If the acquired descriptor is flagged as owned by ...

  • Page 1005

    Ethernet (eth): media access control (mac) with dma controller rm0008 1005/1128 docid13902 rev 15 figure 353. Txdma operation in default mode txdma operation: osf mode while in the run state, the transmit process can simultaneously acquire two frames without closing the status descriptor of the firs...

  • Page 1006

    Docid13902 rev 15 1006/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 1. The dma operates as described in steps 1–6 of the txdma (default mode). 2. Without closing the previous frame’s last descriptor, the dma fetches the next descriptor. 3. If the dma owns the acqui...

  • Page 1007

    Ethernet (eth): media access control (mac) with dma controller rm0008 1007/1128 docid13902 rev 15 figure 354. Txdma operation in osf mode transmit frame processing the transmit dma expects that the data buffers contain complete ethernet frames, excluding preamble, pad bytes, and fcs fields. The da, ...

  • Page 1008

    Docid13902 rev 15 1008/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 indicates the last buffer of the frame. After the last buffer of the frame has been transmitted, the dma writes back the final status information to the transmit descriptor 0 (tdes0) word of the de...

  • Page 1009

    Ethernet (eth): media access control (mac) with dma controller rm0008 1009/1128 docid13902 rev 15 • tdes0: transmit descriptor word0 the application software has to program the control bits [30:26]+[23:20] plus the own bit [31] during descriptor initialization. When the dma updates the descriptor (o...

  • Page 1010

    Docid13902 rev 15 1010/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 bit 21 ter: transmit end of ring when set, this bit indicates that the descriptor list reached its final descriptor. The dma returns to the base address of the list, creating a descriptor ring. Bit...

  • Page 1011

    Ethernet (eth): media access control (mac) with dma controller rm0008 1011/1128 docid13902 rev 15 • tdes1: transmit descriptor word1 bit 10 nc: no carrier when set, this bit indicates that the carrier sense signal form the phy was not asserted during transmission. Bit 9 lco: late collision when set,...

  • Page 1012

    Docid13902 rev 15 1012/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 • tdes2: transmit descriptor word2 tdes2 contains the address pointer to the first buffer of the descriptor or it contains time stamp data. • tdes3: transmit descriptor word3 tdes3 contains the add...

  • Page 1013

    Ethernet (eth): media access control (mac) with dma controller rm0008 1013/1128 docid13902 rev 15 1. The cpu sets up receive descriptors (rdes0-rdes3) and sets the own bit (rdes0[31]). 2. Once the sr (eth_dmaomr register[1]) bit is set, the dma enters the run state. While in the run state, the dma p...

  • Page 1014

    Docid13902 rev 15 1014/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 figure 356. Receive dma operation (re-)fetch next descriptor (ahb) error? No own bit set? Yes yes stop rxdma start rxdma start (ahb) error? No rxdma suspended yes frame data available ? Wait for fr...

  • Page 1015

    Ethernet (eth): media access control (mac) with dma controller rm0008 1015/1128 docid13902 rev 15 receive descriptor acquisition the receive engine always attempts to acquire an extra descriptor in anticipation of an incoming frame. Descriptor acquisition is attempted if any of the following conditi...

  • Page 1016

    Docid13902 rev 15 1016/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 rx dma descriptors the descriptor structure consists of four 32-bit words (16 bytes). These are shown in figure 357 . The bit descriptions of rdes0, rdes1, rdes2 and rdes3 are given below. Figure 3...

  • Page 1017

    Ethernet (eth): media access control (mac) with dma controller rm0008 1017/1128 docid13902 rev 15 bit 15 es: error summary indicates the logical or of the following bits: rdes0[1]: crc error rdes0[3]: receive error rdes0[4]: watchdog timeout rdes0[6]: late collision rdes0[7]: giant frame (this is no...

  • Page 1018

    Docid13902 rev 15 1018/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 bits 5, 7, and 0 reflect the conditions discussed in table 216 . • rdes1: receive descriptor word1 bit 3 re: receive error when set, this bit indicates that the rx_err signal is asserted while rx_d...

  • Page 1019

    Ethernet (eth): media access control (mac) with dma controller rm0008 1019/1128 docid13902 rev 15 • rdes2: receive descriptor word2 rdes2 contains the address pointer to the first data buffer in the descriptor, or it contains time stamp data. Bit 31 dic: disable interrupt on completion when set, thi...

  • Page 1020

    Docid13902 rev 15 1020/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 • rdes3: receive descriptor word3 rdes3 contains the address pointer either to the second data buffer in the descriptor or to the next descriptor, or it contains time stamp data. 29.6.9 dma interru...

  • Page 1021: 29.7 Ethernet

    Ethernet (eth): media access control (mac) with dma controller rm0008 1021/1128 docid13902 rev 15 interrupt. Even then, a new interrupt is generated, due to the active or pending receive buffer unavailable interrupt. Figure 358. Interrupt scheme 29.7 ethernet interrupts the ethernet controller has t...

  • Page 1022: 29.8

    Docid13902 rev 15 1022/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 eth_dmaier register. This timer is disabled before it runs out, when a frame is transferred to memory and the rs is set because it is enabled for that descriptor. Note: reading the pmt control and ...

  • Page 1023

    Ethernet (eth): media access control (mac) with dma controller rm0008 1023/1128 docid13902 rev 15 bits 19:17 ifg: interframe gap these bits control the minimum interframe gap between frames during transmission. 000: 96 bit times 001: 88 bit times 010: 80 bit times …. 111: 40 bit times note: in half-...

  • Page 1024

    Docid13902 rev 15 1024/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 bit 7 apcs: automatic pad/crc stripping when this bit is set, the mac strips the pad/fcs field on incoming frames only if the length’s field value is less than or equal to 1 500 bytes. All received...

  • Page 1025

    Ethernet (eth): media access control (mac) with dma controller rm0008 1025/1128 docid13902 rev 15 ethernet mac frame filter register (eth_macffr) address offset: 0x0004 reset value: 0x0000 0000 the mac frame filter register contains the filter controls for receiving frames. Some of the controls from...

  • Page 1026

    Docid13902 rev 15 1026/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 ethernet mac hash table high register (eth_machthr) address offset: 0x0008 reset value: 0x0000 0000 the 64-bit hash table is used for group address filtering. For hash filtering, the contents of th...

  • Page 1027

    Ethernet (eth): media access control (mac) with dma controller rm0008 1027/1128 docid13902 rev 15 the hash table high register contains the higher 32 bits of the multicast hash table. Ethernet mac hash table low register (eth_machtlr) address offset: 0x000c reset value: 0x0000 0000 the hash table lo...

  • Page 1028

    Docid13902 rev 15 1028/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 ethernet mac mii data register (eth_macmiidr) address offset: 0x0014 reset value: 0x0000 0000 the mac mii data register stores write data to be written to the phy register located at the address sp...

  • Page 1029

    Ethernet (eth): media access control (mac) with dma controller rm0008 1029/1128 docid13902 rev 15 transferred onto the cable. The host must make sure that the busy bit is cleared before writing to the register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pt ...

  • Page 1030

    Docid13902 rev 15 1030/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 ethernet mac vlan tag register (eth_macvlantr) address offset: 0x001c reset value: 0x0000 0000 the vlan tag register contains the ieee 802.1q vlan tag to identify the vlan frames. The mac compares ...

  • Page 1031

    Ethernet (eth): media access control (mac) with dma controller rm0008 1031/1128 docid13902 rev 15 ethernet mac remote wakeup frame filter register (eth_macrwuffr) address offset: 0x0028 reset value: 0x0000 0000 this is the address through which the remote wakeup frame filter registers are written/re...

  • Page 1032

    Docid13902 rev 15 1032/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 ethernet mac pmt control and status register (eth_macpmtcsr) address offset: 0x002c reset value: 0x0000 0000 the eth_macpmtcsr programs the request wakeup events and monitors the wakeup events. 31 ...

  • Page 1033

    Ethernet (eth): media access control (mac) with dma controller rm0008 1033/1128 docid13902 rev 15 ethernet mac interrupt status register (eth_macsr) address offset: 0x0038 reset value: 0x0000 0000 the eth_macsr register contents identify the events in the mac that can generate an interrupt. 15 14 13...

  • Page 1034

    Docid13902 rev 15 1034/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 ethernet mac interrupt mask register (eth_macimr) address offset: 0x003c reset value: 0x0000 0000 the eth_macimr register bits make it possible to mask the interrupt signal due to the corresponding...

  • Page 1035

    Ethernet (eth): media access control (mac) with dma controller rm0008 1035/1128 docid13902 rev 15 ethernet mac address 0 low register (eth_maca0lr) address offset: 0x0044 reset value: 0xffff ffff the mac address 0 low register holds the lower 32 bits of the 6-byte first mac address of the station. E...

  • Page 1036

    Docid13902 rev 15 1036/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 ethernet mac address1 low register (eth_maca1lr) address offset: 0x004c reset value: 0xffff ffff the mac address 1 low register holds the lower 32 bits of the 6-byte second mac address of the stati...

  • Page 1037

    Ethernet (eth): media access control (mac) with dma controller rm0008 1037/1128 docid13902 rev 15 ethernet mac address 2 low register (eth_maca2lr) address offset: 0x0054 reset value: 0xffff ffff the mac address 2 low register holds the lower 32 bits of the 6-byte second mac address of the station. ...

  • Page 1038

    Docid13902 rev 15 1038/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 ethernet mac address 3 low register (eth_maca3lr) address offset: 0x005c reset value: 0xffff ffff the mac address 3 low register holds the lower 32 bits of the 6-byte second mac address of the stat...

  • Page 1039

    Ethernet (eth): media access control (mac) with dma controller rm0008 1039/1128 docid13902 rev 15 29.8.2 mmc register description ethernet mmc control register (eth_mmccr) address offset: 0x0100 reset value: 0x0000 0000 the ethernet mmc control register establishes the operating mode of the manageme...

  • Page 1040

    Docid13902 rev 15 1040/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 ethernet mmc transmit interrupt register (eth_mmctir) address offset: 0x0108 reset value: 0x0000 0000 the ethernet mmc transmit interrupt register maintains the interrupts generated when transmit s...

  • Page 1041

    Ethernet (eth): media access control (mac) with dma controller rm0008 1041/1128 docid13902 rev 15 reset value: 0x0000 0000 the ethernet mmc receive interrupt mask register maintains the masks for interrupts generated when the receive statistic counters reach half their maximum value. (msb of the cou...

  • Page 1042

    Docid13902 rev 15 1042/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 ethernet mmc transmitted good frames after a single collision counter register (eth_mmctgfsccr) address offset: 0x014c reset value: 0x0000 0000 this register contains the number of successfully tra...

  • Page 1043

    Ethernet (eth): media access control (mac) with dma controller rm0008 1043/1128 docid13902 rev 15 ethernet mmc received frames with crc error counter register (eth_mmcrfcecr) address offset: 0x0194 reset value: 0x0000 0000 this register contains the number of frames received with crc error. Ethernet...

  • Page 1044

    Docid13902 rev 15 1044/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 29.8.3 ieee 1588 time stamp registers this section describes the registers required to support precision network clock synchronization functions under the ieee 1588 standard. Ethernet ptp time stam...

  • Page 1045

    Ethernet (eth): media access control (mac) with dma controller rm0008 1045/1128 docid13902 rev 15 this register contains the 8-bit value by which the subsecond register is incremented. In coarse update mode (tsfcu bit in eth_ptptscr), the value in this register is added to the system time every cloc...

  • Page 1046

    Docid13902 rev 15 1046/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 ethernet ptp time stamp high update register (eth_ptptshur) address offset: 0x0710 reset value: 0x0000 0000 this register contains the most significant (higher) 32 bits of the time to be written to...

  • Page 1047

    Ethernet (eth): media access control (mac) with dma controller rm0008 1047/1128 docid13902 rev 15 ethernet ptp time stamp low update register (eth_ptptslur) address offset: 0x0714 reset value: 0x0000 0000 this register contains the least significant (lower) 32 bits of the time to be written to, adde...

  • Page 1048

    Docid13902 rev 15 1048/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 ethernet ptp target time high register (eth_ptptthr) address offset: 0x071c reset value: 0x0000 0000 this register contains the higher 32 bits of time to be compared with the system time for interr...

  • Page 1049

    Ethernet (eth): media access control (mac) with dma controller rm0008 1049/1128 docid13902 rev 15 bits 31:26 reserved, must be kept at reset value. Bit 25 aab: address-aligned beats when this bit is set high and the fb bit equals 1, the ahb interface generates all bursts aligned to the start address...

  • Page 1050

    Docid13902 rev 15 1050/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 ethernet dma transmit poll demand register (eth_dmatpdr) address offset: 0x1004 reset value: 0x0000 0000 this register is used by the application to instruct the dma to poll the transmit descriptor...

  • Page 1051

    Ethernet (eth): media access control (mac) with dma controller rm0008 1051/1128 docid13902 rev 15 ethernet dma receive descriptor list address register (eth_dmardlar) address offset: 0x100c reset value: 0x0000 0000 the receive descriptor list address register points to the start of the receive descr...

  • Page 1052

    Docid13902 rev 15 1052/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 ethernet dma status register (eth_dmasr) address offset: 0x1014 reset value: 0x0000 0000 the status register contains all the status bits that the dma reports to the application. The eth_dmasr regi...

  • Page 1053

    Ethernet (eth): media access control (mac) with dma controller rm0008 1053/1128 docid13902 rev 15 bits 22:20 tps: transmit process state these bits indicate the transmit dma fsm state. This field does not generate an interrupt. 000: stopped; reset or stop transmit command issued 001: running; fetchi...

  • Page 1054

    Docid13902 rev 15 1054/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 ethernet dma operation mode register (eth_dmaomr) address offset: 0x1018 reset value: 0x0000 0000 bit 13 fbes: fatal bus error status this bit indicates that a bus error occurred, as detailed in [2...

  • Page 1055

    Ethernet (eth): media access control (mac) with dma controller rm0008 1055/1128 docid13902 rev 15 the operation mode register establishes the transmit and receive operating modes and commands. The eth_dmaomr register should be the last csr to be written as part of dma initialization. 31 30 29 28 27 ...

  • Page 1056

    Docid13902 rev 15 1056/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 bits 16:14 ttc: transmit threshold control these three bits control the threshold level of the transmit fifo. Transmission starts when the frame size within the transmit fifo is larger than the thr...

  • Page 1057

    Ethernet (eth): media access control (mac) with dma controller rm0008 1057/1128 docid13902 rev 15 bits 4:3 rtc: receive threshold control these two bits control the threshold level of the receive fifo. Transfer (request) to dma starts when the frame size within the receive fifo is larger than the th...

  • Page 1058

    Docid13902 rev 15 1058/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 ethernet dma interrupt enable register (eth_dmaier) address offset: 0x101c reset value: 0x0000 0000 the interrupt enable register enables the interrupts reported by eth_dmasr. Setting a bit to 1 en...

  • Page 1059

    Ethernet (eth): media access control (mac) with dma controller rm0008 1059/1128 docid13902 rev 15 the ethernet interrupt is generated only when the tsts or pmts bits of the dma status register is asserted with their corresponding interrupt are unmasked, or when the nis/ais status bit is asserted and...

  • Page 1060

    Docid13902 rev 15 1060/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 ethernet dma missed frame and buffer overflow counter register (eth_dmamfbocr) address offset: 0x1020 reset value: 0x0000 0000 the dma maintains two counters to track the number of missed frames du...

  • Page 1061

    Ethernet (eth): media access control (mac) with dma controller rm0008 1061/1128 docid13902 rev 15 ethernet dma current host transmit buffer address register (eth_dmachtbar) address offset: 0x1050 reset value: 0x0000 0000 the current host transmit buffer address register points to the current transmi...

  • Page 1062

    Docid13902 rev 15 1062/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 table 217. Ethernet register map and reset values off- set register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 eth_maccr reserved wd jd reserved ifg ...

  • Page 1063

    Ethernet (eth): media access control (mac) with dma controller rm0008 1063/1128 docid13902 rev 15 0x100 eth_mmccr reserved mcf ror csr cr reset value 0 0 0 0 0x104 eth_mmcrir reserved rguf s reserved rf aes rfces reserved reset value 0 0 0 0x108 eth_mmctir reserved tg fs reserved tg fmsc s tg fscs r...

  • Page 1064

    Docid13902 rev 15 1064/1128 rm0008 ethernet (eth): media access control (mac) with dma controller 1064 refer to table 3 on page 51 for the register boundary addresses. 0x718 eth_ptptsar tsa reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x71c eth_ptptthr ttsh reset value...

  • Page 1065: Device Electronic Signature

    Device electronic signature rm0008 1065/1128 docid13902 rev 15 30 device electronic signature low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102xx and stm3...

  • Page 1066: 30.2

    Docid13902 rev 15 1066/1128 rm0008 device electronic signature 1067 30.2 unique device id register (96 bits) the unique device identifier is ideally suited: • for use as serial numbers (for example usb string serial numbers or other end applications) • for use as security keys in order to increase t...

  • Page 1067

    Device electronic signature rm0008 1067/1128 docid13902 rev 15 address offset: 0x08 read only = 0xxxxx xxxx where x is factory-programmed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 u_id(95:80) r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 u_id(79:64) r r r r r r r r r r ...

  • Page 1068: Debug Support (Dbg)

    Docid13902 rev 15 1068/1128 rm0008 debug support (dbg) 1100 31 debug support (dbg) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102xx and stm32f103xx mic...

  • Page 1069

    Debug support (dbg) rm0008 1069/1128 docid13902 rev 15 figure 360. Block diagram of stm32 mcu and cortex ® -m3-level debug support note: the debug features embedded in the cortex ® -m3 core are a subset of the arm ® coresight design kit. The arm ® cortex ® -m3 core provides integrated on-chip debug ...

  • Page 1070: 31.2 Reference

    Docid13902 rev 15 1070/1128 rm0008 debug support (dbg) 1100 31.2 reference arm ® documentation • cortex ® -m3 r1p1 technical reference manual (trm) it is available from: http://infocenter.Arm.Com/help/topic/com.Arm.Doc.Ddi0337e/ddi0337e_cortex_m3_r1p 1_trm.Pdf • arm ® debug interface v5 • arm ® core...

  • Page 1071: 31.4

    Debug support (dbg) rm0008 1071/1128 docid13902 rev 15 31.3.1 mechanism to select the jtag-dp or the sw-dp by default, the jtag-debug port is active. If the debugger host wants to switch to the sw-dp, it must provide a dedicated jtag sequence on tms/tck (respectively mapped to swdio and swclk) which...

  • Page 1072

    Docid13902 rev 15 1072/1128 rm0008 debug support (dbg) 1100 31.4.1 swj debug port pins five pins are used as outputs from the stm32f10xxx for the swj-dp as alternate functions of general-purpose i/os. These pins are available on all packages. 31.4.2 flexible swj-dp pin assignment after reset (sysres...

  • Page 1073

    Debug support (dbg) rm0008 1073/1128 docid13902 rev 15 note: when the apb bridge write buffer is full, it takes one extra apb cycle when writing the afio_mapr register. This is because the deactivation of the jtagsw pins is done in two cycles to guarantee a clean level on the ntrst and tck input sig...

  • Page 1074: 31.5

    Docid13902 rev 15 1074/1128 rm0008 debug support (dbg) 1100 31.4.4 using serial wire and releasing the unused debug pins as gpios to use the serial wire dp to release some gpios, the user software must set swj_cfg=010 just after reset. This releases pa15, pb3 and pb4 which now become available as gp...

  • Page 1075

    Debug support (dbg) rm0008 1075/1128 docid13902 rev 15 figure 362. Jtag tap connections boundary scan tap njtrst cortex-m3 tap jtms tms ntrst tms ntrst jtdi jtdo tdi tdo tdi tdo sw-dp stm32 mcu selected ir is 5-bit wide ir is 4-bit wide ai14981b.

  • Page 1076: 31.6

    Docid13902 rev 15 1076/1128 rm0008 debug support (dbg) 1100 31.6 id codes and locking mechanism there are several id codes inside the stm32f10xxx mcus. St strongly recommends tools designers to lock their debuggers using the mcu device id code located in the external ppb memory map at address 0xe004...

  • Page 1077

    Debug support (dbg) rm0008 1077/1128 docid13902 rev 15 31.6.2 boundary scan tap jtag id code the tap of the stm32f10xxx bsc (boundary scan) integrates a jtag id code equal to • in low-density devices: – 0x06412041 = revision a • in medium-density devices: – 0x06410041 = revision a – 0x16410041 = rev...

  • Page 1078: 31.7

    Docid13902 rev 15 1078/1128 rm0008 debug support (dbg) 1100 31.6.3 cortex ® -m3 tap the tap of the arm ® cortex ® -m3 integrates a jtag id code. This id code is the arm ® default one and has not been modified. This code is only accessible by the jtag debug port. This code is 0x3ba00477(corresponds t...

  • Page 1079

    Debug support (dbg) rm0008 1079/1128 docid13902 rev 15 1011 apacc [35 bits] access port access register initiates an access port and allows access to an access port register. – when transferring data in: bits 34:3 = data[31:0] = 32-bit data to shift in for a write request bits 2:1 = a[3:2] = 2-bit a...

  • Page 1080: 31.8

    Docid13902 rev 15 1080/1128 rm0008 debug support (dbg) 1100 31.8 sw debug port 31.8.1 sw protocol introduction this synchronous serial protocol uses two pins: • swclk: clock from host to target • swdio: bidirectional the protocol allows two banks of registers (dpacc registers and apacc registers) to...

  • Page 1081

    Debug support (dbg) rm0008 1081/1128 docid13902 rev 15 refer to the cortex ® -m3 r1p1 trm for a detailed description of dpacc and apacc registers. The packet request is always followed by the turnaround time (default 1 bit) where neither the host nor target drive the line. The ack response must be f...

  • Page 1082

    Docid13902 rev 15 1082/1128 rm0008 debug support (dbg) 1100 note: note that the sw-dp state machine is inactive until the target reads this id code. • the sw-dp state machine is in reset state either after power-on reset, or after the dp has switched from jtag to swd or after the line is high for mo...

  • Page 1083

    Debug support (dbg) rm0008 1083/1128 docid13902 rev 15 31.8.6 sw-ap registers access to these registers are initiated when apndp=1 there are many ap registers (see ahb-ap) addressed as the combination of: • the shifted value a[3:2] • the current value of the dp select register 01 read/write 0 dp- ct...

  • Page 1084: 31.9

    Docid13902 rev 15 1084/1128 rm0008 debug support (dbg) 1100 31.9 ahb-ap (ahb access port) - valid for both jtag-dp and sw-dp features: • system access is independent of the processor status. • either sw-dp or jtag-dp accesses ahb-ap. • the ahb-ap is an ahb master into the bus matrix. Consequently, i...

  • Page 1085: 31.10 Core

    Debug support (dbg) rm0008 1085/1128 docid13902 rev 15 31.10 core debug core debug is accessed through the core debug registers. Debug access to these registers is by means of the advanced high-performance bus (ahb-ap) port. The processor can access these registers directly over the internal private...

  • Page 1086: 31.11

    Docid13902 rev 15 1086/1128 rm0008 debug support (dbg) 1100 31.11 capability of the debugger host to connect under system reset the reset system of the stm32f10xxx mcu comprises the following reset sources: • por (power-on reset) which asserts a reset at each power-up. • internal watchdog reset • so...

  • Page 1087: 31.13

    Debug support (dbg) rm0008 1087/1128 docid13902 rev 15 31.13 dwt (data watchpoint trigger) the dwt unit consists of four comparators. They are configurable as: • a hardware watchpoint or • a trigger to an etm or • a pc sampler or • a data address sampler the dwt also provides some means to give some...

  • Page 1088

    Docid13902 rev 15 1088/1128 rm0008 debug support (dbg) 1100 for this, the dwt must be configured to trigger the itm: the bit cyccntena (bit0) of the dwt control register must be set. In addition, the bit2 (syncena) of the itm trace control register must be set. Note: if the synena bit is not set, th...

  • Page 1089: 31.15

    Debug support (dbg) rm0008 1089/1128 docid13902 rev 15 example of configuration to output a simple value to the tpiu: • configure the tpiu and assign trace i/os by configuring the dbgmcu_cr (refer to section 31.17.2: trace pin assignment and section 31.16.3: debug mcu configuration register ) • writ...

  • Page 1090: 31.16

    Docid13902 rev 15 1090/1128 rm0008 debug support (dbg) 1100 31.15.3 main etm registers for more information on registers refer to the chapter 3 of the arm ® ihi 0014n specification. 31.15.4 configuration example to output a simple value to the tpiu: • configure the tpiu and enable the i/io_tracen to...

  • Page 1091

    Debug support (dbg) rm0008 1091/1128 docid13902 rev 15 31.16.1 debug support for low-power modes to enter low-power mode, the instruction wfi or wfe must be executed. The mcu implements several low-power modes which can either deactivate the cpu clock or reduce the power of the cpu. The core does no...

  • Page 1092

    Docid13902 rev 15 1092/1128 rm0008 debug support (dbg) 1100 dbgmcu_cr register address: 0xe004 2004 only 32-bit access supported por reset: 0x0000 0000 (not reset by system reset) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res. Dbg_ tim11 _ stop dbg_ tim10 _ stop dbg_ tim9_ stop dbg_ tim14 _ st...

  • Page 1093

    Debug support (dbg) rm0008 1093/1128 docid13902 rev 15 bit 9 dbg_wwdg_stop:debug window watchdog stopped when core is halted 0: the window watchdog counter clock continues even if the core is halted 1: the window watchdog counter clock is stopped when the core is halted bit 8 dbg_iwdg_stop:debug ind...

  • Page 1094: 31.17

    Docid13902 rev 15 1094/1128 rm0008 debug support (dbg) 1100 31.17 tpiu (trace port interface unit) 31.17.1 introduction the tpiu acts as a bridge between the on-chip trace data from the itm and the etm. The output data stream encapsulates the trace source id, that is then captured by a trace port an...

  • Page 1095

    Debug support (dbg) rm0008 1095/1128 docid13902 rev 15 31.17.2 trace pin assignment • asynchronous mode the asynchronous mode requires 1 extra pin and is available on all packages. It is only available if using serial wire mode (not in jtag mode). • synchronous mode the synchronous mode requires fro...

  • Page 1096

    Docid13902 rev 15 1096/1128 rm0008 debug support (dbg) 1100 note: by default, the traceclkin input clock of the tpiu is tied to gnd. It is assigned to hclk two clock cycles after the bit trace_ioen has been set. The debugger must then program the trace mode by writing the protocol[1:0] bits in the s...

  • Page 1097

    Debug support (dbg) rm0008 1097/1128 docid13902 rev 15 note: refer to the arm ® coresight architecture specification v1.0 (arm ® ihi 0029b) for further information 31.17.4 tpui frame synchronization packets the tpui can generate two types of synchronization packets: • the frame synchronization packe...

  • Page 1098

    Docid13902 rev 15 1098/1128 rm0008 debug support (dbg) 1100 31.17.7 asynchronous mode this is a low cost alternative to output the trace using only 1 pin: this is the asynchronous output pin traceswo. Obviously there is a limited bandwidth. Traceswo is multiplexed with jtdo when using the sw-dp pin....

  • Page 1099

    Debug support (dbg) rm0008 1099/1128 docid13902 rev 15 31.17.10 example of configuration • set the bit trcena in the debug exception and monitor control register (demcr) • write the tpiu current port size register to the desired value (default is 0x1 for a 1-bit port size) • write tpiu formatter and...

  • Page 1100: 31.18

    Docid13902 rev 15 1100/1128 rm0008 debug support (dbg) 1100 31.18 dbg register map the following table summarizes the debug registers. . Table 234. Dbg register map and reset values addr. Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0xe004 2000 dbgmc...

  • Page 1101: 32 Revision

    Revision history rm0008 1101/1128 docid13902 rev 15 32 revision history table 235. Document revision history date revision changes 19-oct-2007 1 document reference number changed from um0306 to rm0008. The changes below were made with reference to revision 1 of 01-jun-2007 of um0306. Extsel[2:0] and...

  • Page 1102

    Docid13902 rev 15 1102/1128 rm0008 revision history 1120 19-oct-2007 continued 1 continued figure 114: counter timing diagram, internal clock divided by 1, timx_arr=0x6 and figure 129: output compare mode, toggle on oc1 modified. Ckd definition modified in section 15.4.1: timx control register 1 (ti...

  • Page 1103

    Revision history rm0008 1103/1128 docid13902 rev 15 20-nov- 2007 2 figure 278: usart block diagram modified. Procedure modified in character reception on page 788 . In section 27.3.4: fractional baud rate generation : – equation legend modified – table 192: error calculation for programmed baud rate...

  • Page 1104

    Docid13902 rev 15 1104/1128 rm0008 revision history 1120 08-feb- 2008 3 figure 4: power supply overview on page 68 modified. Section 7.1.2: power reset on page 91 modified. Section 7.2: clocks on page 92 modified. Definition of bits 26:24 modified in section 9.4.2: af remap and debug i/o configurati...

  • Page 1105

    Revision history rm0008 1105/1128 docid13902 rev 15 22-may- 2008 continued 4 (continued) in section 7: low-, medium-, high- and xl-density reset and clock control (rcc) on page 90 : – lsi calibration on page 97 added. Figure 7: simplified diagram of the reset circuit on page 91 updated – apb2 periph...

  • Page 1106

    Docid13902 rev 15 1106/1128 rm0008 revision history 1120 22-may- 2008 continued 4 continued figure 234: can frames on page 663 modified. Bits 31:21 and bits 20:3 modified in can tx mailbox identifier register (can_tixr) (x=0..2) on page 676 . Bits 31:21 and bits 20:3 modified in can receive fifo mai...

  • Page 1107

    Revision history rm0008 1107/1128 docid13902 rev 15 26-sep- 2008 6 this reference manual also applies to low-density stm32f101xx, stm32f102xx and stm32f103xx devices, and to medium-density stm32f102xx devices. In all sections, definitions of low-density and medium-density devices updated. Section 2....

  • Page 1108

    Docid13902 rev 15 1108/1128 rm0008 revision history 1120 23-dec- 2008 7 memory map figure removed from reference manual. Section 3.1: system architecture on page 48 modified. Section 3.4: boot configuration on page 61 modified. Exiting sleep mode on page 73 modified. Section 6.3.2: rtc calibration o...

  • Page 1109

    Revision history rm0008 1109/1128 docid13902 rev 15 11-feb- 2009 8 reset value corrected in section 4.4.1: data register (crc_dr) . Section 11.10: temperature sensor modified. Reset value corrected in section 11.12.7: adc watchdog high threshold register (adc_htr) . Section 12.3.9: triangle-wave gen...

  • Page 1110

    Docid13902 rev 15 1110/1128 rm0008 revision history 1120 22-jun- 2009 9 reference manual updated to support also stm32f105xx/stm32f107xx connectivity line devices. Memory and bus architecture section: embedded boot loader updated. Section 4.3: crc functional description updated. Note modified in sec...

  • Page 1111

    Revision history rm0008 1111/1128 docid13902 rev 15 04-dec- 2009 10 (to be continued on next page) references to the stm32f10xxx cortex-m3 programming manual (pm0056) made throughout the document. The gpio, afio, exti, adc, dac, can, fsmc, sdio, usb_otg registers are accessed by words (32 bits). The...

  • Page 1112

    Docid13902 rev 15 1112/1128 rm0008 revision history 1120 04-dec- 2009 10 continued txfelvl bit description modified in otg_fs ahb configuration register (otg_fs_gahbcfg) . Nptxfe bit description modified in otg_fs core interrupt register (otg_fs_gintsts) . Nptxfem bit description modified in otg_fs ...

  • Page 1113

    Revision history rm0008 1113/1128 docid13902 rev 15 23-apr-2010 11 xl-density devices added. Flash access control register (flash_acr) inserted. External source (hse bypass) and external source (hse bypass) : maximum hse frequency modified. Hsebyp bit description modified in section 7.3.1: clock con...

  • Page 1114

    Docid13902 rev 15 1114/1128 rm0008 revision history 1120 12-jan-2011 12 added section 1: overview of the manual added fsmc boundary addresses to table 3 on page 51 added paragraph on hsi to programming and erasing the flash memory on page 60 updated table 11.12.12: adc injected sequence register (ad...

  • Page 1115

    Revision history rm0008 1115/1128 docid13902 rev 15 17-may- 2011 13 updated spi table in section 9.1.11: gpio configurations for device peripherals on page 166 updated bit descriptions in section 7.3.1: clock control register (rcc_cr) on page 99 and section 8.3.1: clock control register (rcc_cr) on ...

  • Page 1116

    Docid13902 rev 15 1116/1128 rm0008 revision history 1120 20-oct-2011 14 changed references to programming manual from pm0042 to pm0075. Adc: removed scan mode note from awdie in section 11.12.2 on page 237 updated section 11.3.8: scan mode on page 220 to refer to dma use. Dma: added tim8 and tim7 dm...

  • Page 1117

    Revision history rm0008 1117/1128 docid13902 rev 15 02-jun- 2014 15 updated table 3: register boundary addresses restricted hyperlinks to homepages. Pwr: added note related to hse failure in section : entering stop mode . Updated note related to stop mode entry in table 14: stop mode . Changed condi...

  • Page 1118

    Docid13902 rev 15 1118/1128 rm0008 revision history 1120 02-jun- 2014 15 (continued) timer 2 to 5: removed all mentions to “repetition counter”. Renamed figure 113: counter timing diagram, update event . Updated figure 127: output stage of capture/compare channel (channel 1) . Updated figure 140: ma...

  • Page 1119

    Revision history rm0008 1119/1128 docid13902 rev 15 02-jun- 2014 15 (continued) fsmc: updated figure 185: fsmc block diagram . Updated table 109 to table 128 . Replaced all occurrences of datalat by datlat in the whole section. Updated section 21.1: fsmc main features . Replace sram/cram by sram/psr...

  • Page 1120

    Docid13902 rev 15 1120/1128 rm0008 revision history 1120 02-jun- 2014 15 (continued) bxcan: added register access in section 24.9: can registers . Updated figure 222: dual can block diagram (connectivity devices) . Updated definition of can2sb bits in section : can filter master register (can_fmr) ....

  • Page 1121: Index

    Index rm0008 1121/1128 docid13902 rev 15 index a adc_cr1 . . . . . . . . . . . . . . . . . . . . . . . . . . .237 adc_cr2 . . . . . . . . . . . . . . . . . . . . . . . . . . .239 adc_dr . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 adc_htr . . . . . . . . . . . . . . . . . . . . . . . ....

  • Page 1122

    Docid13902 rev 15 1122/1128 rm0008 index 1127 can_rixr . . . . . . . . . . . . . . . . . . . . . . . . . . .679 can_tdhxr . . . . . . . . . . . . . . . . . . . . . . . . .678 can_tdlxr . . . . . . . . . . . . . . . . . . . . . . . . .678 can_tdtxr . . . . . . . . . . . . . . . . . . . . . . . . .677...

  • Page 1123

    Index rm0008 1123/1128 docid13902 rev 15 eth_macsr . . . . . . . . . . . . . . . . . . . . . . . .1033 eth_macvlantr . . . . . . . . . . . . . . . . . . .1030 eth_mmccr . . . . . . . . . . . . . . . . . . . . . . .1039 eth_mmcrfaecr . . . . . . . . . . . . . . . . . . .1043 eth_mmcrfcecr . . . . . ....

  • Page 1124

    Docid13902 rev 15 1124/1128 rm0008 index 1127 i2c_sr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .770 i2c_sr2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .774 i2c_trise . . . . . . . . . . . . . . . . . . . . . . . . . . .776 iwdg_kr . . . . . . . . . . . . . . . . . . . . ....

  • Page 1125

    Index rm0008 1125/1128 docid13902 rev 15 otg_fs_hfir . . . . . . . . . . . . . . . . . . . . . . .872 otg_fs_hfnum . . . . . . . . . . . . . . . . . . . . .873 otg_fs_hprt . . . . . . . . . . . . . . . . . . . . . . .875 otg_fs_hptxfsiz . . . . . . . . . . . . . . . . . . .870 otg_fs_hptxsts . . . ....

  • Page 1126

    Docid13902 rev 15 1126/1128 rm0008 index 1127 spi_dr . . . . . . . . . . . . . . . . . . . . . . . . . . . . .737 spi_i2scfgr . . . . . . . . . . . . . . . . . . . . . . . .739 spi_i2spr . . . . . . . . . . . . . . . . . . . . . . . . . . .740 spi_rxcrcr . . . . . . . . . . . . . . . . . . . . . . ....

  • Page 1127

    Index rm0008 1127/1128 docid13902 rev 15 wwdg_cr . . . . . . . . . . . . . . . . . . . . . . . . . .495 wwdg_sr . . . . . . . . . . . . . . . . . . . . . . . . . .496.

  • Page 1128

    Docid13902 rev 15 1128/1128 rm0008 1128 please read carefully: information in this document is provided solely in connection with st products. Stmicroelectronics nv and its subsidiaries (“st”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the pr...