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ST STM32F101xx series Reference Manual

Other manuals for STM32F101xx series: Reference Manual
Manual is about: advanced ARM-based 32-bit MCUs

Summary of STM32F101xx series

  • Page 1

    January 2011 doc id 13902 rev 12 1/1096 rm0008 reference manual stm32f101xx, stm32f102xx, stm32f103xx, stm32f105xx and stm32f107xx advanced arm-based 32-bit mcus introduction this reference manual targets application developers. It provides complete information on how to use the stm32f101xx, stm32f1...

  • Page 2: Contents

    Contents rm0008 2/1096 doc id 13902 rev 12 contents 1 overview of the manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2 documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.1 list of abbreviations for registers . . . . ....

  • Page 3

    Rm0008 contents doc id 13902 rev 12 3/1096 5.2.2 programmable voltage detector (pvd) . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.3.1 slowing down system clocks . . . . . . . . . . . ...

  • Page 4

    Contents rm0008 4/1096 doc id 13902 rev 12 7.2.4 lse clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2.5 lsi clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2.6 system clock (sysclk)...

  • Page 5

    Rm0008 contents doc id 13902 rev 12 5/1096 8.3.1 clock control register (rcc_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8.3.2 clock configuration register (rcc_cfgr) . . . . . . . . . . . . . . . . . . . . . 131 8.3.3 clock interrupt register (rcc_cir) . . . . . . . . . . . . ...

  • Page 6

    Contents rm0008 6/1096 doc id 13902 rev 12 9.3.2 using osc_in/osc_out pins as gpio ports pd0/pd1 . . . . . . . . . . 169 9.3.3 can1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 9.3.4 can2 alternate function remapping . . . . . . . . . . . . . . . . . . . . ....

  • Page 7

    Rm0008 contents doc id 13902 rev 12 7/1096 10.3.6 pending register (exti_pr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 10.3.7 exti register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11 analog-to-digital converter (adc) . . . . ....

  • Page 8

    Contents rm0008 8/1096 doc id 13902 rev 12 11.12.2 adc control register 1 (adc_cr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 11.12.3 adc control register 2 (adc_cr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 11.12.4 adc sample time register 1 (adc_smpr1) . . . . . . ...

  • Page 9

    Rm0008 contents doc id 13902 rev 12 9/1096 12.4.9 simultaneous trigger with different lfsr generation . . . . . . . . . . . . . 253 12.4.10 simultaneous trigger with same triangle generation . . . . . . . . . . . . . . 253 12.4.11 simultaneous trigger with different triangle generation . . . . . . ....

  • Page 10

    Contents rm0008 10/1096 doc id 13902 rev 12 13.4 dma registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 13.4.1 dma interrupt status register (dma_isr) . . . . . . . . . . . . . . . . . . . . . . 273 13.4.2 dma interrupt flag clear register (dma_if...

  • Page 11

    Rm0008 contents doc id 13902 rev 12 11/1096 14.4 tim1&tim8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 14.4.1 tim1&tim8 control register 1 (timx_cr1) . . . . . . . . . . . . . . . . . . . . . 321 14.4.2 tim1&tim8 control register 2 (timx_cr2) . . . . ....

  • Page 12

    Contents rm0008 12/1096 doc id 13902 rev 12 15.3.11 clearing the ocxref signal on an external event . . . . . . . . . . . . . . . 372 15.3.12 encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 15.3.13 timer input xor function . . . . . . . . . . . . . ...

  • Page 13

    Rm0008 contents doc id 13902 rev 12 13/1096 16.4.5 input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 16.4.6 pwm input mode (only for tim9/12) . . . . . . . . . . . . . . . . . . . . . . . . . . 419 16.4.7 forced output mode . . . . . . . . . . . . ....

  • Page 14

    Contents rm0008 14/1096 doc id 13902 rev 12 16.6.11 tim10/11/13/14 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 17 basic timers (tim6&tim7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 17.1 tim6&tim7 introduction . . . . . . . . . . . ...

  • Page 15

    Rm0008 contents doc id 13902 rev 12 15/1096 18.4.6 rtc alarm register high (rtc_alrh / rtc_alrl) . . . . . . . . . . . . . . 474 18.4.7 rtc register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 19 independent watchdog (iwdg) . . . . . . . . . . . . . . . ...

  • Page 16

    Contents rm0008 16/1096 doc id 13902 rev 12 21.4.2 nand/pc card address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 21.5 nor flash/psram controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 21.5.1 external memory interface signals . . . . . . . . . ....

  • Page 17

    Rm0008 contents doc id 13902 rev 12 17/1096 22.4.11 card status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 22.4.12 sd status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 22.4.13 sd i/o mode . . . . . . . ...

  • Page 18

    Contents rm0008 18/1096 doc id 13902 rev 12 22.9.12 sdio interrupt clear register (sdio_icr) . . . . . . . . . . . . . . . . . . . . . . 592 22.9.13 sdio mask register (sdio_mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 22.9.14 sdio fifo counter register (sdio_fifocnt) . . . . . . ...

  • Page 19

    Rm0008 contents doc id 13902 rev 12 19/1096 24.5.1 silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 24.5.2 loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 24.5.3 loop back combined with sile...

  • Page 20

    Contents rm0008 20/1096 doc id 13902 rev 12 25.3.11 spi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696 25.4 i 2 s functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697 25.4.1 i 2 s general descriptio...

  • Page 21

    Rm0008 contents doc id 13902 rev 12 21/1096 26.5 i 2 c debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 26.6 i 2 c registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 26.6.1 control register 1 (...

  • Page 22

    Contents rm0008 22/1096 doc id 13902 rev 12 27.6.2 data register (usart_dr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794 27.6.3 baud rate register (usart_brr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794 27.6.4 control register 1 (usart_cr1) . . . . . . . . . ...

  • Page 23

    Rm0008 contents doc id 13902 rev 12 23/1096 28.11 peripheral fifo architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820 28.11.1 peripheral rx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820 28.11.2 peripheral tx fifos . . . . . . . ...

  • Page 24

    Contents rm0008 24/1096 doc id 13902 rev 12 29.3 ethernet pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941 29.4 ethernet functional description: smi, mii and rmii . . . . . . . . . . . . . . . . 942 29.4.1 station management interface: smi . . . . . ...

  • Page 25

    Rm0008 contents doc id 13902 rev 12 25/1096 30.1.1 flash size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045 30.2 unique device id register (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046 31 debug support (dbg) . . . . . . . . . . ....

  • Page 26

    Contents rm0008 26/1096 doc id 13902 rev 12 31.15 etm (embedded trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067 31.15.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067 31.15.2 signal protocol, packet types . . . . . ....

  • Page 27: List of Tables

    Rm0008 list of tables doc id 13902 rev 12 27/1096 list of tables table 1. Sections related to each stm32f10xxx product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 2. Sections related to each peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

  • Page 28

    List of tables rm0008 28/1096 doc id 13902 rev 12 table 49. Tim11 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 50. Tim13 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 29

    Rm0008 list of tables doc id 13902 rev 12 29/1096 table 100. External memory address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 table 101. Memory mapping and timing registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 30

    List of tables rm0008 30/1096 doc id 13902 rev 12 table 152. Erase offset field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 table 153. Block-oriented write commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

  • Page 31

    Rm0008 list of tables doc id 13902 rev 12 31/1096 table 201. Data fifo (dfifo) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831 table 202. Power and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831 ...

  • Page 32: List of Figures

    List of figures rm0008 32/1096 doc id 13902 rev 12 list of figures figure 1. System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 2. System architecture in connectivity line devices. . . . . . . . . . . . . . . . . ...

  • Page 33

    Rm0008 list of figures doc id 13902 rev 12 33/1096 figure 49. Dma block diagram in low-, medium- high- and xl-density devices . . . . . . . . . . . . . . . . 265 figure 50. Dma1 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 fi...

  • Page 34

    List of figures rm0008 34/1096 doc id 13902 rev 12 figure 99. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 320 figure 100. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 35

    Rm0008 list of figures doc id 13902 rev 12 35/1096 figure 151. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 figure 152. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4...

  • Page 36

    List of figures rm0008 36/1096 doc id 13902 rev 12 figure 199. Asynchronous wait during a read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 figure 200. Asynchronous wait during a write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 37

    Rm0008 list of figures doc id 13902 rev 12 37/1096 discontinuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690 figure 246. Transmission using dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 38

    List of figures rm0008 38/1096 doc id 13902 rev 12 figure 297. Hardware flow control between two usarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789 figure 298. Rts flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

  • Page 39

    Rm0008 list of figures doc id 13902 rev 12 39/1096 figure 349. Ptp trigger output to tim2 itr1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978 figure 350. Pps output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

  • Page 40: Overview Of The Manual

    Overview of the manual rm0008 40/1096 doc id 13902 rev 12 1 overview of the manual legend for table 1 : the section in each row applies to products in columns marked with “ • " table 1. Sections related to each stm32f10xxx product lo w-de nsity stm32 f 10 1xx medium-dens ity stm3 2f1 01x x high a n ...

  • Page 41

    Rm0008 overview of the manual doc id 13902 rev 12 41/1096 section 12: digital-to- analog converter (dac) • • • • section 14: advanced- control timers (tim1&tim8) • • • • • • section 15: general- purpose timers (tim2 to tim5) • • • • • • • • • • section 16: general- purpose timers (tim9 to tim14) • (...

  • Page 42

    Overview of the manual rm0008 42/1096 doc id 13902 rev 12 note: 1) available only on xl-density devices section 26: inter- integrated circuit (i2c) interface • • • • • • • • • • section 27: universal synchronous asynchronous receiver transmitter (usart) • • • • • • • • • • section 28: usb on- the-go...

  • Page 43

    Rm0008 overview of the manual doc id 13902 rev 12 43/1096 legend for table 2 : • the section in this row must be read when using the peripherals in columns marked with “ • " ◊ the section in this row can optionally be read when using the peripherals in columns marked with “ ◊ " table 2. Sections rel...

  • Page 44

    Overview of the manual rm0008 44/1096 doc id 13902 rev 12 section 11: analog-to- digital converter (adc) • section 12: digital-to- analog converter (dac) • section 14: advanced- control timers (tim1&tim8) ◊ ◊ • section 15: general- purpose timers (tim2 to tim5) ◊ ◊ • section 16: general- purpose tim...

  • Page 45

    Rm0008 overview of the manual doc id 13902 rev 12 45/1096 section 25: serial peripheral interface (spi) • section 26: inter- integrated circuit (i2c) interface • section 27: universal synchronous asynchronous receiver transmitter (usart) • section 28: usb on- the-go full-speed (otg_fs) • section 29:...

  • Page 46: 2 Documentation

    Documentation conventions rm0008 46/1096 doc id 13902 rev 12 2 documentation conventions 2.1 list of abbreviations for registers the following abbreviations are used in register descriptions: 2.2 glossary ● low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the f...

  • Page 47: Memory And Bus Architecture

    Rm0008 memory and bus architecture doc id 13902 rev 12 47/1096 3 memory and bus architecture 3.1 system architecture in low-, medium-, high- and xl-density devices, the main system consists of: ● four masters: – cortex™-m3 core dcode bus (d-bus) and system bus (s-bus) – gp-dma1 & 2 (general-purpose ...

  • Page 48

    Memory and bus architecture rm0008 48/1096 doc id 13902 rev 12 in connectivity line devices the main system consists of: ● five masters: – cortex™-m3 core dcode bus (d-bus) and system bus (s-bus) – gp-dma1 & 2 (general-purpose dma) – ethernet dma ● three slaves: – internal sram – internal flash memo...

  • Page 49: 3.2 Memory

    Rm0008 memory and bus architecture doc id 13902 rev 12 49/1096 dcode bus this bus connects the dcode bus (literal load and debug access) of the cortex™-m3 core to the flash memory data interface. System bus this bus connects the system bus of the cortex™-m3 core (peripherals bus) to a busmatrix whic...

  • Page 50: 3.3 Memory

    Memory and bus architecture rm0008 50/1096 doc id 13902 rev 12 3.3 memory map see the datasheet corresponding to your device for a comprehensive diagram of the memory map. Table 3 gives the boundary addresses of the peripherals available in all stm32f10xxx devices. Table 3. Register boundary address...

  • Page 51

    Rm0008 memory and bus architecture doc id 13902 rev 12 51/1096 0x4001 5800 - 0x4001 7fff reserved apb2 0x4001 5400 - 0x4001 57ff tim11 timer section 16.5.14 on page 441 0x4001 5000 - 0x4001 53ff tim10 timer section 16.5.14 on page 441 0x4001 4c00 - 0x4001 4fff tim9 timer section 16.5.14 on page 441 ...

  • Page 52

    Memory and bus architecture rm0008 52/1096 doc id 13902 rev 12 0x4000 7800 - 0x4000 ffff reserved apb1 0x4000 7400 - 0x4000 77ff dac section 12.5.14 on page 262 0x4000 7000 - 0x4000 73ff power control pwr section 5.4.3 on page 78 0x4000 6c00 - 0x4000 6fff backup registers (bkp) section 6.4.5 on page...

  • Page 53

    Rm0008 memory and bus architecture doc id 13902 rev 12 53/1096 3.3.1 embedded sram the stm32f10xxx features up to 96 kbytes of static sram. It can be accessed as bytes, half-words (16 bits) or full words (32 bits). The sram start address is 0x2000 0000. 3.3.2 bit banding the cortex™-m3 memory map in...

  • Page 54

    Memory and bus architecture rm0008 54/1096 doc id 13902 rev 12 3.3.3 embedded flash memory the high-performance flash memory module has the following key features: ● for xl-density devices: density of up to 1 mbyte with dual bank architecture for read- while-write (rww) capability: – bank 1: fixed s...

  • Page 55

    Rm0008 memory and bus architecture doc id 13902 rev 12 55/1096 information block system memory 0x1fff f000 - 0x1fff f7ff 2 kbytes option bytes 0x1fff f800 - 0x1fff f80f 16 flash memory interface registers flash_acr 0x4002 2000 - 0x4002 2003 4 flash_keyr 0x4002 2004 - 0x4002 2007 4 flash_optkeyr 0x40...

  • Page 56

    Memory and bus architecture rm0008 56/1096 doc id 13902 rev 12 table 6. Flash module organization (high-density devices) block name base addresses size (bytes) main memory page 0 0x0800 0000 - 0x0800 07ff 2 kbytes page 1 0x0800 0800 - 0x0800 0fff 2 kbytes page 2 0x0800 1000 - 0x0800 17ff 2 kbytes pa...

  • Page 57

    Rm0008 memory and bus architecture doc id 13902 rev 12 57/1096 table 7. Flash module organization (connectivity line devices) block name base addresses size (bytes) main memory page 0 0x0800 0000 - 0x0800 07ff 2 kbytes page 1 0x0800 0800 - 0x0800 0fff 2 kbytes page 2 0x0800 1000 - 0x0800 17ff 2 kbyt...

  • Page 58

    Memory and bus architecture rm0008 58/1096 doc id 13902 rev 12 note: for further information on the flash memory interface registers, please refer to the: ● “stm32f10xxx xl-density flash programming manual” (pm0068) for xl-density devices ● “stm32f10xxx flash programming manual” (pm0042) for other d...

  • Page 59

    Rm0008 memory and bus architecture doc id 13902 rev 12 59/1096 note: 1 these options should be used in accordance with the flash memory access time. The wait states represent the ratio of the sysclk (system clock) period to the flash memory access time: zero wait state, if 0 ≤ 24 mhz one wait state,...

  • Page 60: 3.4 Boot

    Memory and bus architecture rm0008 60/1096 doc id 13902 rev 12 flash access control register (flash_acr) address offset: 0x00 reset value: 0x0000 0030 3.4 boot configuration in the stm32f10xxx, 3 different boot modes can be selected through boot[1:0] pins as shown in table 9 . The values on the boot...

  • Page 61

    Rm0008 memory and bus architecture doc id 13902 rev 12 61/1096 delay has elapsed, the cpu fetches the top-of-stack value from address 0x0000 0000, then starts code execution from the boot memory starting from 0x0000 0004. Due to its fixed memory map, the code area starts from address 0x0000 0000 (ac...

  • Page 62: Crc Calculation Unit

    Crc calculation unit rm0008 62/1096 doc id 13902 rev 12 4 crc calculation unit low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102xx and stm32f103xx microco...

  • Page 63: 4.3

    Rm0008 crc calculation unit doc id 13902 rev 12 63/1096 4.3 crc functional description the crc calculation unit mainly consists of a single 32-bit data register, which: ● is used as an input register to enter new data in the crc calculator (when writing into the register) ● holds the result of the p...

  • Page 64

    Crc calculation unit rm0008 64/1096 doc id 13902 rev 12 4.4.3 control register (crc_cr) address offset: 0x08 reset value: 0x0000 0000 4.4.4 crc register map the following table provides the crc register map and reset values. Bits 7:0 general-purpose 8-bit data register bits can be used as a temporar...

  • Page 65: Power Control (Pwr)

    Rm0008 power control (pwr) doc id 13902 rev 12 65/1096 5 power control (pwr) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcont...

  • Page 66

    Power control (pwr) rm0008 66/1096 doc id 13902 rev 12 figure 4. Power supply overview note: 1 v dda and v ssa must be connected to v dd and v ss , respectively. 5.1.1 independent a/d and d/a converter supply and reference voltage to improve conversion accuracy, the adc and the dac have an independe...

  • Page 67

    Rm0008 power control (pwr) doc id 13902 rev 12 67/1096 5.1.2 battery backup domain to retain the content of the backup registers and supply the rtc function when v dd is turned off, v bat pin can be connected to an optional standby voltage supplied by a battery or by another source. The v bat pin po...

  • Page 68: 5.2

    Power control (pwr) rm0008 68/1096 doc id 13902 rev 12 5.1.3 voltage regulator the voltage regulator is always enabled after reset. It works in three different modes depending on the application modes. ● in run mode, the regulator supplies full power to the 1.8 v domain (core, memories and digital p...

  • Page 69

    Rm0008 power control (pwr) doc id 13902 rev 12 69/1096 pvd output interrupt can be generated when v dd /v dda drops below the pvd threshold and/or when v dd /v dda rises above the pvd threshold depending on exti line16 rising/falling edge configuration. As an example the service routine could perfor...

  • Page 70: 5.3 Low-Power

    Power control (pwr) rm0008 70/1096 doc id 13902 rev 12 5.3 low-power modes by default, the microcontroller is in run mode after a system or a power reset. Several low- power modes are available to save power when the cpu does not need to be kept running, for example when waiting for an external even...

  • Page 71

    Rm0008 power control (pwr) doc id 13902 rev 12 71/1096 5.3.2 peripheral clock gating in run mode, the hclk and pclkx for individual peripherals and memories can be stopped at any time to reduce power consumption. To further reduce power consumption in sleep mode the peripheral clocks can be disabled...

  • Page 72

    Power control (pwr) rm0008 72/1096 doc id 13902 rev 12 5.3.4 stop mode the stop mode is based on the cortex-m3 deepsleep mode combined with peripheral clock gating. The voltage regulator can be configured either in normal or low-power mode. In stop mode, all clocks in the 1.8 v domain are stopped, t...

  • Page 73

    Rm0008 power control (pwr) doc id 13902 rev 12 73/1096 ● real-time clock (rtc): this is configured by the rtcen bit in the backup domain control register (rcc_bdcr) ● internal rc oscillator (lsi rc): this is configured by the lsion bit in the control/status register (rcc_csr) . ● external 32.768 khz...

  • Page 74

    Power control (pwr) rm0008 74/1096 doc id 13902 rev 12 entering standby mode refer to table 15 for more details on how to enter standby mode. In standby mode, the following features can be selected by programming individual control bits: ● independent watchdog (iwdg): the iwdg is started by writing ...

  • Page 75: 5.4

    Rm0008 power control (pwr) doc id 13902 rev 12 75/1096 debug mode by default, the debug connection is lost if the application puts the mcu in stop or standby mode while the debug features are used. This is due to the fact that the cortex™-m3 core is no longer clocked. However, by setting some config...

  • Page 76

    Power control (pwr) rm0008 76/1096 doc id 13902 rev 12 bit 8 dbp: disable backup domain write protection. In reset state, the rtc and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. 0: access to rtc and backup registers d...

  • Page 77

    Rm0008 power control (pwr) doc id 13902 rev 12 77/1096 5.4.2 power control/status register (pwr_csr) address offset: 0x04 reset value: 0x0000 0000 (not reset by wakeup from standby mode) additional apb cycles are needed to read this register versus a standard apb read. 31 30 29 28 27 26 25 24 23 22 ...

  • Page 78

    Power control (pwr) rm0008 78/1096 doc id 13902 rev 12 5.4.3 pwr register map the following table summarizes the pwr registers. Refer to table 3 on page 50 for the register boundary addresses. Table 16. Pwr register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

  • Page 79: Backup Registers (Bkp)

    Rm0008 backup registers (bkp) doc id 13902 rev 12 79/1096 6 backup registers (bkp) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102xx and stm32f103xx mic...

  • Page 80: 6.3

    Backup registers (bkp) rm0008 80/1096 doc id 13902 rev 12 6.3 bkp functional description 6.3.1 tamper detection the tamper pin generates a tamper detection event when the pin changes from 0 to 1 or from 1 to 0 depending on the tpal bit in the backup control register (bkp_cr) . A tamper detection eve...

  • Page 81: 6.4 Bkp

    Rm0008 backup registers (bkp) doc id 13902 rev 12 81/1096 6.4 bkp registers refer to section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 6.4.1 backup data register x (bkp_drx) (x = 1 ..42...

  • Page 82

    Backup registers (bkp) rm0008 82/1096 doc id 13902 rev 12 6.4.3 backup control register (bkp_cr) address offset: 0x30 reset value: 0x0000 0000 note: setting the tpal and tpe bits at the same time is always safe, however resetting both at the same time can generate a spurious tamper event. For this r...

  • Page 83

    Rm0008 backup registers (bkp) doc id 13902 rev 12 83/1096 6.4.5 bkp register map bkp registers are mapped as 16-bit addressable registers as described in the table below: bit 8 tef:tamper event flag this bit is set by hardware when a tamper event is detected. It is cleared by writing 1 to the cte bi...

  • Page 84

    Backup registers (bkp) rm0008 84/1096 doc id 13902 rev 12 0x1c bkp_dr7 reserved d[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x20 bkp_dr8 reserved d[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x24 bkp_dr9 reserved d[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x28 bkp_dr10 reserv...

  • Page 85

    Rm0008 backup registers (bkp) doc id 13902 rev 12 85/1096 0x64 bkp_dr20 reserved d[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x68 bkp_dr21 reserved d[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x6c bkp_dr22 reserved d[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x70 bkp_dr23 res...

  • Page 86

    Backup registers (bkp) rm0008 86/1096 doc id 13902 rev 12 refer to table 3 on page 50 for the register boundary addresses. 0xa8 bkp_dr37 reserved d[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xac bkp_dr38 reserved d[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xb0 bkp_dr39 reserved d[15...

  • Page 87: Control (Rcc)

    Rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) doc id 13902 rev 12 87/1096 7 low-, medium-, high- and xl-density reset and clock control (rcc) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 ...

  • Page 88

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 88/1096 doc id 13902 rev 12 1. Reset generated when entering standby mode: this type of reset is enabled by resetting nrst_stdby bit in user option bytes. In this case, whenever a standby mode entry sequence is successfully exe...

  • Page 89: 7.2 Clocks

    Rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) doc id 13902 rev 12 89/1096 7.2 clocks three different clock sources can be used to drive the system clock (sysclk): ● hsi oscillator clock ● hse oscillator clock ● pll clock the devices have the following two secondary clock s...

  • Page 90

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 90/1096 doc id 13902 rev 12 figure 8. Clock tree 1. When the hsi is used as a pll clock input, the maximum system clock frequency that can be achieved is 64 mhz. 2. For full details about the internal and external clock source ...

  • Page 91

    Rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) doc id 13902 rev 12 91/1096 the timer clock frequencies are automatically fixed by hardware. There are two cases: 1. If the apb prescaler is 1, the timer clock frequencies are set to the same frequency as that of the apb domain...

  • Page 92

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 92/1096 doc id 13902 rev 12 external source (hse bypass) in this mode, an external clock source must be provided. It can have a frequency of up to 25 mhz. You select this mode by setting the hsebyp and hseon bits in the clock c...

  • Page 93

    Rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) doc id 13902 rev 12 93/1096 the pll configuration (selection of hsi oscillator divided by 2 or hse oscillator for pll input clock, and multiplication factor) must be done before enabling the pll. Once the pll enabled, these par...

  • Page 94

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 94/1096 doc id 13902 rev 12 oscillator, the software can adjust the programmable 20-bit prescaler of the rtc to get an accurate time base or can compute accurate iwdg timeout. Use the following procedure to calibrate the lsi: 1...

  • Page 95

    Rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) doc id 13902 rev 12 95/1096 the lse clock is in the backup domain, whereas the hse and lsi clocks are not. Consequently: ● if lse is selected as rtc clock: – the rtc continues to work even if the v dd supply is switched off, pr...

  • Page 96: 7.3 Rcc

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 96/1096 doc id 13902 rev 12 7.3 rcc registers refer to section 2.1 on page 46 for a list of abbreviations used in register descriptions. 7.3.1 clock control register (rcc_cr) address offset: 0x00 reset value: 0x0000 xx83 where ...

  • Page 97

    Rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) doc id 13902 rev 12 97/1096 bit 16 hseon: external high-speed clock enable set and cleared by software. Cleared by hardware to stop the external 1-25mhz oscillator when entering in stop or standby mode. This bit cannot be reset...

  • Page 98

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 98/1096 doc id 13902 rev 12 7.3.2 clock configuration register (rcc_cfgr) address offset: 0x04 reset value: 0x0000 0000 access: 0 ≤ wait state ≤ 2, word, half-word and byte access 1 or 2 wait states inserted only if the access ...

  • Page 99

    Rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) doc id 13902 rev 12 99/1096 bits 21:18 pllmul: pll multiplication factor these bits are written by software to define the pll multiplication factor. These bits can be written only when pll is disabled. Caution: the pll output f...

  • Page 100

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 100/1096 doc id 13902 rev 12 bits 10:8 ppre1: apb low-speed prescaler (apb1) set and cleared by software to control the division factor of the apb low-speed clock (pclk1). Warning: the software has to set correctly these bits t...

  • Page 101

    Rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) doc id 13902 rev 12 101/1096 7.3.3 clock interrupt register (rcc_cir) address offset: 0x08 reset value: 0x0000 0000 access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved...

  • Page 102

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 102/1096 doc id 13902 rev 12 bit 12 pllrdyie: pll ready interrupt enable set and cleared by software to enable/disable interrupt caused by pll lock. 0: pll lock interrupt disabled 1: pll lock interrupt enabled bit 11 hserdyie: ...

  • Page 103

    Rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) doc id 13902 rev 12 103/1096 7.3.4 apb2 peripheral reset register (rcc_apb2rstr) address offset: 0x0c reset value: 0x00000 0000 access: no wait state, word, half-word and byte access bit 1 lserdyf: lse ready interrupt flag set ...

  • Page 104

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 104/1096 doc id 13902 rev 12 bit 14 usart1rst: usart1 reset set and cleared by software. 0: no effect 1: reset usart1 adc1rst: adc1 interface reset set and cleared by software. 0: no effect 1: reset adc1 interface bit 13 tim8rs...

  • Page 105

    Rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) doc id 13902 rev 12 105/1096 bit 4 iopcrst: io port c reset set and cleared by software. 0: no effect 1: reset io port c bit 3 iopbrst: io port b reset set and cleared by software. 0: no effect 1: reset io port b bit 2 ioparst:...

  • Page 106

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 106/1096 doc id 13902 rev 12 7.3.5 apb1 peripheral reset register (rcc_apb1rstr) address offset: 0x10 reset value: 0x0000 0000 access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ...

  • Page 107

    Rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) doc id 13902 rev 12 107/1096 bit 21 i2c1rst: i2c1 reset set and cleared by software. 0: no effect 1: reset i2c1 bit 20 uart5rst: usart5 reset set and cleared by software. 0: no effect 1: reset usart5 bit 19 uart4rst: usart4 res...

  • Page 108

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 108/1096 doc id 13902 rev 12 7.3.6 ahb peripheral clock enable register (rcc_ahbenr) address offset: 0x14 reset value: 0x0000 0014 access: no wait state, word, half-word and byte access note: when the peripheral clock is not ac...

  • Page 109

    Rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) doc id 13902 rev 12 109/1096 7.3.7 apb2 peripheral clock enable register (rcc_apb2enr) address: 0x18 reset value: 0x0000 0000 access: word, half-word and byte access no wait states, except if the access occurs while an access t...

  • Page 110

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 110/1096 doc id 13902 rev 12 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved tim11 en tim10 en tim9 en reserved rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 adc3 en usar t1en tim8 en spi1 en tim1 en adc2 en adc1 en i...

  • Page 111

    Rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) doc id 13902 rev 12 111/1096 7.3.8 apb1 peripheral clock enable register (rcc_apb1enr) address: 0x1c reset value: 0x0000 0000 bit 10 adc2en: adc 2 interface clock enable set and cleared by software. 0: adc 2 interface clock dis...

  • Page 112

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 112/1096 doc id 13902 rev 12 access: word, half-word and byte access no wait state, except if the access occurs while an access to a peripheral on apb1 domain is on going. In this case, wait states are inserted until this acces...

  • Page 113

    Rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) doc id 13902 rev 12 113/1096 bit 21 i2c1en: i2c1 clock enable set and cleared by software. 0: i2c1 clock disabled 1: i2c1 clock enabled bit 20 uart5en: usart5 clock enable set and cleared by software. 0: usart5 clock disabled 1...

  • Page 114

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 114/1096 doc id 13902 rev 12 bit 6 tim12en: tim12 timer clock enable set and cleared by software. 0: tim12 clock disabled 1: tim12 clock enabled bit 5 tim7en: tim7 timer clock enable set and cleared by software. 0: tim7 clock d...

  • Page 115

    Rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) doc id 13902 rev 12 115/1096 7.3.9 backup domain control register (rcc_bdcr) address offset: 0x20 reset value: 0x0000 0000, reset by backup domain reset. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access wait states a...

  • Page 116

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 116/1096 doc id 13902 rev 12 bit 1 lserdy: external low-speed oscillator ready set and cleared by hardware to indicate when the external 32 khz oscillator is stable. After the lseon bit is cleared, lserdy goes low after 6 exter...

  • Page 117

    Rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) doc id 13902 rev 12 117/1096 7.3.10 control/status register (rcc_csr) address: 0x24 reset value: 0x0c00 0000, reset by system reset, except reset flags by power reset only. Access: 0 ≤ wait state ≤ 3, word, half-word and byte a...

  • Page 118

    Low-, medium-, high- and xl-density reset and clock control (rcc) rm0008 118/1096 doc id 13902 rev 12 bit 26 pinrstf: pin reset flag set by hardware when a reset from the nrst pin occurs. Cleared by writing to the rmvf bit. 0: no reset from nrst pin occurred 1: reset from nrst pin occurred bit 25 re...

  • Page 119

    Rm0008 low-, medium-, high- and xl-density reset and clock control (rcc) doc id 13902 rev 12 119/1096 7.3.11 rcc register map the following table gives the rcc register map and the reset values. Refer to table 3 on page 50 for the register boundary addresses. Table 18. Rcc register map and reset val...

  • Page 120: (Rcc)

    Connectivity line devices: reset and clock control (rcc) rm0008 120/1096 doc id 13902 rev 12 8 connectivity line devices: reset and clock control (rcc) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Me...

  • Page 121

    Rm0008 connectivity line devices: reset and clock control (rcc) doc id 13902 rev 12 121/1096 low-power management reset there are two ways to generate a low-power management reset: 1. Reset generated when entering standby mode: this type of reset is enabled by resetting nrst_stdby bit in user option...

  • Page 122: 8.2 Clocks

    Connectivity line devices: reset and clock control (rcc) rm0008 122/1096 doc id 13902 rev 12 8.1.3 backup domain reset the backup domain has two specific resets that affect only the backup domain (see figure 4 ). A backup domain reset is generated when one of the following events occurs: 1. Software...

  • Page 123

    Rm0008 connectivity line devices: reset and clock control (rcc) doc id 13902 rev 12 123/1096 figure 11. Clock tree 1. When the hsi is used as a pll clock input, the maximum system clock frequency that can be achieved is 36 mhz. 2. For full details about the internal and external clock source charact...

  • Page 124

    Connectivity line devices: reset and clock control (rcc) rm0008 124/1096 doc id 13902 rev 12 several prescalers allow the configuration of the ahb frequency, the high speed apb (apb2) and the low speed apb (apb1) domains. The maximum frequency of the ahb and the apb2 domains is 72 mhz. The maximum a...

  • Page 125

    Rm0008 connectivity line devices: reset and clock control (rcc) doc id 13902 rev 12 125/1096 external source (hse bypass) in this mode, an external clock source must be provided. It can have a frequency of up to 50 mhz. You select this mode by setting the hsebyp and hseon bits in the clock control r...

  • Page 126

    Connectivity line devices: reset and clock control (rcc) rm0008 126/1096 doc id 13902 rev 12 calibration rc oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by st for 1% accuracy at t a = 25 °c. After rese...

  • Page 127

    Rm0008 connectivity line devices: reset and clock control (rcc) doc id 13902 rev 12 127/1096 external source (lse bypass) in this mode, an external clock source must be provided. It can have a frequency of up to 1 mhz. You select this mode by setting the lsebyp and lseon bits in the backup domain co...

  • Page 128

    Connectivity line devices: reset and clock control (rcc) rm0008 128/1096 doc id 13902 rev 12 8.2.7 clock security system (css) clock security system can be activated by software. In this case, the clock detector is enabled after the hse oscillator startup delay, and disabled when this oscillator is ...

  • Page 129: 8.3 Rcc

    Rm0008 connectivity line devices: reset and clock control (rcc) doc id 13902 rev 12 129/1096 8.2.10 clock-out capability the microcontroller clock output (mco) capability allows the clock to be output onto the external mco pin. The configuration registers of the corresponding gpio port must be progr...

  • Page 130

    Connectivity line devices: reset and clock control (rcc) rm0008 130/1096 doc id 13902 rev 12 bit 27 pll2rdy: pll2 clock ready flag set by hardware to indicate that the pll2 is locked. 0: pll2 unlocked 1: pll2 locked bit 26 pll2on: pll2 enable set and cleared by software to enable pll2. Cleared by ha...

  • Page 131

    Rm0008 connectivity line devices: reset and clock control (rcc) doc id 13902 rev 12 131/1096 8.3.2 clock configuration register (rcc_cfgr) address offset: 0x04 reset value: 0x0000 0000 access: 0 ≤ wait state ≤ 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs d...

  • Page 132

    Connectivity line devices: reset and clock control (rcc) rm0008 132/1096 doc id 13902 rev 12 bits 26:24 mco[3:0]: microcontroller clock output set and cleared by software. 00xx: no clock 0100: system clock (sysclk) selected 0101: hsi clock selected 0110: hse clock selected 0111: pll clock divided by...

  • Page 133

    Rm0008 connectivity line devices: reset and clock control (rcc) doc id 13902 rev 12 133/1096 bits 14:14 adcpre[1:0]: adc prescaler set and cleared by software to select the frequency of the clock to the adcs. 00: pclk2 divided by 2 01: pclk2 divided by 4 10: pclk2 divided by 6 11: pclk2 divided by 8...

  • Page 134

    Connectivity line devices: reset and clock control (rcc) rm0008 134/1096 doc id 13902 rev 12 8.3.3 clock interrupt register (rcc_cir) address offset: 0x08 reset value: 0x0000 0000 access: no wait state, word, half-word and byte access bits 1:0 sw[1:0]: system clock switch set and cleared by software...

  • Page 135

    Rm0008 connectivity line devices: reset and clock control (rcc) doc id 13902 rev 12 135/1096 bit 18 hsirdyc: hsi ready interrupt clear this bit is set by software to clear the hsirdyf flag. 0: no effect 1: clear hsirdyf flag bit 17 lserdyc: lse ready interrupt clear this bit is set by software to cl...

  • Page 136

    Connectivity line devices: reset and clock control (rcc) rm0008 136/1096 doc id 13902 rev 12 bit 7 cssf: clock security system interrupt flag set by hardware when a failure is detected in the external 3-25 mhz oscillator. It is cleared by software setting the cssc bit. 0: no clock security interrupt...

  • Page 137

    Rm0008 connectivity line devices: reset and clock control (rcc) doc id 13902 rev 12 137/1096 8.3.4 apb2 peripheral reset register (rcc_apb2rstr) address offset: 0x0c reset value: 0x00000 0000 access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reser...

  • Page 138

    Connectivity line devices: reset and clock control (rcc) rm0008 138/1096 doc id 13902 rev 12 8.3.5 apb1 peripheral reset register (rcc_apb1rstr) address offset: 0x10 reset value: 0x0000 0000 access: no wait state, word, half-word and byte access bit 4 iopcrst: io port c reset set and cleared by soft...

  • Page 139

    Rm0008 connectivity line devices: reset and clock control (rcc) doc id 13902 rev 12 139/1096 bit 27 bkprst: backup interface reset set and cleared by software. 0: no effect 1: reset backup interface bit 26 can2rst: can2 reset set and cleared by software. 0: no effect 1: reset can2 bit 25 can1rst: ca...

  • Page 140

    Connectivity line devices: reset and clock control (rcc) rm0008 140/1096 doc id 13902 rev 12 bits 13:12 reserved, always read as 0. Bit 11 wwdgrst: window watchdog reset set and cleared by software. 0: no effect 1: reset window watchdog bits 10:6 reserved, always read as 0. Bit 5 tim7rst: timer 7 re...

  • Page 141

    Rm0008 connectivity line devices: reset and clock control (rcc) doc id 13902 rev 12 141/1096 8.3.6 ahb peripheral clock enable register (rcc_ahbenr) address offset: 0x14 reset value: 0x0000 0014 access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 re...

  • Page 142

    Connectivity line devices: reset and clock control (rcc) rm0008 142/1096 doc id 13902 rev 12 8.3.7 apb2 peripheral clock enable register (rcc_apb2enr) address: 0x18 reset value: 0x0000 0000 access: word, half-word and byte access no wait states, except if the access occurs while an access to a perip...

  • Page 143

    Rm0008 connectivity line devices: reset and clock control (rcc) doc id 13902 rev 12 143/1096 bit 11 tim1en: tim1 timer clock enable set and cleared by software. 0: tim1 timer clock disabled 1: tim1 timer clock enabled bit 10 adc2en: adc 2 interface clock enable set and cleared by software. 0: adc 2 ...

  • Page 144

    Connectivity line devices: reset and clock control (rcc) rm0008 144/1096 doc id 13902 rev 12 8.3.8 apb1 peripheral clock enable register (rcc_apb1enr) address: 0x1c reset value: 0x0000 0000 access: word, half-word and byte access no wait state, except if the access occurs while an access to a periph...

  • Page 145

    Rm0008 connectivity line devices: reset and clock control (rcc) doc id 13902 rev 12 145/1096 bit 21 i2c1en: i2c 1 clock enable set and cleared by software. 0: i2c 1 clock disabled 1: i2c 1 clock enabled bit 20 uart5en: usart 5 clock enable set and cleared by software. 0: usart 5 clock disabled 1: us...

  • Page 146

    Connectivity line devices: reset and clock control (rcc) rm0008 146/1096 doc id 13902 rev 12 8.3.9 backup domain control register (rcc_bdcr) address: 0x20 reset value: 0x0000 0000, reset by backup domain reset. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access wait states are inserted in t...

  • Page 147

    Rm0008 connectivity line devices: reset and clock control (rcc) doc id 13902 rev 12 147/1096 bit 15 rtcen: rtc clock enable set and cleared by software. 0: rtc clock disabled 1: rtc clock enabled bits 14:10 reserved, always read as 0. Bits 9:8 rtcsel[1:0]: rtc clock source selection set by software ...

  • Page 148

    Connectivity line devices: reset and clock control (rcc) rm0008 148/1096 doc id 13902 rev 12 8.3.10 control/status register (rcc_csr) address: 0x24 reset value: 0x0c00 0000, reset by system reset, except reset flags by power reset only. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access wai...

  • Page 149

    Rm0008 connectivity line devices: reset and clock control (rcc) doc id 13902 rev 12 149/1096 8.3.11 ahb peripheral clock reset register (rcc_ahbrstr) address offset: 0x28 reset value: 0x0000 0000 access: no wait state, word, half-word and byte access bit 24 rmvf: remove reset flag set by software to...

  • Page 150

    Connectivity line devices: reset and clock control (rcc) rm0008 150/1096 doc id 13902 rev 12 8.3.12 clock configuration register2 (rcc_cfgr2) address offset: 0x2c reset value: 0x0000 0000 access: no wait state, word, half-word and byte access 7 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserve...

  • Page 151

    Rm0008 connectivity line devices: reset and clock control (rcc) doc id 13902 rev 12 151/1096 bits 11:8 pll2mul[3:0]: pll2 multiplication factor set and cleared by software to control pll2 multiplication factor. These bits can be written only when pll2 is disabled. 00xx: reserved 010x: reserved 0110:...

  • Page 152

    Connectivity line devices: reset and clock control (rcc) rm0008 152/1096 doc id 13902 rev 12 8.3.13 rcc register map the following table gives the rcc register map and the reset values. Bits 3:0 prediv1[3:0]: prediv1 division factor set and cleared by software to select prediv1 division factor. Thes...

  • Page 153

    Rm0008 connectivity line devices: reset and clock control (rcc) doc id 13902 rev 12 153/1096 refer to table 3 on page 50 for the register boundary addresses. 0x014 rcc_ahbenr reserved ethma crxen ethma c txe n ethma c en re se rv e d ot g f s e n reserved crcen re se rv e d flitfen re se rv e d sr a...

  • Page 154: And Afios)

    General-purpose and alternate-function i/os (gpios and afios) rm0008 154/1096 doc id 13902 rev 12 9 general-purpose and alternate-function i/os (gpios and afios) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 ...

  • Page 155

    Rm0008 general-purpose and alternate-function i/os (gpios and afios) doc id 13902 rev 12 155/1096 figure 13. Basic structure of a standard i/o port bit figure 14. Basic structure of a five-volt tolerant i/o port bit 1. V dd_ft is a potential specific to five-volt tolerant i/os and different from v d...

  • Page 156

    General-purpose and alternate-function i/os (gpios and afios) rm0008 156/1096 doc id 13902 rev 12 9.1.1 general-purpose i/o (gpio) during and just after reset, the alternate functions are not active and the i/o ports are configured in input floating mode (cnfx[1:0]=01b, modex[1:0]=00b). The jtag pin...

  • Page 157

    Rm0008 general-purpose and alternate-function i/os (gpios and afios) doc id 13902 rev 12 157/1096 or for reset only gpiox_brr) to select the bits you want to modify. The unselected bits will not be modified. 9.1.3 external interrupt/wakeup lines all ports have external interrupt capability. To use e...

  • Page 158

    General-purpose and alternate-function i/os (gpios and afios) rm0008 158/1096 doc id 13902 rev 12 9.1.7 input configuration when the i/o port is programmed as input: ● the output buffer is disabled ● the schmitt trigger input is activated ● the weak pull-up and pull-down resistors are activated or n...

  • Page 159

    Rm0008 general-purpose and alternate-function i/os (gpios and afios) doc id 13902 rev 12 159/1096 the figure 16 on page 159 shows the output configuration of the i/o port bit. Figure 16. Output configuration 1. V dd_ft is a potential specific to five-volt tolerant i/os and different from v dd . 9.1....

  • Page 160

    General-purpose and alternate-function i/os (gpios and afios) rm0008 160/1096 doc id 13902 rev 12 figure 17. Alternate function configuration 1. V dd_ft is a potential specific to five-volt tolerant i/os and different from v dd . 9.1.10 analog configuration when the i/o port is programmed as analog ...

  • Page 161

    Rm0008 general-purpose and alternate-function i/os (gpios and afios) doc id 13902 rev 12 161/1096 figure 18. High impedance-analog configuration 9.1.11 gpio configurations for device peripherals table 22 to table 33 give the gpio configurations of the device peripherals. From on-chip peripheral to o...

  • Page 162

    General-purpose and alternate-function i/os (gpios and afios) rm0008 162/1096 doc id 13902 rev 12 usartx_rx full duplex input floating / input pull-up half duplex synchronous mode not used. Can be used as a general io usartx_ck synchronous mode alternate function push-pull usartx_rts hardware flow c...

  • Page 163

    Rm0008 general-purpose and alternate-function i/os (gpios and afios) doc id 13902 rev 12 163/1096 table 27. I2c i2c pinout configuration gpio configuration i2cx_scl i2c clock alternate function open drain i2cx_sda i2c data i/o alternate function open drain table 28. Bxcan bxcan pinout gpio configura...

  • Page 164

    General-purpose and alternate-function i/os (gpios and afios) rm0008 164/1096 doc id 13902 rev 12 the gpio configuration of the adc inputs should be analog. Table 31. Sdio sdio pinout gpio configuration sdio_ck alternate function push-pull sdio_cmd alternate function push-pull sdio[d7:d0] alternate ...

  • Page 165: 9.2 Gpio

    Rm0008 general-purpose and alternate-function i/os (gpios and afios) doc id 13902 rev 12 165/1096 9.2 gpio registers refer to section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 9.2.1 port configuration reg...

  • Page 166

    General-purpose and alternate-function i/os (gpios and afios) rm0008 166/1096 doc id 13902 rev 12 9.2.2 port configuration register high (gpiox_crh) (x=a..G) address offset: 0x04 reset value: 0x4444 4444 9.2.3 port input data register (gpiox_idr) (x=a..G) address offset: 0x08h reset value: 0x0000 xx...

  • Page 167

    Rm0008 general-purpose and alternate-function i/os (gpios and afios) doc id 13902 rev 12 167/1096 9.2.4 port output data register (gpiox_odr) (x=a..G) address offset: 0x0c reset value: 0x0000 0000 9.2.5 port bit set/reset register (gpiox_bsrr) (x=a..G) address offset: 0x10 reset value: 0x0000 0000 3...

  • Page 168

    General-purpose and alternate-function i/os (gpios and afios) rm0008 168/1096 doc id 13902 rev 12 9.2.6 port bit reset register (gpiox_brr) (x=a..G) address offset: 0x14 reset value: 0x0000 0000 9.2.7 port configuration lock register (gpiox_lckr) (x=a..G) this register is used to lock the configurat...

  • Page 169: 9.3

    Rm0008 general-purpose and alternate-function i/os (gpios and afios) doc id 13902 rev 12 169/1096 9.3 alternate function i/o and debug configuration (afio) to optimize the number of peripherals available for the 64-pin or the 100-pin or the 144-pin package, it is possible to remap some alternate fun...

  • Page 170

    General-purpose and alternate-function i/os (gpios and afios) rm0008 170/1096 doc id 13902 rev 12 9.3.3 can1 alternate function remapping the can signals can be mapped on port a, port b or port d as shown in table 34 . For port d, remapping is not possible in devices delivered in 36-, 48- and 64-pin...

  • Page 171

    Rm0008 general-purpose and alternate-function i/os (gpios and afios) doc id 13902 rev 12 171/1096 to optimize the number of free gpios during debugging, this mapping can be configured in different ways by programming the swj_cfg[1:0] bits in the af remap and debug i/o configuration register (afio_ma...

  • Page 172

    General-purpose and alternate-function i/os (gpios and afios) rm0008 172/1096 doc id 13902 rev 12 9.3.7 timer alternate function remapping timer 4 channels 1 to 4 can be remapped from port b to port d. Other timer remapping possibilities are listed in table 44 to table 46 . Refer to af remap and deb...

  • Page 173

    Rm0008 general-purpose and alternate-function i/os (gpios and afios) doc id 13902 rev 12 173/1096 table 45. Tim2 alternate function remapping alternate function tim2_remap[1: 0] = “00” (no remap) tim2_remap[1: 0] = “01” (partial remap) tim2_remap[1: 0] = “10” (partial remap) (1) 1. Remap not availab...

  • Page 174

    General-purpose and alternate-function i/os (gpios and afios) rm0008 174/1096 doc id 13902 rev 12 9.3.8 usart alternate function remapping refer to af remap and debug i/o configuration register (afio_mapr) . Table 49. Tim11 remapping (1) 1. Refer to the af remap and debug i/o configuration register ...

  • Page 175

    Rm0008 general-purpose and alternate-function i/os (gpios and afios) doc id 13902 rev 12 175/1096 9.3.9 i2c1 alternate function remapping refer to af remap and debug i/o configuration register (afio_mapr) 9.3.10 spi1 alternate function remapping refer to af remap and debug i/o configuration register...

  • Page 176: 9.4 Afio

    General-purpose and alternate-function i/os (gpios and afios) rm0008 176/1096 doc id 13902 rev 12 9.4 afio registers refer to section 2.1 on page 46 for a list of abbreviations used in register descriptions. Note: to read/write the afio_evcr, afio_mapr and afio_exticrx registers, the afio clock shou...

  • Page 177

    Rm0008 general-purpose and alternate-function i/os (gpios and afios) doc id 13902 rev 12 177/1096 9.4.1 event control register (afio_evcr) address offset: 0x00 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved evoe port[2...

  • Page 178

    General-purpose and alternate-function i/os (gpios and afios) rm0008 178/1096 doc id 13902 rev 12 9.4.2 af remap and debug i/o configuration register (afio_mapr) address offset: 0x04 reset value: 0x0000 0000 memory map and bit definitions for low-, medium- high- and xl-density devices: 31 30 29 28 2...

  • Page 179

    Rm0008 general-purpose and alternate-function i/os (gpios and afios) doc id 13902 rev 12 179/1096 bits 17 adc1_etrginj_remap:adc 1 external trigger injected conversion remapping set and cleared by software. This bit controls the trigger input connected to adc1 external trigger injected conversion. W...

  • Page 180

    General-purpose and alternate-function i/os (gpios and afios) rm0008 180/1096 doc id 13902 rev 12 bits 7:6 tim1_remap[1:0]: tim1 remapping these bits are set and cleared by software. They control the mapping of tim1 channels 1 to 4, 1n to 3n, external trigger (etr) and break input (bkin) on the gpio...

  • Page 181

    Rm0008 general-purpose and alternate-function i/os (gpios and afios) doc id 13902 rev 12 181/1096 memory map and bit definitions for connectivity line devices: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res. Ptp_p ps_re map tim2itr 1_ iremap spi3_ remap res. Swj_ cfg[2:0] mii_rmi i_sel can2_ re...

  • Page 182

    General-purpose and alternate-function i/os (gpios and afios) rm0008 182/1096 doc id 13902 rev 12 bit 22 can2_remap: can2 i/o remapping this bit is set and cleared by software. It controls the can2_tx and can2_rx pins. 0: no remap (can2_rx/pb12, can2_tx/pb13) 1: remap (can2_rx/pb5, can2_tx/pb6) note...

  • Page 183

    Rm0008 general-purpose and alternate-function i/os (gpios and afios) doc id 13902 rev 12 183/1096 bits 9:8 tim2_remap[1:0]: tim2 remapping these bits are set and cleared by software. They control the mapping of tim2 channels 1 to 4 and external trigger (etr) on the gpio ports. 00: no remap (ch1/etr/...

  • Page 184

    General-purpose and alternate-function i/os (gpios and afios) rm0008 184/1096 doc id 13902 rev 12 9.4.3 external interrupt configuration register 1 (afio_exticr1) address offset: 0x08 reset value: 0x0000 9.4.4 external interrupt configuration register 2 (afio_exticr2) address offset: 0x0c reset valu...

  • Page 185

    Rm0008 general-purpose and alternate-function i/os (gpios and afios) doc id 13902 rev 12 185/1096 9.4.5 external interrupt configuration register 3 (afio_exticr3) address offset: 0x10 reset value: 0x0000 9.4.6 external interrupt configuration register 4 (afio_exticr4) address offset: 0x14 reset valu...

  • Page 186

    General-purpose and alternate-function i/os (gpios and afios) rm0008 186/1096 doc id 13902 rev 12 9.4.7 af remap and debug i/o configuration register2 (afio_mapr2) address offset: 0x1c reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

  • Page 187: 9.5

    Rm0008 general-purpose and alternate-function i/os (gpios and afios) doc id 13902 rev 12 187/1096 9.5 gpio and afio register maps refer to table 3 on page 50 for the register boundary addresses. The following tables give the gpio and afio register map and the reset values. Table 59. Gpio register ma...

  • Page 188

    General-purpose and alternate-function i/os (gpios and afios) rm0008 188/1096 doc id 13902 rev 12 refer to table 3 on page 50 for the register boundary addresses. 0x10 afio_exticr3 reserved exti11[3:0] exti10[3:0] exti9[3:0] exti8[3:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x14 afio_exticr4 re...

  • Page 189: Interrupts and Events

    Rm0008 interrupts and events doc id 13902 rev 12 189/1096 10 interrupts and events low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102xx and stm32f103xx mic...

  • Page 190

    Interrupts and events rm0008 190/1096 doc id 13902 rev 12 -2 fixed nmi non maskable interrupt. The rcc clock security system (css) is linked to the nmi vector. 0x0000_0008 -1 fixed hardfault all class of fault 0x0000_000c 0 settable memmanage memory management 0x0000_0010 1 settable busfault pre-fet...

  • Page 191

    Rm0008 interrupts and events doc id 13902 rev 12 191/1096 19 26 settable can1_tx can1 tx interrupts 0x0000_008c 20 27 settable can1_rx0 can1 rx0 interrupts 0x0000_0090 21 28 settable can1_rx1 can1 rx1 interrupt 0x0000_0094 22 29 settable can1_sce can1 sce interrupt 0x0000_0098 23 30 settable exti9_5...

  • Page 192

    Interrupts and events rm0008 192/1096 doc id 13902 rev 12 56 63 settable dma2_channel1 dma2 channel1 global interrupt 0x0000_0120 57 64 settable dma2_channel2 dma2 channel2 global interrupt 0x0000_0124 58 65 settable dma2_channel3 dma2 channel3 global interrupt 0x0000_0128 59 66 settable dma2_channe...

  • Page 193

    Rm0008 interrupts and events doc id 13902 rev 12 193/1096 1 8 settable pvd pvd through exti line detection interrupt 0x0000_0044 2 9 settable tamper tamper interrupt 0x0000_0048 3 10 settable rtc rtc global interrupt 0x0000_004c 4 11 settable flash flash global interrupt 0x0000_0050 5 12 settable rc...

  • Page 194

    Interrupts and events rm0008 194/1096 doc id 13902 rev 12 31 38 settable i2c1_ev i2c1 event interrupt 0x0000_00bc 32 39 settable i2c1_er i2c1 error interrupt 0x0000_00c0 33 40 settable i2c2_ev i2c2 event interrupt 0x0000_00c4 34 41 settable i2c2_er i2c2 error interrupt 0x0000_00c8 35 42 settable spi...

  • Page 195

    Rm0008 interrupts and events doc id 13902 rev 12 195/1096 table 63. Vector table for other stm32f10xxx devices po s it io n priority type of priority acronym description address - - - reserved 0x0000_0000 -3 fixed reset reset 0x0000_0004 -2 fixed nmi non maskable interrupt. The rcc clock security sy...

  • Page 196

    Interrupts and events rm0008 196/1096 doc id 13902 rev 12 17 24 settable dma1_channel7 dma1 channel7 global interrupt 0x0000_0084 18 25 settable adc1_2 adc1 and adc2 global interrupt 0x0000_0088 19 26 settable usb_hp_can_ tx usb high priority or can tx interrupts 0x0000_008c 20 27 settable usb_lp_ca...

  • Page 197: 10.2 External

    Rm0008 interrupts and events doc id 13902 rev 12 197/1096 10.2 external interrupt/event controller (exti) the external interrupt/event controller consists of up to 20 edge detectors in connectivity line devices, or 19 edge detectors in other devices for generating event/interrupt requests. Each inpu...

  • Page 198

    Interrupts and events rm0008 198/1096 doc id 13902 rev 12 figure 20. External interrupt/event controller block diagram 10.2.3 wakeup event management the stm32f10xxx is able to handle external or internal events in order to wake up the core (wfe). The wakeup event can be generated either by: ● enabl...

  • Page 199

    Rm0008 interrupts and events doc id 13902 rev 12 199/1096 event request by writing a ‘1’ to the corresponding bit in the event mask register. When the selected edge occurs on the event line, an event pulse is generated. The pending bit corresponding to the event line is not set an interrupt/event re...

  • Page 200

    Interrupts and events rm0008 200/1096 doc id 13902 rev 12 figure 21. External interrupt/event gpio mapping 1. To configure the afio_exticrx for the mapping of external interrupt/event lines onto gpios, the afio clock should first be enabled. Refer to section 7.3.7: apb2 peripheral clock enable regis...

  • Page 201: 10.3

    Rm0008 interrupts and events doc id 13902 rev 12 201/1096 10.3 exti registers refer to section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 10.3.1 interrupt mask register (exti_imr) address offset: 0x00 rese...

  • Page 202

    Interrupts and events rm0008 202/1096 doc id 13902 rev 12 10.3.3 rising trigger selection register (exti_rtsr) address offset: 0x08 reset value: 0x0000 0000 note: the external wakeup lines are edge triggered, no glitches must be generated on these lines. If a rising edge on external interrupt line o...

  • Page 203

    Rm0008 interrupts and events doc id 13902 rev 12 203/1096 10.3.5 software interrupt event register (exti_swier) address offset: 0x10 reset value: 0x0000 0000 10.3.6 pending register (exti_pr) address offset: 0x14 reset value: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved swier 1...

  • Page 204

    Interrupts and events rm0008 204/1096 doc id 13902 rev 12 10.3.7 exti register map the following table gives the exti register map and the reset values. Bits 19 in all registers, are used in connectivity line devices and is reserved otherwise. Refer to table 3 on page 50 for the register boundary ad...

  • Page 205: 11 Analog-to-Digital

    Rm0008 analog-to-digital converter (adc) doc id 13902 rev 12 205/1096 11 analog-to-digital converter (adc) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f1...

  • Page 206: 11.2

    Analog-to-digital converter (adc) rm0008 206/1096 doc id 13902 rev 12 11.2 adc main features ● 12-bit resolution ● interrupt generation at end of conversion, end of injected conversion and analog watchdog event ● single and continuous conversion modes ● scan mode for automatic conversion of channel ...

  • Page 207

    Rm0008 analog-to-digital converter (adc) doc id 13902 rev 12 207/1096 figure 22. Single adc block diagram 1. Adc3 has regular and injected conversion triggers different from those of adc1 and adc2. 2. Tim8_ch4 and tim8_trgo with their corresponding remap bits exist only in high-density and xl-densit...

  • Page 208

    Analog-to-digital converter (adc) rm0008 208/1096 doc id 13902 rev 12 table 65. Adc pins name signal type remarks v ref+ input, analog reference positive the higher/positive reference voltage for the adc, 2.4 v ≤ v ref+ ≤ v dda v dda (1) 1. V dda and v ssa have to be connected to v dd and v ss , res...

  • Page 209

    Rm0008 analog-to-digital converter (adc) doc id 13902 rev 12 209/1096 11.3.1 adc on-off control the adc can be powered-on by setting the adon bit in the adc_cr2 register. When the adon bit is set for the first time, it wakes up the adc from power down mode. Conversion starts when adon bit is set for...

  • Page 210

    Analog-to-digital converter (adc) rm0008 210/1096 doc id 13902 rev 12 once the conversion of the selected channel is complete: ● if a regular channel was converted: – the converted data is stored in the 16-bit adc_dr register – the eoc (end of conversion) flag is set – and an interrupt is generated ...

  • Page 211

    Rm0008 analog-to-digital converter (adc) doc id 13902 rev 12 211/1096 11.3.7 analog watchdog the awd analog watchdog status bit is set if the analog voltage converted by the adc is below a low threshold or above a high threshold. These thresholds are programmed in the 12 least significant bits of th...

  • Page 212

    Analog-to-digital converter (adc) rm0008 212/1096 doc id 13902 rev 12 11.3.9 injected channel management triggered injection to use triggered injection, the jauto bit must be cleared and scan bit must be set in the adc_cr1 register. 1. Start conversion of a group of regular channels either by extern...

  • Page 213: 11.4 Calibration

    Rm0008 analog-to-digital converter (adc) doc id 13902 rev 12 213/1096 11.3.10 discontinuous mode regular group this mode is enabled by setting the discen bit in the adc_cr1 register. It can be used to convert a short sequence of n conversions (n conversions selected in the adc_sqrx registers. The va...

  • Page 214: 11.5 Data

    Analog-to-digital converter (adc) rm0008 214/1096 doc id 13902 rev 12 calibration is started by setting the cal bit in the adc_cr2 register. Once calibration is over, the cal bit is reset by hardware and normal conversion can be performed. It is recommended to calibrate the adc once at power-on. The...

  • Page 215: 11.6

    Rm0008 analog-to-digital converter (adc) doc id 13902 rev 12 215/1096 11.6 channel-by-channel programmable sample time adc samples the input voltage for a number of adc_clk cycles which can be modified us- ing the smp[2:0] bits in the adc_smpr1 and adc_smpr2 registers. Each channel can be sampled wi...

  • Page 216

    Analog-to-digital converter (adc) rm0008 216/1096 doc id 13902 rev 12 table 68. External trigger for injected channels for adc1 and adc2 source connection type jextsel[2:0] tim1_trgo event internal signal from on-chip timers 000 tim1_cc4 event 001 tim2_trgo event 010 tim2_cc1 event 011 tim3_cc4 even...

  • Page 217: 11.8 Dma

    Rm0008 analog-to-digital converter (adc) doc id 13902 rev 12 217/1096 the software source trigger events can be generated by setting a bit in a register (swstart and jswstart in adc_cr2). A regular group conversion can be interrupted by an injected trigger. 11.8 dma request since converted regular c...

  • Page 218: 11.9

    Analog-to-digital converter (adc) rm0008 218/1096 doc id 13902 rev 12 11.9 dual adc mode in devices with two adcs or more, dual adc mode can be used (see figure 29 ). In dual adc mode the start of conversion is triggered alternately or simultaneously by the adc1 master to the adc2 slave, depending o...

  • Page 219

    Rm0008 analog-to-digital converter (adc) doc id 13902 rev 12 219/1096 figure 29. Dual adc block diagram (1) 1. External triggers are present on adc2 but are not shown for the purposes of this diagram. 2. In some dual adc modes, the adc1 data register (adc1_dr) contains both adc1 and adc2 regular con...

  • Page 220

    Analog-to-digital converter (adc) rm0008 220/1096 doc id 13902 rev 12 11.9.1 injected simultaneous mode this mode converts an injected channel group. The source of external trigger comes from the injected group mux of adc1 (selected by the jextsel[2:0] bits in the adc1_cr2 register). A simultaneous ...

  • Page 221

    Rm0008 analog-to-digital converter (adc) doc id 13902 rev 12 221/1096 figure 31. Regular simultaneous mode on 16 channels 11.9.3 fast interleaved mode this mode can be started only on a regular channel group (usually one channel). The source of external trigger comes from the regular channel mux of ...

  • Page 222

    Analog-to-digital converter (adc) rm0008 222/1096 doc id 13902 rev 12 after an eoc interrupt is generated by adc1 (if enabled through the eocie bit) a 32-bit dma transfer request is generated (if the dma bit is set) which transfers to sram the adc1_dr 32-bit register containing the adc2 converted da...

  • Page 223

    Rm0008 analog-to-digital converter (adc) doc id 13902 rev 12 223/1096 if the injected discontinuous mode is enabled for both adc1 and adc2: ● when the 1st trigger occurs, the first injected channel in adc1 is converted. ● when the 2nd trigger arrives, the first injected channel in adc2 are converted...

  • Page 224

    Analog-to-digital converter (adc) rm0008 224/1096 doc id 13902 rev 12 figure 36. Alternate + regular simultaneous if a trigger occurs during an injected conversion that has interrupted a regular conversion, it will be ignored. Figure 37 shows the behavior in this case (2nd trig is ignored). Figure 3...

  • Page 225: 11.10 Temperature

    Rm0008 analog-to-digital converter (adc) doc id 13902 rev 12 225/1096 11.10 temperature sensor the temperature sensor can be used to measure the ambient temperature (t a ) of the device. The temperature sensor is internally connected to the adcx_in16 input channel which is used to convert the sensor...

  • Page 226: 11.11 Adc

    Analog-to-digital converter (adc) rm0008 226/1096 doc id 13902 rev 12 reading the temperature to use the sensor: 1. Select the adcx_in16 input channel. 2. Select a sample time of 17.1 µs 3. Set the tsvrefe bit in the adc control register 2 (adc_cr2) to wake up the temperature sensor from power down ...

  • Page 227: 11.12 Adc

    Rm0008 analog-to-digital converter (adc) doc id 13902 rev 12 227/1096 11.12 adc registers refer to section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 11.12.1 adc status register (adc_sr) address offset: 0x...

  • Page 228

    Analog-to-digital converter (adc) rm0008 228/1096 doc id 13902 rev 12 11.12.2 adc control register 1 (adc_cr1) address offset: 0x04 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved awden jawden reserved dualmod[3:0] rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

  • Page 229

    Rm0008 analog-to-digital converter (adc) doc id 13902 rev 12 229/1096 bit 12 jdiscen: discontinuous mode on injected channels this bit set and cleared by software to enable/disable discontinuous mode on injected group channels 0: discontinuous mode on injected channels disabled 1: discontinuous mode...

  • Page 230

    Analog-to-digital converter (adc) rm0008 230/1096 doc id 13902 rev 12 11.12.3 adc control register 2 (adc_cr2) address offset: 0x08 reset value: 0x0000 0000 bits 4:0 awdch[4:0]: analog watchdog channel select bits these bits are set and cleared by software. They select the input channel to be guarde...

  • Page 231

    Rm0008 analog-to-digital converter (adc) doc id 13902 rev 12 231/1096 bit 20 exttrig: external trigger conversion mode for regular channels this bit is set and cleared by software to enable/disable the external trigger used to start conversion of a regular channel group. 0: conversion on external ev...

  • Page 232

    Analog-to-digital converter (adc) rm0008 232/1096 doc id 13902 rev 12 bits 14:12 jextsel[2:0]: external event select for injected group these bits select the external event used to trigger the start of conversion of an injected group: for adc1 and adc2 the assigned triggers are: 000: timer 1 trgo ev...

  • Page 233

    Rm0008 analog-to-digital converter (adc) doc id 13902 rev 12 233/1096 bit 1 cont: continuous conversion this bit is set and cleared by software. If set conversion takes place continuously till this bit is reset. 0: single conversion mode 1: continuous conversion mode bit 0 adon: a/d converter on / o...

  • Page 234

    Analog-to-digital converter (adc) rm0008 234/1096 doc id 13902 rev 12 11.12.4 adc sample time register 1 (adc_smpr1) address offset: 0x0c reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved smp17[2:0] smp16[2:0] smp15[2:1] rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7...

  • Page 235

    Rm0008 analog-to-digital converter (adc) doc id 13902 rev 12 235/1096 11.12.5 adc sample time register 2 (adc_smpr2) address offset: 0x10 reset value: 0x0000 0000 11.12.6 adc injected channel data offset register x (adc_jofrx)(x=1..4) address offset: 0x14-0x20 reset value: 0x0000 0000 31 30 29 28 27...

  • Page 236

    Analog-to-digital converter (adc) rm0008 236/1096 doc id 13902 rev 12 11.12.7 adc watchdog high threshold register (adc_htr) address offset: 0x24 reset value: 0x0000 0fff 11.12.8 adc watchdog low threshold register (adc_ltr) address offset: 0x28 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22...

  • Page 237

    Rm0008 analog-to-digital converter (adc) doc id 13902 rev 12 237/1096 11.12.9 adc regular sequence register 1 (adc_sqr1) address offset: 0x2c reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved l[3:0] sq16[4:1] rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

  • Page 238

    Analog-to-digital converter (adc) rm0008 238/1096 doc id 13902 rev 12 11.12.10 adc regular sequence register 2 (adc_sqr2) address offset: 0x30 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sq12[4:0] sq11[4:0] sq10[4:1] rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 ...

  • Page 239

    Rm0008 analog-to-digital converter (adc) doc id 13902 rev 12 239/1096 11.12.11 adc regular sequence register 3 (adc_sqr3) address offset: 0x34 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sq6[4:0] sq5[4:0] sq4[4:1] rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 ...

  • Page 240

    Analog-to-digital converter (adc) rm0008 240/1096 doc id 13902 rev 12 11.12.12 adc injected sequence register (adc_jsqr) address offset: 0x38 reset value: 0x0000 0000 11.12.13 adc injected data register x (adc_jdrx) (x= 1..4) address offset: 0x3c - 0x48 reset value: 0x0000 0000 31 30 29 28 27 26 25 ...

  • Page 241

    Rm0008 analog-to-digital converter (adc) doc id 13902 rev 12 241/1096 11.12.14 adc regular data register (adc_dr) address offset: 0x4c reset value: 0x0000 0000 11.12.15 adc register map the following table summarizes the adc registers. Bits 31:16 reserved, must be kept cleared. Bits 15:0 jdata[15:0]...

  • Page 242

    Analog-to-digital converter (adc) rm0008 242/1096 doc id 13902 rev 12 refer to table 3 on page 50 for the register boundary addresses. 0x14 adc_jofr1 reserved joffset1[11:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0x18 adc_jofr2 reserved joffset2[11:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0x1c adc_jofr3 ...

  • Page 243: 12 Digital-to-Analog

    Rm0008 digital-to-analog converter (dac) doc id 13902 rev 12 243/1096 12 digital-to-analog converter (dac) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f1...

  • Page 244

    Digital-to-analog converter (dac) rm0008 244/1096 doc id 13902 rev 12 figure 40. Dac channel block diagram 1. In connectivity line devices, the tim8_trgo trigger is replaced by tim3_trgo . Note: once the dac channelx is enabled, the corresponding gpio pin (pa4 or pa5) is automatically connected to t...

  • Page 245: 12.3

    Rm0008 digital-to-analog converter (dac) doc id 13902 rev 12 245/1096 12.3 dac functional description 12.3.1 dac channel enable each dac channel can be powered on by setting its corresponding enx bit in the dac_cr register. The dac channel is then enabled after a startup time t wakeup . Note: the en...

  • Page 246

    Digital-to-analog converter (dac) rm0008 246/1096 doc id 13902 rev 12 figure 41. Data registers in single dac channel mode ● dual dac channels, there are three possibilities: – 8-bit right alignment: data for dac channel1 to be loaded into dac_dhr8rd [7:0] bits (stored into dhr1[11:4] bits) and data...

  • Page 247

    Rm0008 digital-to-analog converter (dac) doc id 13902 rev 12 247/1096 figure 43. Timing diagram for conversion with trigger disabled ten = 0 12.3.5 dac output voltage digital inputs are converted to output voltages on a linear conversion between 0 and v ref+ . The analog output voltages on each dac ...

  • Page 248

    Digital-to-analog converter (dac) rm0008 248/1096 doc id 13902 rev 12 note: 1 tselx[2:0] bit cannot be changed when the enx bit is set. 2 when software trigger is selected, it takes only one apb1 clock cycle for dac_dhrx-to- dac_dorx register transfer. 12.3.7 dma request each dac channel has a dma c...

  • Page 249

    Rm0008 digital-to-analog converter (dac) doc id 13902 rev 12 249/1096 figure 45. Dac conversion (sw trigger enabled) with lfsr wave generation note: dac trigger must be enabled for noise generation, by setting the tenx bit in the dac_cr register. 12.3.9 triangle-wave generation it is possible to add...

  • Page 250: 12.4

    Digital-to-analog converter (dac) rm0008 250/1096 doc id 13902 rev 12 figure 47. Dac conversion (sw trigger enabled) with triangle wave generation note: 1 dac trigger must be enabled for noise generation, by setting the tenx bit in the dac_cr register. 2 mampx[3:0] bits must be configured before ena...

  • Page 251

    Rm0008 digital-to-analog converter (dac) doc id 13902 rev 12 251/1096 12.4.2 independent trigger with same lfsr generation to configure the dac in this conversion mode, the following sequence is required: ● set the two dac channel trigger enable bits ten1 and ten2 ● configure different trigger sourc...

  • Page 252

    Digital-to-analog converter (dac) rm0008 252/1096 doc id 13902 rev 12 dac_dor1 (three apb1 clock cycles later). The dac channel1 triangle counter is then updated. When a dac channel2 trigger arrives, the dac channel2 triangle counter, with the same triangle amplitude, is added to the dhr2 register a...

  • Page 253

    Rm0008 digital-to-analog converter (dac) doc id 13902 rev 12 253/1096 12.4.8 simultaneous trigger with same lfsr generation to configure the dac in this conversion mode, the following sequence is required: ● set the two dac channel trigger enable bits ten1 and ten2 ● configure the same trigger sourc...

  • Page 254: 12.5 Dac

    Digital-to-analog converter (dac) rm0008 254/1096 doc id 13902 rev 12 added to the dhr2 register and the sum is transferred into dac_dor2 (three apb1 clock cycles later). The dac channel2 triangle counter is then updated. 12.4.11 simultaneous trigger with different triangle generation to configure t...

  • Page 255

    Rm0008 digital-to-analog converter (dac) doc id 13902 rev 12 255/1096 bit 27:24 mamp2[3:0]: dac channel2 mask/amplitude selector these bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: unmask bit0 of lfsr/ triangle amplitude equal to ...

  • Page 256

    Digital-to-analog converter (dac) rm0008 256/1096 doc id 13902 rev 12 bits 15:13 reserved. Bit 12 dmaen1: dac channel1 dma enable this bit is set and cleared by software. 0: dac channel1 dma mode disabled 1: dac channel1 dma mode enabled bits 11:8 mamp1[3:0]: dac channel1 mask/amplitude selector the...

  • Page 257

    Rm0008 digital-to-analog converter (dac) doc id 13902 rev 12 257/1096 12.5.2 dac software trigger register (dac_swtrigr) address offset: 0x04 reset value: 0x0000 0000 bit 1 boff1: dac channel1 output buffer disable this bit set and cleared by software to enable/disable dac channel1 output buffer. 0:...

  • Page 258

    Digital-to-analog converter (dac) rm0008 258/1096 doc id 13902 rev 12 12.5.3 dac channel1 12-bit right-aligned data holding register (dac_dhr12r1) address offset: 0x08 reset value: 0x0000 0000 12.5.4 dac channel1 12-bit left aligned data holding register (dac_dhr12l1) address offset: 0x0c reset valu...

  • Page 259

    Rm0008 digital-to-analog converter (dac) doc id 13902 rev 12 259/1096 12.5.6 dac channel2 12-bit right aligned data holding register (dac_dhr12r2) address offset: 0x14 reset value: 0x0000 0000 12.5.7 dac channel2 12-bit left aligned data holding register (dac_dhr12l2) address offset: 0x18 reset valu...

  • Page 260

    Digital-to-analog converter (dac) rm0008 260/1096 doc id 13902 rev 12 12.5.9 dual dac 12-bit right-aligned data holding register (dac_dhr12rd) address offset: 0x20 reset value: 0x0000 0000 12.5.10 dual dac 12-bit left aligned data holding register (dac_dhr12ld) address offset: 0x24 reset value: 0x00...

  • Page 261

    Rm0008 digital-to-analog converter (dac) doc id 13902 rev 12 261/1096 12.5.11 dual dac 8-bit right aligned data holding register (dac_dhr8rd) address offset: 0x28 reset value: 0x0000 0000 12.5.12 dac channel1 data output register (dac_dor1) address offset: 0x2c reset value: 0x0000 0000 12.5.13 dac c...

  • Page 262

    Digital-to-analog converter (dac) rm0008 262/1096 doc id 13902 rev 12 12.5.14 dac register map the following table summarizes the dac registers. Note: refer to table 3 on page 50 for the register boundary addresses. Table 75. Dac register map offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18...

  • Page 263: Dma Controller (Dma)

    Rm0008 dma controller (dma) doc id 13902 rev 12 263/1096 13 dma controller (dma) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102xx and stm32f103xx micro...

  • Page 264

    Dma controller (dma) rm0008 264/1096 doc id 13902 rev 12 the block diagram is shown in figure 48 . Figure 48. Dma block diagram in connectivity line devices &,)4& #h #h #h !Rbiter #ortex - 32!- !(" $-! )#ode $#ode 3ys tem $-! !0" &lash "ridge "ridge #h #h #h !Rbiter !(" $-! !0" aib $-! "us ix $-! $-...

  • Page 265: 13.3

    Rm0008 dma controller (dma) doc id 13902 rev 12 265/1096 figure 49. Dma block diagram in low-, medium- high- and xl-density devices 1. The dma2 controller is available only in high-density and xl-density devices. 1. Adc3, spi/i2s3, uart4, sdio, tim5, tim6, dac, tim7, tim8 dma requests are available ...

  • Page 266

    Dma controller (dma) rm0008 266/1096 doc id 13902 rev 12 in summary, each dma transfer consists of three operations: ● the loading of data from the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start address used for th...

  • Page 267

    Rm0008 dma controller (dma) doc id 13902 rev 12 267/1096 addresses (in the current internal peripheral/memory address register) are not accessible by software. If the channel is configured in noncircular mode, no dma request is served after the last transfer (that is once the number of data items to...

  • Page 268

    Dma controller (dma) rm0008 268/1096 doc id 13902 rev 12 the transfer stops once the dma_cndtrxregister reaches zero. Memory to memory mode may not be used at the same time as circular mode. 13.3.4 programmable data width, data alignment and endians when psize and msize are not equal, the dma perfor...

  • Page 269

    Rm0008 dma controller (dma) doc id 13902 rev 12 269/1096 and does not generate any error, the dma writes the 32 hwdata bits as shown in the two examples below: ● to write the halfword “0xabcd”, the dma sets the hwdata bus to “0xabcdabcd” with hsize = halfword ● to write the byte “0xab”, the dma sets...

  • Page 270

    Dma controller (dma) rm0008 270/1096 doc id 13902 rev 12 13.3.7 dma request mapping dma1 controller the 7 requests from the peripherals (timx[1,2,3,4], adc1, spi1, spi/i2s2, i2cx[1,2] and usartx[1,2,3]) are simply logically ored before entering the dma1, this means that only one request must be enab...

  • Page 271

    Rm0008 dma controller (dma) doc id 13902 rev 12 271/1096 table 78 lists the dma requests for each channel. Dma2 controller the 5 requests from the peripherals (timx[5,6,7,8], adc3, spi/i2s3, uart4, dac_channel[1,2] and sdio) are simply logically ored before entering the dma2, this means that only on...

  • Page 272

    Dma controller (dma) rm0008 272/1096 doc id 13902 rev 12 figure 51. Dma2 request mapping table 79 lists the dma2 requests for each channel. Table 79. Summary of dma2 requests for each channel peripherals channel 1 channel 2 channel 3 channel 4 channel 5 adc3 (1) 1. Adc3, sdio and tim8 dma requests a...

  • Page 273: 13.4 Dma

    Rm0008 dma controller (dma) doc id 13902 rev 12 273/1096 13.4 dma registers refer to section 2.1 on page 46 for a list of abbreviations used in register descriptions. Note: in the following registers, all bits related to channel6 and channel7 are not relevant for dma2 since it has only 5 channels. T...

  • Page 274

    Dma controller (dma) rm0008 274/1096 doc id 13902 rev 12 13.4.2 dma interrupt flag clear register (dma_ifcr) address offset: 0x04 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved cteif7 chtif7 ctcif7 cgif7 cteif6 chtif6 ctcif6 cgif6 cteif5 chtif5 ctcif5 cgif5 w w w w...

  • Page 275

    Rm0008 dma controller (dma) doc id 13902 rev 12 275/1096 13.4.3 dma channel x configuration register (dma_ccrx) (x = 1..7, where x = channel number) address offset: 0x08 + 0d20 × (channel number – 1) reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 ...

  • Page 276

    Dma controller (dma) rm0008 276/1096 doc id 13902 rev 12 13.4.4 dma channel x number of data register (dma_cndtrx) (x = 1..7), where x = channel number) address offset: 0x0c + 0d20 × (channel number – 1) reset value: 0x0000 0000 bit 4 dir: data transfer direction this bit is set and cleared by softw...

  • Page 277

    Rm0008 dma controller (dma) doc id 13902 rev 12 277/1096 13.4.5 dma channel x peripheral address register (dma_cparx) (x = 1..7), where x = channel number) address offset: 0x10 + 0d20 × (channel number – 1) reset value: 0x0000 0000 this register must not be written when the channel is enabled. 13.4....

  • Page 278

    Dma controller (dma) rm0008 278/1096 doc id 13902 rev 12 13.4.7 dma register map the following table gives the dma register map and the reset values. Table 80. Dma register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00...

  • Page 279

    Rm0008 dma controller (dma) doc id 13902 rev 12 279/1096 refer to table 3 on page 50 for the register boundary addresses. 0x04c dma_cpar4 pa[31:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x050 dma_cmar4 ma[31:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

  • Page 280: 14.1 Tim1&tim8

    Advanced-control timers (tim1&tim8) rm0008 280/1096 doc id 13902 rev 12 14 advanced-control timers (tim1&tim8) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm...

  • Page 281: 14.2

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 281/1096 14.2 tim1&tim8 main features tim1&tim8 timer features include: ● 16-bit up, down, up/down auto-reload counter. ● 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock frequency either by any facto...

  • Page 282

    Advanced-control timers (tim1&tim8) rm0008 282/1096 doc id 13902 rev 12 figure 52. Advanced-control timer block diagram prescaler autoreload register counter capture/compare 1 register capture/compare 2 register u u u cc1i cc2i etr trigger controller +/- stop, clear or up/down ti1fp1 ti2fp2 itr0 itr...

  • Page 283: 14.3

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 283/1096 14.3 tim1&tim8 functional description 14.3.1 time-base unit the main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down....

  • Page 284

    Advanced-control timers (tim1&tim8) rm0008 284/1096 doc id 13902 rev 12 figure 53. Counter timing diagram with prescaler division change from 1 to 2 figure 54. Counter timing diagram with prescaler division change from 1 to 4 14.3.2 counter modes upcounting mode in upcounting mode, the counter count...

  • Page 285

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 285/1096 preload registers. Then no update event occurs until the udis bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the ...

  • Page 286

    Advanced-control timers (tim1&tim8) rm0008 286/1096 doc id 13902 rev 12 figure 57. Counter timing diagram, internal clock divided by 4 figure 58. Counter timing diagram, internal clock divided by n figure 59. Counter timing diagram, update event when arpe=0 (timx_arr not preloaded) ck_psc 0000 0001 ...

  • Page 287

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 287/1096 figure 60. Counter timing diagram, update event when arpe=1 (timx_arr preloaded) downcounting mode in downcounting mode, the counter counts from the auto-reload value (content of the timx_arr register) down to 0, then restarts f...

  • Page 288

    Advanced-control timers (tim1&tim8) rm0008 288/1096 doc id 13902 rev 12 the following figures show some examples of the counter behavior for different clock frequencies when timx_arr=0x36. Figure 61. Counter timing diagram, internal clock divided by 1 figure 62. Counter timing diagram, internal cloc...

  • Page 289

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 289/1096 figure 64. Counter timing diagram, internal clock divided by n figure 65. Counter timing diagram, update event when repetition counter is not used center-aligned mode (up/down counting) in center-aligned mode, the counter counts...

  • Page 290

    Advanced-control timers (tim1&tim8) rm0008 290/1096 doc id 13902 rev 12 the uev update event can be disabled by software by setting the udis bit in the timx_cr1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs unt...

  • Page 291

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 291/1096 figure 67. Counter timing diagram, internal clock divided by 2 figure 68. Counter timing diagram, internal clock divided by 4, timx_arr=0x36 1. Center-aligned mode 2 or 3 is used with an uif on overflow. Figure 69. Counter timin...

  • Page 292

    Advanced-control timers (tim1&tim8) rm0008 292/1096 doc id 13902 rev 12 figure 70. Counter timing diagram, update event with arpe=1 (counter underflow) figure 71. Counter timing diagram, update event with arpe=1 (counter overflow) 14.3.3 repetition counter section 14.3.1: time-base unit describes ho...

  • Page 293

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 293/1096 the repetition counter is decremented: ● at each counter overflow in upcounting mode, ● at each counter underflow in downcounting mode, ● at each counter overflow and at each counter underflow in center-aligned mode. Although th...

  • Page 294

    Advanced-control timers (tim1&tim8) rm0008 294/1096 doc id 13902 rev 12 14.3.4 clock selection the counter clock can be provided by the following clock sources: ● internal clock (ck_int) ● external clock mode1: external input pin ● external clock mode2: external trigger input etr ● internal trigger ...

  • Page 295

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 295/1096 for example, to configure the upcounter to count in response to a rising edge on the ti2 input, use the following procedure: 1. Configure channel 2 to detect rising edges on the ti2 input by writing cc2s = ‘01’ in the timx_ccmr1...

  • Page 296

    Advanced-control timers (tim1&tim8) rm0008 296/1096 doc id 13902 rev 12 for example, to configure the upcounter to count each 2 rising edges on etr, use the following procedure: 1. As no filter is needed in this example, write etf[3:0]=0000 in the timx_smcr register. 2. Set the prescaler by writing ...

  • Page 297

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 297/1096 figure 78. Capture/compare channel (example: channel 1 input stage) the output stage generates an intermediate waveform which is then used for reference: ocxref (active high). The polarity acts at the end of the chain. Figure 79...

  • Page 298

    Advanced-control timers (tim1&tim8) rm0008 298/1096 doc id 13902 rev 12 figure 80. Output stage of capture/compare channel (channel 1 to 3) figure 81. Output stage of capture/compare channel (channel 4) the capture/compare block is made of one preload register and one shadow register. Write and read...

  • Page 299

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 299/1096 the following example shows how to capture the counter value in timx_ccr1 when ti1 input rises. To do this, use the following procedure: ● select the active input: timx_ccr1 must be linked to the ti1 input, so write the cc1s bit...

  • Page 300

    Advanced-control timers (tim1&tim8) rm0008 300/1096 doc id 13902 rev 12 for example, you can measure the period (in timx_ccr1 register) and the duty cycle (in timx_ccr2 register) of the pwm applied on ti1 using the following procedure (depending on ck_int frequency and prescaler value): ● select the...

  • Page 301

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 301/1096 anyway, the comparison between the timx_ccrx shadow register and the counter is still performed and allows the flag to be set. Interrupt and dma requests can be sent accordingly. This is described in the output compare mode sect...

  • Page 302

    Advanced-control timers (tim1&tim8) rm0008 302/1096 doc id 13902 rev 12 figure 83. Output compare mode, toggle on oc1. 14.3.10 pwm mode pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the timx_arr register and a duty cycle determined by the val...

  • Page 303

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 303/1096 pwm edge-aligned mode ● upcounting configuration upcounting is active when the dir bit in the timx_cr1 register is low. Refer to the upcounting mode on page 284 . In the following example, we consider pwm mode 1. The reference p...

  • Page 304

    Advanced-control timers (tim1&tim8) rm0008 304/1096 doc id 13902 rev 12 figure 85. Center-aligned pwm waveforms (arr=8) hints on using center-aligned mode: ● when starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the ...

  • Page 305

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 305/1096 14.3.11 complementary outputs and dead-time insertion the advanced-control timers (tim1&tim8) can output two complementary signals and manage the switching-off and the switching-on instants of the outputs. This time is generally...

  • Page 306

    Advanced-control timers (tim1&tim8) rm0008 306/1096 doc id 13902 rev 12 figure 88. Dead-time waveforms with delay greater than the positive pulse. The dead-time delay is the same for each of the channels and is programmable with the dtg bits in the timx_bdtr register. Refer to section 14.4.18: tim1&...

  • Page 307

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 307/1096 must insert a delay (dummy instruction) before reading it correctly. This is because you write the asynchronous signal and read the synchronous signal. When a break occurs (selected level on the break input): ● the moe bit is cl...

  • Page 308

    Advanced-control timers (tim1&tim8) rm0008 308/1096 doc id 13902 rev 12 figure 89. Output behavior in response to a break. Delay ocxref break (moe ocx (ocxn not implemented, ccxp=0, oisx=1) ocx (ocxn not implemented, ccxp=0, oisx=0) ocx (ocxn not implemented, ccxp=1, oisx=1) ocx (ocxn not implemente...

  • Page 309

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 309/1096 14.3.13 clearing the ocxref signal on an external event the ocxref signal for a given channel can be driven low by applying a high level to the etrf input (ocxce enable bit of the corresponding timx_ccmrx register set to ‘1’). T...

  • Page 310

    Advanced-control timers (tim1&tim8) rm0008 310/1096 doc id 13902 rev 12 14.3.14 6-step pwm generation when complementary outputs are used on a channel, preload bits are available on the ocxm, ccxe and ccxne bits. The preload bits are transferred to the shadow bits at the com commutation event. Thus ...

  • Page 311

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 311/1096 14.3.15 one-pulse mode one-pulse mode (opm) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay....

  • Page 312

    Advanced-control timers (tim1&tim8) rm0008 312/1096 doc id 13902 rev 12 the opm waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). ● the t delay is defined by the value written in the timx_ccr1 register. ● the t pulse is defined ...

  • Page 313

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 313/1096 repetition counter, trigger output features continue to work as normal. Encoder mode and external clock mode 2 are not compatible and must not be selected together. In this mode, the counter is modified automatically following t...

  • Page 314

    Advanced-control timers (tim1&tim8) rm0008 314/1096 doc id 13902 rev 12 figure 93. Example of counter operation in encoder interface mode. Figure 94 gives an example of counter behavior when ti1fp1 polarity is inverted (same configuration as above except cc1p=’1’). Figure 94. Example of encoder inte...

  • Page 315

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 315/1096 14.3.17 timer input xor function the ti1s bit in the timx_cr2 register, allows the input filter of channel 1 to be connected to the output of a xor gate, combining the three input pins timx_ch1, timx_ch2 and timx_ch3. The xor ou...

  • Page 316

    Advanced-control timers (tim1&tim8) rm0008 316/1096 doc id 13902 rev 12 written after a com event for the next step (this can be done in an interrupt subroutine generated by the rising edge of oc2ref). The figure 95 describes this example. Figure 95. Example of hall sensor interface counter (cnt) tr...

  • Page 317

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 317/1096 14.3.19 timx and external trigger synchronization the timx timer can be synchronized with an external trigger in several modes: reset mode, gated mode and trigger mode. Slave mode: reset mode the counter and its prescaler can be...

  • Page 318

    Advanced-control timers (tim1&tim8) rm0008 318/1096 doc id 13902 rev 12 slave mode: gated mode the counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when ti1 input is low: ● configure the channel 1 to detect low levels on ti1. Conf...

  • Page 319

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 319/1096 slave mode: trigger mode the counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on ti2 input: ● configure the channel 2 to detect rising edg...

  • Page 320

    Advanced-control timers (tim1&tim8) rm0008 320/1096 doc id 13902 rev 12 2. Configure the channel 1 as follows, to detect rising edges on ti: – ic1f=0000: no filter. – the capture prescaler is not used for triggering and does not need to be configured. – cc1s=01in timx_ccmr1 register to select only t...

  • Page 321: 14.4 Tim1&tim8

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 321/1096 14.4 tim1&tim8 registers refer to section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 14.4.1 tim1&tim8 control regi...

  • Page 322

    Advanced-control timers (tim1&tim8) rm0008 322/1096 doc id 13902 rev 12 14.4.2 tim1&tim8 control register 2 (timx_cr2) address offset: 0x04 reset value: 0x0000 bit 2 urs:update request source this bit is set and cleared by software to select the uev event sources. 0: any of the following events gene...

  • Page 323

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 323/1096 bit 9 ois1n: output idle state 1 (oc1n output) 0: oc1n=0 after a dead-time when moe=0 1: oc1n=1 after a dead-time when moe=0 note: this bit can not be modified as long as lock level 1, 2 or 3 has been programmed (lock bits in ti...

  • Page 324

    Advanced-control timers (tim1&tim8) rm0008 324/1096 doc id 13902 rev 12 14.4.3 tim1&tim8 slave mode control register (timx_smcr) address offset: 0x08 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 etp ece etps[1:0] etf[3:0] msm ts[2:0] res. Sms[2:0] rw rw rw rw rw rw rw rw rw rw rw rw res...

  • Page 325

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 325/1096 bits 11:8 etf[3:0]: external trigger filter this bit-field then defines the frequency used to sample etrp signal and the length of the digital filter applied to etrp. The digital filter is made of an event counter in which n eve...

  • Page 326

    Advanced-control timers (tim1&tim8) rm0008 326/1096 doc id 13902 rev 12 14.4.4 tim1&tim8 dma/interrupt enable register (timx_dier) address offset: 0x0c reset value: 0x0000 bits 2:0 sms: slave mode selection when external signals are selected the active edge of the trigger signal (trgi) is linked to ...

  • Page 327

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 327/1096 bit 12 cc4de: capture/compare 4 dma request enable 0: cc4 dma request disabled 1: cc4 dma request enabled bit 11 cc3de: capture/compare 3 dma request enable 0: cc3 dma request disabled 1: cc3 dma request enabled bit 10 cc2de: ca...

  • Page 328

    Advanced-control timers (tim1&tim8) rm0008 328/1096 doc id 13902 rev 12 14.4.5 tim1&tim8 status register (timx_sr) address offset: 0x10 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved cc4of cc3of cc2of cc1of res. Bif tif comif cc4if cc3if cc2if cc1if uif rc_w0 rc_w0 rc_w0 rc_w0 re...

  • Page 329

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 329/1096 14.4.6 tim1&tim8 event generation register (timx_egr) address offset: 0x14 reset value: 0x0000 bit 2 cc2if: capture/compare 2 interrupt flag refer to cc1if description bit 1 cc1if: capture/compare 1 interrupt flag if channel cc1...

  • Page 330

    Advanced-control timers (tim1&tim8) rm0008 330/1096 doc id 13902 rev 12 bit 6 tg: trigger generation this bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: no action 1: the tif flag is set in timx_sr register. Related interrupt or dma transfer can occu...

  • Page 331

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 331/1096 14.4.7 tim1&tim8 capture/compare mode register 1 (timx_ccmr1) address offset: 0x18 reset value: 0x0000 the channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by config...

  • Page 332

    Advanced-control timers (tim1&tim8) rm0008 332/1096 doc id 13902 rev 12 bits 6:4 oc1m: output compare 1 mode these bits define the behavior of the output reference signal oc1ref from which oc1 and oc1n are derived. Oc1ref is active high whereas oc1 and oc1n active level depends on cc1p and cc1np bit...

  • Page 333

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 333/1096 input capture mode bits 1:0 cc1s: capture/compare 1 selection this bit-field defines the direction of the channel (input/output) as well as the used input. 00: cc1 channel is configured as output 01: cc1 channel is configured as...

  • Page 334

    Advanced-control timers (tim1&tim8) rm0008 334/1096 doc id 13902 rev 12 14.4.8 tim1&tim8 capture/compare mode register 2 (timx_ccmr2) address offset: 0x1c reset value: 0x0000 refer to the above ccmr1 register description. Output compare mode bits 1:0 cc1s: capture/compare 1 selection this bit-field ...

  • Page 335

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 335/1096 input capture mode 14.4.9 tim1&tim8 capture/compare enable register (timx_ccer) address offset: 0x20 reset value: 0x0000 bits 15:12 ic4f:input capture 4 filter bits 11:10 ic4psc:input capture 4 prescaler bits 9:8 cc4s: capture/c...

  • Page 336

    Advanced-control timers (tim1&tim8) rm0008 336/1096 doc id 13902 rev 12 bit 7 cc2np: capture/compare 2 complementary output polarity refer to cc1np description bit 6 cc2ne: capture/compare 2 complementary output enable refer to cc1ne description bit 5 cc2p: capture/compare 2 output polarity refer to...

  • Page 337

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 337/1096 note: the state of the external i/o pins connected to the complementary ocx and ocxn channels depends on the ocx and ocxn channel state and the gpio and afio registers. Table 83. Output control bits for complementary ocx and ocx...

  • Page 338

    Advanced-control timers (tim1&tim8) rm0008 338/1096 doc id 13902 rev 12 14.4.10 tim1&tim8 counter (timx_cnt) address offset: 0x24 reset value: 0x0000 14.4.11 tim1&tim8 prescaler (timx_psc) address offset: 0x28 reset value: 0x0000 14.4.12 tim1&tim8 auto-reload register (timx_arr) address offset: 0x2c...

  • Page 339

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 339/1096 14.4.13 tim1&tim8 repetition counter register (timx_rcr) address offset: 0x30 reset value: 0x0000 14.4.14 tim1&tim8 capture/compare register 1 (timx_ccr1) address offset: 0x34 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 ...

  • Page 340

    Advanced-control timers (tim1&tim8) rm0008 340/1096 doc id 13902 rev 12 14.4.15 tim1&tim8 capture/compare register 2 (timx_ccr2) address offset: 0x38 reset value: 0x0000 14.4.16 tim1&tim8 capture/compare register 3 (timx_ccr3) address offset: 0x3c reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 ...

  • Page 341

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 341/1096 14.4.17 tim1&tim8 capture/compare register 4 (timx_ccr4) address offset: 0x40 reset value: 0x0000 14.4.18 tim1&tim8 break and dead-time register (timx_bdtr) address offset: 0x44 reset value: 0x0000 note: as the bits aoe, bkp, bk...

  • Page 342

    Advanced-control timers (tim1&tim8) rm0008 342/1096 doc id 13902 rev 12 bit 13 bkp: break polarity 0: break input brk is active low 1: break input brk is active high note: this bit can not be modified as long as lock level 1 has been programmed (lock bits in timx_bdtr register). Note: any write oper...

  • Page 343

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 343/1096 14.4.19 tim1&tim8 dma control register (timx_dcr) address offset: 0x48 reset value: 0x0000 bits 7:0 dtg[7:0]: dead-time generator setup this bit-field defines the duration of the dead-time inserted between the complementary outp...

  • Page 344

    Advanced-control timers (tim1&tim8) rm0008 344/1096 doc id 13902 rev 12 14.4.20 tim1&tim8 dma address for full transfer (timx_dmar) address offset: 0x4c reset value: 0x0000 14.4.21 tim1&tim8 register map tim1&tim8 registers are mapped as 16-bit addressable registers as described in the table below: ...

  • Page 345

    Rm0008 advanced-control timers (tim1&tim8) doc id 13902 rev 12 345/1096 0x04 timx_cr2 reserved oi s4 oi s3 n oi s3 oi s2 n oi s2 oi s1 n oi s1 ti 1 s mms[2:0] cc ds cc us reser v ed cc p c reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x08 timx_smcr reserved etp ece etps [1:0] etf[3:0] msm ts[2:0] re s e ...

  • Page 346

    Advanced-control timers (tim1&tim8) rm0008 346/1096 doc id 13902 rev 12 refer to table 3 on page 50 for the register boundary addresses. 0x40 timx_ccr4 reserved ccr4[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x44 timx_bdtr reserved moe ao e bk p bk e os sr os si lock [1:0] dt[7:0] reset valu...

  • Page 347: 15.1

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 347/1096 15 general-purpose timers (tim2 to tim5) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx,...

  • Page 348: 15.2

    General-purpose timers (tim2 to tim5) rm0008 348/1096 doc id 13902 rev 12 15.2 timx main features general-purpose timx timer features include: ● 16-bit up, down, up/down auto-reload counter. ● 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor ...

  • Page 349: 15.3

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 349/1096 figure 100. General-purpose timer block diagram 15.3 timx functional description 15.3.1 time-base unit the main block of the programmable timer is a 16-bit counter with its related auto-reload register. The counter can count u...

  • Page 350

    General-purpose timers (tim2 to tim5) rm0008 350/1096 doc id 13902 rev 12 the auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each upda...

  • Page 351

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 351/1096 figure 102. Counter timing diagram with prescaler division change from 1 to 4 15.3.2 counter modes upcounting mode in upcounting mode, the counter counts from 0 to the auto-reload value (content of the timx_arr register), then...

  • Page 352

    General-purpose timers (tim2 to tim5) rm0008 352/1096 doc id 13902 rev 12 figure 103. Counter timing diagram, internal clock divided by 1 figure 104. Counter timing diagram, internal clock divided by 2 figure 105. Counter timing diagram, internal clock divided by 4 ck_int 00 cnt_en timer clock = ck_...

  • Page 353

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 353/1096 figure 106. Counter timing diagram, internal clock divided by n figure 107. Counter timing diagram, update event when arpe=0 (timx_arr not preloaded) timer clock = ck_cnt counter register 00 1f 20 update interrupt flag (uif) c...

  • Page 354

    General-purpose timers (tim2 to tim5) rm0008 354/1096 doc id 13902 rev 12 figure 108. Counter timing diagram, update event when arpe=1 (timx_arr preloaded) downcounting mode in downcounting mode, the counter counts from the auto-reload value (content of the timx_arr register) down to 0, then restart...

  • Page 355

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 355/1096 figure 109. Counter timing diagram, internal clock divided by 1 figure 110. Counter timing diagram, internal clock divided by 2 figure 111. Counter timing diagram, internal clock divided by 4 ck_int 36 cnt_en timer clock = ck_...

  • Page 356

    General-purpose timers (tim2 to tim5) rm0008 356/1096 doc id 13902 rev 12 figure 112. Counter timing diagram, internal clock divided by n figure 113. Counter timing diagram, update event when repetition counter is not used center-aligned mode (up/down counting) in center-aligned mode, the counter co...

  • Page 357

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 357/1096 the uev update event can be disabled by software by setting the udis bit in timx_cr1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until...

  • Page 358

    General-purpose timers (tim2 to tim5) rm0008 358/1096 doc id 13902 rev 12 figure 115. Counter timing diagram, internal clock divided by 2 figure 116. Counter timing diagram, internal clock divided by 4, timx_arr=0x36 1. Center-aligned mode 2 or 3 is used with an uif on overflow. Figure 117. Counter ...

  • Page 359

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 359/1096 figure 118. Counter timing diagram, update event with arpe=1 (counter underflow) figure 119. Counter timing diagram, update event with arpe=1 (counter overflow) 00 cnt_en timer clock = ck_cnt counter register update interrupt ...

  • Page 360

    General-purpose timers (tim2 to tim5) rm0008 360/1096 doc id 13902 rev 12 15.3.3 clock selection the counter clock can be provided by the following clock sources: ● internal clock (ck_int) ● external clock mode1: external input pin (tix) ● external clock mode2: external trigger input (etr) ● interna...

  • Page 361

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 361/1096 figure 121. Ti2 external clock connection example for example, to configure the upcounter to count in response to a rising edge on the ti2 input, use the following procedure: for example, to configure the upcounter to count in...

  • Page 362

    General-purpose timers (tim2 to tim5) rm0008 362/1096 doc id 13902 rev 12 external clock source mode 2 this mode is selected by writing ece=1 in the timx_smcr register. The counter can count at each rising or falling edge on the external trigger input etr. The figure 123 gives an overview of the ext...

  • Page 363

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 363/1096 15.3.4 capture/compare channels each capture/compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output s...

  • Page 364

    General-purpose timers (tim2 to tim5) rm0008 364/1096 doc id 13902 rev 12 figure 127. Output stage of capture/compare channel (channel 1) the capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures ar...

  • Page 365

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 365/1096 15.3.5 input capture mode in input capture mode, the capture/compare registers (timx_ccrx) are used to latch the value of the counter after a transition detected by the corresponding icx signal. When a capture occurs, the corr...

  • Page 366

    General-purpose timers (tim2 to tim5) rm0008 366/1096 doc id 13902 rev 12 15.3.6 pwm input mode this mode is a particular case of input capture mode. The procedure is the same except: ● two icx signals are mapped on the same tix input. ● these 2 icx signals are active on edges with opposite polarity...

  • Page 367

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 367/1096 15.3.7 forced output mode in output mode (ccxs bits = 00 in the timx_ccmrx register), each output compare signal (ocxref and then ocx) can be forced to active or inactive level directly by software, independently of any compar...

  • Page 368

    General-purpose timers (tim2 to tim5) rm0008 368/1096 doc id 13902 rev 12 the timx_ccrx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (ocxpe=0, else timx_ccrx shadow register is updated only at the next update event ...

  • Page 369

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 369/1096 this forces the pwm by software while the timer is running. The timer is able to generate pwm in edge-aligned mode or center-aligned mode depending on the cms bits in the timx_cr1 register. Pwm edge-aligned mode upcounting con...

  • Page 370

    General-purpose timers (tim2 to tim5) rm0008 370/1096 doc id 13902 rev 12 figure 131 shows some center-aligned pwm waveforms in an example where: ● timx_arr=8, ● pwm mode is the pwm mode 1, ● the flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for cms=01 ...

  • Page 371

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 371/1096 – the direction is updated if you write 0 or write the timx_arr value in the counter but no update event uev is generated. ● the safest way to use center-aligned mode is to generate an update by software (setting the ug bit in...

  • Page 372

    General-purpose timers (tim2 to tim5) rm0008 372/1096 doc id 13902 rev 12 the opm waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). ● the t delay is defined by the value written in the timx_ccr1 register. ● the t pulse is define...

  • Page 373

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 373/1096 figure 133. Clearing timx ocxref 15.3.12 encoder interface mode to select encoder interface mode write sms=‘001 in the timx_smcr register if the counter is counting on ti2 edges only, sms=010 if it is counting on ti1 edges onl...

  • Page 374

    General-purpose timers (tim2 to tim5) rm0008 374/1096 doc id 13902 rev 12 an external incremental encoder can be connected directly to the mcu without external interface logic. However, comparators are normally be used to convert the encoder’s differential outputs to digital signals. This greatly in...

  • Page 375

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 375/1096 figure 135 gives an example of counter behavior when ic1fp1 polarity is inverted (same configuration as above except cc1p=1). Figure 135. Example of encoder interface mode with ic1fp1 polarity inverted. The timer, when configu...

  • Page 376

    General-purpose timers (tim2 to tim5) rm0008 376/1096 doc id 13902 rev 12 prescaler is not used for triggering, so you don’t need to configure it. The cc1s bits select the input capture source only, cc1s = 01 in the timx_ccmr1 register. Write cc1p=0 in timx_ccer register to validate the polarity (an...

  • Page 377

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 377/1096 figure 137. Control circuit in gated mode slave mode: trigger mode the counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on ti2 input: ● ...

  • Page 378

    General-purpose timers (tim2 to tim5) rm0008 378/1096 doc id 13902 rev 12 in the following example, the upcounter is incremented at each rising edge of the etr signal as soon as a rising edge of ti1 occurs: 1. Configure the external trigger input circuit by programming the timx_smcr register as foll...

  • Page 379

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 379/1096 using one timer as prescaler for another figure 140. Master/slave timer example for example, you can configure timer 1 to act as a prescaler for timer 2. Refer to figure 140 . To do this: ● configure timer 1 in master mode so ...

  • Page 380

    General-purpose timers (tim2 to tim5) rm0008 380/1096 doc id 13902 rev 12 figure 141. Gating timer 2 with oc1ref of timer 1 in the example in figure 141 , the timer 2 counter and prescaler are not initialized before being started. So they start counting from their current value. It is possible to st...

  • Page 381

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 381/1096 figure 142. Gating timer 2 with enable of timer 1 using one timer to start another timer in this example, we set the enable of timer 2 with the update event of timer 1. Refer to figure 140 for connections. Timer 2 starts count...

  • Page 382

    General-purpose timers (tim2 to tim5) rm0008 382/1096 doc id 13902 rev 12 as in the previous example, you can initialize both counters before starting counting. Figure 144 shows the behavior with the same configuration as in figure 143 but in trigger mode instead of gated mode (sms=110 in the tim2_s...

  • Page 383

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 383/1096 counters are aligned, timer 1 must be configured in master/slave mode (slave with respect to ti1, master with respect to timer 2): ● configure timer 1 master mode to send its enable as trigger output (mms=001 in the tim1_cr2 r...

  • Page 384: 15.4

    General-purpose timers (tim2 to tim5) rm0008 384/1096 doc id 13902 rev 12 15.4 timx2 to tim5 registers refer to section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 15.4.1 timx control reg...

  • Page 385

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 385/1096 bit 2 urs:update request source this bit is set and cleared by software to select the uev event sources. 0: any of the following events generate an update interrupt or dma request if enabled. These events can be: – counter ove...

  • Page 386

    General-purpose timers (tim2 to tim5) rm0008 386/1096 doc id 13902 rev 12 15.4.2 timx control register 2 (timx_cr2) address offset: 0x04 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ti1s mms[2:0] ccds reserved rw rw rw rw rw bits 15:8 reserved, always read as 0. Bit 7 ti1s: ti1...

  • Page 387

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 387/1096 15.4.3 timx slave mode control register (timx_smcr) address offset: 0x08 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 etp ece etps[1:0] etf[3:0] msm ts[2:0] res. Sms[2:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw ...

  • Page 388

    General-purpose timers (tim2 to tim5) rm0008 388/1096 doc id 13902 rev 12 bit 7 msm:master/slave mode 0: no action 1: the effect of an event on the trigger input (trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through trgo). It is useful if we want to s...

  • Page 389

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 389/1096 tim4 tim1 tim2 tim3 tim8 tim5 tim2 tim3 tim4 tim8 1. When a timer is not present in the product, the corresponding trigger itrx is not available. Table 86. Timx internal trigger connection (1) slave tim itr0 (ts = 000) itr1 (t...

  • Page 390

    General-purpose timers (tim2 to tim5) rm0008 390/1096 doc id 13902 rev 12 15.4.4 timx dma/interrupt enable register (timx_dier) address offset: 0x0c reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res. Tde res cc4de cc3de cc2de cc1de ude res. Tie res cc4ie cc3ie cc2ie cc1ie uie rw rw rw rw...

  • Page 391

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 391/1096 15.4.5 timx status register (timx_sr) address offset: 0x10 reset value: 0x0000 bit 2 cc2ie: capture/compare 2 interrupt enable 0: cc2 interrupt disabled. 1: cc2 interrupt enabled. Bit 1 cc1ie: capture/compare 1 interrupt enabl...

  • Page 392

    General-purpose timers (tim2 to tim5) rm0008 392/1096 doc id 13902 rev 12 bit 1 cc1if: capture/compare 1 interrupt flag if channel cc1 is configured as output: this flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the cms bits i...

  • Page 393

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 393/1096 15.4.6 timx event generation register (timx_egr) address offset: 0x14 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved tg res. Cc4g cc3g cc2g cc1g ug w w w w w w bits 15:7 reserved, always read as 0. Bit 6 tg...

  • Page 394

    General-purpose timers (tim2 to tim5) rm0008 394/1096 doc id 13902 rev 12 15.4.7 timx capture/compare mode register 1 (timx_ccmr1) address offset: 0x18 reset value: 0x0000 the channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuri...

  • Page 395

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 395/1096 bits 6:4 oc1m: output compare 1 mode these bits define the behavior of the output reference signal oc1ref from which oc1 and oc1n are derived. Oc1ref is active high whereas oc1 and oc1n active level depends on cc1p and cc1np b...

  • Page 396

    General-purpose timers (tim2 to tim5) rm0008 396/1096 doc id 13902 rev 12 input capture mode bits 15:12 ic2f: input capture 2 filter bits 11:10 ic2psc[1:0]:input capture 2 prescaler bits 9:8 cc2s: capture/compare 2 selection this bit-field defines the direction of the channel (input/output) as well ...

  • Page 397

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 397/1096 15.4.8 timx capture/compare mode register 2 (timx_ccmr2) address offset: 0x1c reset value: 0x0000 refer to the above ccmr1 register description. Output compare mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 oc4ce oc4m[2:0] oc4pe o...

  • Page 398

    General-purpose timers (tim2 to tim5) rm0008 398/1096 doc id 13902 rev 12 input capture mode 15.4.9 timx capture/compare enable register (timx_ccer) address offset: 0x20 reset value: 0x0000 bits 15:12 ic4f:input capture 4 filter bits 11:10 ic4psc: input capture 4 prescaler bits 9:8 cc4s: capture/com...

  • Page 399

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 399/1096 note: the state of the external io pins connected to the standard ocx channels depends on the ocx channel state and the gpio and afio registers. 15.4.10 timx counter (timx_cnt) address offset: 0x24 reset value: 0x0000 15.4.11 ...

  • Page 400

    General-purpose timers (tim2 to tim5) rm0008 400/1096 doc id 13902 rev 12 reset value: 0x0000 15.4.12 timx auto-reload register (timx_arr) address offset: 0x2c reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 psc[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 15:0 psc[15:0]: pre...

  • Page 401

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 401/1096 15.4.13 timx capture/compare register 1 (timx_ccr1) address offset: 0x34 reset value: 0x0000 15.4.14 timx capture/compare register 2 (timx_ccr2) address offset: 0x38 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cc...

  • Page 402

    General-purpose timers (tim2 to tim5) rm0008 402/1096 doc id 13902 rev 12 15.4.15 timx capture/compare register 3 (timx_ccr3) address offset: 0x3c reset value: 0x0000 15.4.16 timx capture/compare register 4 (timx_ccr4) address offset: 0x40 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cc...

  • Page 403

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 403/1096 15.4.17 timx dma control register (timx_dcr) address offset: 0x48 reset value: 0x0000 15.4.18 timx dma address for full transfer (timx_dmar) address offset: 0x4c reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserv...

  • Page 404

    General-purpose timers (tim2 to tim5) rm0008 404/1096 doc id 13902 rev 12 bits 15:0 dmab[15:0]: dma register for burst accesses a read or write access to the dmar register accesses the register located at the address: “(timx_cr1 address) + dba + (dma index)” in which: timx_cr1 address is the address...

  • Page 405

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 405/1096 15.4.19 timx register map timx registers are mapped as 16-bit addressable registers as described in the table below: table 88. Timx register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ...

  • Page 406

    General-purpose timers (tim2 to tim5) rm0008 406/1096 doc id 13902 rev 12 refer to table 3 on page 50 for the register boundary addresses. 0x28 timx_psc reserved psc[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x2c timx_arr reserved arr[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x30 re...

  • Page 407

    Rm0008 general-purpose timers (tim2 to tim5) doc id 13902 rev 12 407/1096.

  • Page 408: 16.1

    General-purpose timers (tim9 to tim14) rm0008 408/1096 doc id 13902 rev 12 16 general-purpose timers (tim9 to tim14) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101x...

  • Page 409: 16.2

    Rm0008 general-purpose timers (tim9 to tim14) doc id 13902 rev 12 409/1096 16.2 tim9 to tim14 main features 16.2.1 tim9/tim12 main features the features of the tim9/tim12 general-purpose timers include: ● 16-bit auto-reload upcounter ● 16-bit programmable prescaler used to divide the counter clock f...

  • Page 410: 16.3

    General-purpose timers (tim9 to tim14) rm0008 410/1096 doc id 13902 rev 12 16.3 tim10/tim11 and tim13/tim14 main features the features of general-purpose timers tim10/tim11 and tim13/tim14 include: ● 16-bit auto-reload upcounter ● 16-bit programmable prescaler used to divide the counter clock freque...

  • Page 411: 16.4

    Rm0008 general-purpose timers (tim9 to tim14) doc id 13902 rev 12 411/1096 16.4 tim9 to tim14 functional description 16.4.1 time-base unit the main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up. The counter clock ...

  • Page 412

    General-purpose timers (tim9 to tim14) rm0008 412/1096 doc id 13902 rev 12 figure 148. Counter timing diagram with prescaler division change from 1 to 2 figure 149. Counter timing diagram with prescaler division change from 1 to 4 16.4.2 counter modes upcounting mode in upcounting mode, the counter ...

  • Page 413

    Rm0008 general-purpose timers (tim9 to tim14) doc id 13902 rev 12 413/1096 setting the uif flag (thus no interrupt is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and t...

  • Page 414

    General-purpose timers (tim9 to tim14) rm0008 414/1096 doc id 13902 rev 12 figure 152. Counter timing diagram, internal clock divided by 4 figure 153. Counter timing diagram, internal clock divided by n figure 154. Counter timing diagram, update event when arpe=0 (timx_arr not preloaded) ck_psc 0000...

  • Page 415

    Rm0008 general-purpose timers (tim9 to tim14) doc id 13902 rev 12 415/1096 figure 155. Counter timing diagram, update event when arpe=1 (timx_arr preloaded) 16.4.3 clock selection the counter clock can be provided by the following clock sources: ● internal clock (ck_int) ● external clock mode1 (for ...

  • Page 416

    General-purpose timers (tim9 to tim14) rm0008 416/1096 doc id 13902 rev 12 figure 156. Control circuit in normal mode, internal clock divided by 1 external clock source mode 1( tim9 and tim12) this mode is selected when sms=’111’ in the timx_smcr register. The counter can count at each rising or fal...

  • Page 417

    Rm0008 general-purpose timers (tim9 to tim14) doc id 13902 rev 12 417/1096 figure 158. Control circuit in external clock mode 1 16.4.4 capture/compare channels each capture/compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digit...

  • Page 418

    General-purpose timers (tim9 to tim14) rm0008 418/1096 doc id 13902 rev 12 figure 160. Capture/compare channel 1 main circuit figure 161. Output stage of capture/compare channel (channel 1) the capture/compare block is made of one preload register and one shadow register. Write and read always acces...

  • Page 419

    Rm0008 general-purpose timers (tim9 to tim14) doc id 13902 rev 12 419/1096 cleared by software by writing it to ‘0’ or by reading the captured data stored in the timx_ccrx register. Ccxof is cleared when you write it to ‘0’. The following example shows how to capture the counter value in timx_ccr1 w...

  • Page 420

    General-purpose timers (tim9 to tim14) rm0008 420/1096 doc id 13902 rev 12 1. Select the active input for timx_ccr1: write the cc1s bits to ‘01’ in the timx_ccmr1 register (ti1 selected). 2. Select the active polarity for ti1fp1 (used both for capture in timx_ccr1 and counter clear): program the cc1...

  • Page 421

    Rm0008 general-purpose timers (tim9 to tim14) doc id 13902 rev 12 421/1096 16.4.8 output compare mode this function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare fu...

  • Page 422

    General-purpose timers (tim9 to tim14) rm0008 422/1096 doc id 13902 rev 12 figure 163. Output compare mode, toggle on oc1. 16.4.9 pwm mode pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the timx_arr register and a duty cycle determined by the ...

  • Page 423

    Rm0008 general-purpose timers (tim9 to tim14) doc id 13902 rev 12 423/1096 figure 164. Edge-aligned pwm waveforms (arr=8) counter register ‘ 0 1 2 3 4 5 6 7 8 0 1 ‘ ocxref ccxif ocxref ccxif ocxref ccxif ocxref ccxif ccrx=4 ccrx=8 ccrx>8 ccrx=0

  • Page 424

    General-purpose timers (tim9 to tim14) rm0008 424/1096 doc id 13902 rev 12 16.4.10 one-pulse mode (only for tim9/12) one-pulse mode (opm) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after...

  • Page 425

    Rm0008 general-purpose timers (tim9 to tim14) doc id 13902 rev 12 425/1096 the opm waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). ● the t delay is defined by the value written in the timx_ccr1 register. ● the t pulse is defin...

  • Page 426

    General-purpose timers (tim9 to tim14) rm0008 426/1096 doc id 13902 rev 12 16.4.11 tim9/12 external trigger synchronization the tim9/12 timers can be synchronized with an external trigger in several modes: reset mode, gated mode and trigger mode. Slave mode: reset mode the counter and its prescaler ...

  • Page 427

    Rm0008 general-purpose timers (tim9 to tim14) doc id 13902 rev 12 427/1096 slave mode: gated mode the counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when ti1 input is low: 1. Configure the channel 1 to detect low levels on ti1. ...

  • Page 428

    General-purpose timers (tim9 to tim14) rm0008 428/1096 doc id 13902 rev 12 slave mode: trigger mode the counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on ti2 input: 1. Configure the channel 2 to detect rising...

  • Page 429: 16.5

    Rm0008 general-purpose timers (tim9 to tim14) doc id 13902 rev 12 429/1096 16.5 tim9 and tim12 registers refer to section 1.1 for a list of abbreviations used in register descriptions. 16.5.1 tim9/12 control register 1 (timx_cr1) address offset: 0x00 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4...

  • Page 430

    General-purpose timers (tim9 to tim14) rm0008 430/1096 doc id 13902 rev 12 16.5.2 tim9/12 control register 2 (timx_cr2) address offset: 0x04 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved mms[2:0] reserved rw rw rw bits 15:7 reserved, always read as 0. Bits 6:4 mms: master mode s...

  • Page 431

    Rm0008 general-purpose timers (tim9 to tim14) doc id 13902 rev 12 431/1096 16.5.3 tim9/12 slave mode control register (timx_smcr) address offset: 0x08 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved msm ts[2:0] res. Sms[2:0] rw rw rw rw rw rw rw bits 15:8 reserved. Bit 7 msm:maste...

  • Page 432

    General-purpose timers (tim9 to tim14) rm0008 432/1096 doc id 13902 rev 12 16.5.4 tim9/12 interrupt enable register (timx_dier) address offset: 0x0c reset value: 0x0000 table 89. Timx internal trigger connection slave tim itr0 (ts =’ 000’) itr1 (ts = ‘001’) itr2 (ts = ‘010’) itr3 (ts = ’011’) tim2 t...

  • Page 433

    Rm0008 general-purpose timers (tim9 to tim14) doc id 13902 rev 12 433/1096 16.5.5 tim9/12 status register (timx_sr) address offset: 0x10 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved cc2of cc1of reserved tif reserved cc2if cc1if uif rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 bit 15:11 ...

  • Page 434

    General-purpose timers (tim9 to tim14) rm0008 434/1096 doc id 13902 rev 12 16.5.6 tim9/12 event generation register (timx_egr) address offset: 0x14 reset value: 0x0000 bit 0 uif: update interrupt flag this bit is set by hardware on an update event. It is cleared by software. 0: no update occurred. 1...

  • Page 435

    Rm0008 general-purpose timers (tim9 to tim14) doc id 13902 rev 12 435/1096 16.5.7 tim9/12 capture/compare mode register 1 (timx_ccmr1) address offset: 0x18 reset value: 0x0000 the channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by confi...

  • Page 436

    General-purpose timers (tim9 to tim14) rm0008 436/1096 doc id 13902 rev 12 bits 6:4 oc1m: output compare 1 mode these bits define the behavior of the output reference signal oc1ref from which oc1 and oc1n are derived. Oc1ref is active high whereas the active levels of oc1 and oc1n depend on the cc1p...

  • Page 437

    Rm0008 general-purpose timers (tim9 to tim14) doc id 13902 rev 12 437/1096 input capture mode bits 15:12 ic2f: input capture 2 filter bits 11:10 ic2psc[1:0]:input capture 2 prescaler bits 9:8 cc2s: capture/compare 2 selection this bitfield defines the direction of the channel (input/output) as well ...

  • Page 438

    General-purpose timers (tim9 to tim14) rm0008 438/1096 doc id 13902 rev 12 16.5.8 tim9/12 capture/compare enable register (timx_ccer) address offset: 0x20 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved cc2np res. Cc2p cc2e cc1np res. Cc1p cc1e rw rw rw rw rw rw bits 15:8 reserved...

  • Page 439

    Rm0008 general-purpose timers (tim9 to tim14) doc id 13902 rev 12 439/1096 note: the states of the external i/o pins connected to the standard ocx channels depend on the state of the ocx channel and on the gpio registers. 16.5.9 tim9/12 counter (timx_cnt) address offset: 0x24 reset value: 0x0000 000...

  • Page 440

    General-purpose timers (tim9 to tim14) rm0008 440/1096 doc id 13902 rev 12 16.5.12 tim9/12 capture/compare register 1 (timx_ccr1) address offset: 0x34 reset value: 0x0000 0000 16.5.13 tim9/12 capture/compare register 2 (timx_ccr2) address offset: 0x38 reset value: 0x0000 0000 15 14 13 12 11 10 9 8 7...

  • Page 441

    Rm0008 general-purpose timers (tim9 to tim14) doc id 13902 rev 12 441/1096 16.5.14 tim9/12 register map tim9/12 registers are mapped as 16-bit addressable registers as described in the table below: table 91. Tim9/12 register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19...

  • Page 442: 16.6 Tim10/11/13/14

    General-purpose timers (tim9 to tim14) rm0008 442/1096 doc id 13902 rev 12 16.6 tim10/11/13/14 registers 16.6.1 tim10/11/13/14 control register 1 (timx_cr1) address offset: 0x00 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ckd[1:0] arpe reserved urs udis cen rw rw rw rw rw rw b...

  • Page 443

    Rm0008 general-purpose timers (tim9 to tim14) doc id 13902 rev 12 443/1096 16.6.2 tim10/11/13/14 interrupt enable register (timx_dier) address offset: 0x0c reset value: 0x0000 16.6.3 tim10/11/13/14 status register (timx_sr) address offset: 0x10 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

  • Page 444

    General-purpose timers (tim9 to tim14) rm0008 444/1096 doc id 13902 rev 12 16.6.4 tim10/11/13/14 event generation register (timx_egr) address offset: 0x14 reset value: 0x0000 bit 0 uif: update interrupt flag this bit is set by hardware on an update event. It is cleared by software. 0: no update occu...

  • Page 445

    Rm0008 general-purpose timers (tim9 to tim14) doc id 13902 rev 12 445/1096 16.6.5 tim10/11/13/14 capture/compare mode register 1 (timx_ccmr1) address offset: 0x18 reset value: 0x0000 the channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined b...

  • Page 446

    General-purpose timers (tim9 to tim14) rm0008 446/1096 doc id 13902 rev 12 bit 2 oc1fe: output compare 1 fast enable this bit is used to accelerate the effect of an event on the trigger in input on the cc output. 0: cc1 behaves normally depending on counter and ccr1 values even when the trigger is o...

  • Page 447

    Rm0008 general-purpose timers (tim9 to tim14) doc id 13902 rev 12 447/1096 input capture mode bits 15:8 reserved bits 7:4 ic1f: input capture 1 filter this bit-field defines the frequency used to sample ti1 input and the length of the digital filter applied to ti1. The digital filter is made of an e...

  • Page 448

    General-purpose timers (tim9 to tim14) rm0008 448/1096 doc id 13902 rev 12 16.6.6 tim10/11/13/14 capture/compare enable register (timx_ccer) address offset: 0x20 reset value: 0x0000 note: the state of the external i/o pins connected to the standard ocx channels depends on the ocx channel state and t...

  • Page 449

    Rm0008 general-purpose timers (tim9 to tim14) doc id 13902 rev 12 449/1096 16.6.7 tim10/11/13/14 counter (timx_cnt) address offset: 0x24 reset value: 0x0000 16.6.8 tim10/11/13/14 prescaler (timx_psc) address offset: 0x28 reset value: 0x0000 16.6.9 tim10/11/13/14 auto-reload register (timx_arr) addre...

  • Page 450

    General-purpose timers (tim9 to tim14) rm0008 450/1096 doc id 13902 rev 12 16.6.10 tim10/11/13/14 capture/compare register 1 (timx_ccr1) address offset: 0x34 reset value: 0x0000 16.6.11 tim10/11/13/14 register map timx registers are mapped as 16-bit addressable registers as described in the tables b...

  • Page 451

    Rm0008 general-purpose timers (tim9 to tim14) doc id 13902 rev 12 451/1096 refer to table 3 on page 50 for the register boundary addresses. 0x24 timx_cnt reserved cnt[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x28 timx_psc reserved psc[15:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x2c t...

  • Page 452: Basic Timers (Tim6&tim7)

    Basic timers (tim6&tim7) rm0008 452/1096 doc id 13902 rev 12 17 basic timers (tim6&tim7) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102xx and stm32f103...

  • Page 453: 17.3

    Rm0008 basic timers (tim6&tim7) doc id 13902 rev 12 453/1096 figure 169. Basic timer block diagram 17.3 tim6&tim7 functional description 17.3.1 time-base unit the main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a p...

  • Page 454

    Basic timers (tim6&tim7) rm0008 454/1096 doc id 13902 rev 12 prescaler description the prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the timx_psc register). It can be changed on the fly as ...

  • Page 455

    Rm0008 basic timers (tim6&tim7) doc id 13902 rev 12 455/1096 17.3.2 counting mode the counter counts from 0 to the auto-reload value (contents of the timx_arr register), then restarts from 0 and generates a counter overflow event. An update event can be generate at each counter overflow or by settin...

  • Page 456

    Basic timers (tim6&tim7) rm0008 456/1096 doc id 13902 rev 12 figure 173. Counter timing diagram, internal clock divided by 2 figure 174. Counter timing diagram, internal clock divided by 4 figure 175. Counter timing diagram, internal clock divided by n ck_int 0035 0000 0001 0002 0003 cnt_en timer cl...

  • Page 457

    Rm0008 basic timers (tim6&tim7) doc id 13902 rev 12 457/1096 figure 176. Counter timing diagram, update event when arpe = 0 (timx_arr not preloaded) figure 177. Counter timing diagram, update event when arpe=1 (timx_arr preloaded) 17.3.3 clock source the counter clock is provided by the internal clo...

  • Page 458: 17.4 Tim6&tim7

    Basic timers (tim6&tim7) rm0008 458/1096 doc id 13902 rev 12 figure 178. Control circuit in normal mode, internal clock divided by 1 17.3.4 debug mode when the microcontroller enters the debug mode (cortex-m3 core - halted), the timx counter either continues to work normally or stops, depending on t...

  • Page 459

    Rm0008 basic timers (tim6&tim7) doc id 13902 rev 12 459/1096 bit 2 urs:update request source this bit is set and cleared by software to select the uev event sources. 0: any of the following events generates an update interrupt or dma request if enabled. These events can be: – counter overflow/underf...

  • Page 460

    Basic timers (tim6&tim7) rm0008 460/1096 doc id 13902 rev 12 17.4.2 tim6&tim7 control register 2 (timx_cr2) address offset: 0x04 reset value: 0x0000 17.4.3 tim6&tim7 dma/interrupt enable register (timx_dier) address offset: 0x0c reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved mms[...

  • Page 461

    Rm0008 basic timers (tim6&tim7) doc id 13902 rev 12 461/1096 17.4.4 tim6&tim7 status register (timx_sr) address offset: 0x10 reset value: 0x0000 17.4.5 tim6&tim7 event generation register (timx_egr) address offset: 0x14 reset value: 0x0000 17.4.6 tim6&tim7 counter (timx_cnt) address offset: 0x24 res...

  • Page 462

    Basic timers (tim6&tim7) rm0008 462/1096 doc id 13902 rev 12 17.4.7 tim6&tim7 prescaler (timx_psc) address offset: 0x28 reset value: 0x0000 17.4.8 tim6&tim7 auto-reload register (timx_arr) address offset: 0x2c reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 psc[15:0] rw rw rw rw rw rw rw r...

  • Page 463

    Rm0008 basic timers (tim6&tim7) doc id 13902 rev 12 463/1096 17.4.9 tim6&tim7 register map timx registers are mapped as 16-bit addressable registers as described in the table below: refer to table 3: register boundary addresses for the register boundary addresses. Table 94. Tim6&tim7 register map an...

  • Page 464: 18 Real-Time

    Real-time clock (rtc) rm0008 464/1096 doc id 13902 rev 12 18 real-time clock (rtc) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102xx and stm32f103xx mic...

  • Page 465: 18.2 Rtc

    Rm0008 real-time clock (rtc) doc id 13902 rev 12 465/1096 18.2 rtc main features ● programmable prescaler: division factor up to 2 20 ● 32-bit programmable counter for long-term measurement ● two separate clocks: pclk1 for the apb1 interface and rtc clock (must be at least four times slower than the...

  • Page 466: 18.3

    Real-time clock (rtc) rm0008 466/1096 doc id 13902 rev 12 18.3 rtc functional description 18.3.1 overview the rtc consists of two main units (see figure 179 on page 466 ). The first one (apb1 interface) is used to interface with the apb1 bus. This unit also contains a set of 16-bit registers accessi...

  • Page 467

    Rm0008 real-time clock (rtc) doc id 13902 rev 12 467/1096 18.3.2 resetting rtc registers all system registers are asynchronously reset by a system reset or power reset, except for rtc_prl, rtc_alr, rtc_cnt, and rtc_div. The rtc_prl, rtc_alr, rtc_cnt, and rtc_div registers are reset only by a backup ...

  • Page 468

    Real-time clock (rtc) rm0008 468/1096 doc id 13902 rev 12 18.3.5 rtc flag assertion the rtc second flag (secf) is asserted on each rtc core clock cycle before the update of the rtc counter. The rtc overflow flag (owf) is asserted on the last rtc core clock cycle before the counter reaches 0x0000. Th...

  • Page 469: 18.4 Rtc

    Rm0008 real-time clock (rtc) doc id 13902 rev 12 469/1096 18.4 rtc registers refer to section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 18.4.1 rtc control register high (rtc_crh) addres...

  • Page 470

    Real-time clock (rtc) rm0008 470/1096 doc id 13902 rev 12 18.4.2 rtc control register low (rtc_crl) address offset: 0x04 reset value: 0x0020 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved rtoff cnf rsf owf alrf secf r rw rc_w0 rc_w0 rc_w0 rc_w0 bits 15:6 reserved, forced by hardware to 0. Bit 5 rtof...

  • Page 471

    Rm0008 real-time clock (rtc) doc id 13902 rev 12 471/1096 the functions of the rtc are controlled by this control register. It is not possible to write to the rtc_cr register while the peripheral is completing a previous write operation (flagged by rtoff=0, see section 18.3.4 on page 467 ). Note: 1 ...

  • Page 472

    Real-time clock (rtc) rm0008 472/1096 doc id 13902 rev 12 rtc prescaler load register low (rtc_prll) address offset: 0x0c write only (see section 18.3.4 on page 467 ) reset value: 0x8000 note: if the input clock frequency (f rtcclk ) is 32.768 khz, write 7fffh in this register to get a signal period...

  • Page 473

    Rm0008 real-time clock (rtc) doc id 13902 rev 12 473/1096 18.4.5 rtc counter register (rtc_cnth / rtc_cntl) the rtc core has one 32-bit programmable counter, accessed through two 16-bit registers; the count rate is based on the tr_clk time reference, generated by the prescaler. Rtc_cnt registers kee...

  • Page 474

    Real-time clock (rtc) rm0008 474/1096 doc id 13902 rev 12 18.4.6 rtc alarm register high (rtc_alrh / rtc_alrl) when the programmable counter reaches the 32-bit value stored in the rtc_alr register, an alarm is triggered and the rtc_alarmit interrupt request is generated. This register is write-prote...

  • Page 475

    Rm0008 real-time clock (rtc) doc id 13902 rev 12 475/1096 18.4.7 rtc register map rtc registers are mapped as 16-bit addressable registers as described in the table below: refer to table 3 on page 50 for the register boundary addresses. Table 95. Rtc register map and reset values offset register 31 ...

  • Page 476: Independent Watchdog (Iwdg)

    Independent watchdog (iwdg) rm0008 476/1096 doc id 13902 rev 12 19 independent watchdog (iwdg) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102xx and stm...

  • Page 477

    Rm0008 independent watchdog (iwdg) doc id 13902 rev 12 477/1096 whenever the key value 0xaaaa is written in the iwdg_kr register, the iwdg_rlr value is reloaded in the counter and the watchdog reset is prevented. 19.3.1 hardware watchdog if the “hardware watchdog” feature is enabled through the devi...

  • Page 478

    Independent watchdog (iwdg) rm0008 478/1096 doc id 13902 rev 12 19.3.2 register access protection write access to the iwdg_pr and iwdg_rlr registers is protected. To modify them, you must first write the code 0x5555 in the iwdg_kr register. A write access to this register with a different value will...

  • Page 479: 19.4 Iwdg

    Rm0008 independent watchdog (iwdg) doc id 13902 rev 12 479/1096 19.4 iwdg registers refer to section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 19.4.1 key register (iwdg_kr) address offs...

  • Page 480

    Independent watchdog (iwdg) rm0008 480/1096 doc id 13902 rev 12 19.4.3 reload register (iwdg_rlr) address offset: 0x08 reset value: 0x0000 0fff (reset by standby mode) 19.4.4 status register (iwdg_sr) address offset: 0x0c reset value: 0x0000 0000 (not reset by standby mode) note: if several reload v...

  • Page 481

    Rm0008 independent watchdog (iwdg) doc id 13902 rev 12 481/1096 19.4.5 iwdg register map the following table gives the iwdg register map and reset values. Refer to table 3 on page 50 for the register boundary addresses. Table 97. Iwdg register map and reset values offset register 31 30 29 28 27 26 2...

  • Page 482: Window Watchdog (Wwdg)

    Window watchdog (wwdg) rm0008 482/1096 doc id 13902 rev 12 20 window watchdog (wwdg) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102xx and stm32f103xx m...

  • Page 483

    Rm0008 window watchdog (wwdg) doc id 13902 rev 12 483/1096 figure 183. Watchdog block diagram the application program must write in the wwdg_cr register at regular intervals during normal operation to prevent an mcu reset. This operation must occur only when the counter value is lower than the windo...

  • Page 484: 20.4

    Window watchdog (wwdg) rm0008 484/1096 doc id 13902 rev 12 20.4 how to program the watchdog timeout you can use the formula in figure 184 to calculate the wwdg timeout. Warning: when writing to the wwdg_cr register, always write 1 in the t6 bit to avoid generating an immediate reset. Figure 184. Win...

  • Page 485: 20.6 Wwdg

    Rm0008 window watchdog (wwdg) doc id 13902 rev 12 485/1096 20.6 wwdg registers refer to section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 20.6.1 control register (wwdg_cr) address offse...

  • Page 486

    Window watchdog (wwdg) rm0008 486/1096 doc id 13902 rev 12 20.6.2 configuration register (wwdg_cfr) address offset: 0x04 reset value: 0x7f 20.6.3 status register (wwdg_sr) address offset: 0x08 reset value: 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 ...

  • Page 487

    Rm0008 window watchdog (wwdg) doc id 13902 rev 12 487/1096 20.6.4 wwdg register map the following table gives the wwdg register map and reset values. Refer to table 3 on page 50 for the register boundary addresses. Table 98. Wwdg register map and reset values offset register 31 30 29 28 27 26 25 24 ...

  • Page 488: 21.1 Fsmc

    Flexible static memory controller (fsmc) rm0008 488/1096 doc id 13902 rev 12 21 flexible static memory controller (fsmc) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f...

  • Page 489: 21.2 Block

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 489/1096 ● write enable and byte lane select outputs for use with psram and sram devices ● translation of 32-bit wide ahb transactions into consecutive 16-bit or 8-bit accesses to external 16-bit or 8-bit devices ● a write fifo, 2 w...

  • Page 490: 21.3 Ahb

    Flexible static memory controller (fsmc) rm0008 490/1096 doc id 13902 rev 12 figure 185. Fsmc block diagram 21.3 ahb interface the ahb slave interface enables internal cpus and other bus master peripherals to access the external static memories. Ahb transactions are translated into the external devi...

  • Page 491

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 491/1096 the effect of this ahb error depends on the ahb master which has attempted the r/w access: ● if it is the cortex™-m3 cpu, a hard fault inetrrupt is generated ● if is is a dma, a dma transfer error is generated and the corre...

  • Page 492: 21.4

    Flexible static memory controller (fsmc) rm0008 492/1096 doc id 13902 rev 12 21.4 external device address mapping from the fsmc point of view, the external memory is divided into 4 fixed-size banks of 256 mbytes each (refer to figure 186 ): ● bank 1 used to address up to 4 nor flash or psram memory ...

  • Page 493

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 493/1096 haddr[25:0] contain the external memory address. Since haddr is a byte address whereas the memory is addressed in words, the address actually issued to the memory varies according to the memory data width, as shown in the f...

  • Page 494: 21.5

    Flexible static memory controller (fsmc) rm0008 494/1096 doc id 13902 rev 12 the application software uses the 3 sections to access the nand flash memory: ● to send a command to nand flash memory: the software must write the command value to any memory location in the command section. ● to specify t...

  • Page 495

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 495/1096 21.5.1 external memory interface signals table 104 , table 105 and table 106 list the signals that are typically used to interface nor flash, sram and psram. Note: prefix “n”. Specifies the associated signal as active low. ...

  • Page 496

    Flexible static memory controller (fsmc) rm0008 496/1096 doc id 13902 rev 12 nor-flash memories are addressed in 16-bit words. The maximum capacity is 512 mbit (26 address lines). Psram/sram psram memories are addressed in 16-bit words. The maximum capacity is 512 mbit (26 address lines). 21.5.2 sup...

  • Page 497

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 497/1096 table 107. Nor flash/psram supported memories and transactions device mode r/w ahb data size memory data size allowed/ not allowed comments nor flash (muxed i/os and nonmuxed i/os) asynchronous r 8 16 y asynchronous w 8 16 ...

  • Page 498

    Flexible static memory controller (fsmc) rm0008 498/1096 doc id 13902 rev 12 21.5.3 general timing rules signals synchronization ● all controller output signals change on the rising edge of the internal clock (hclk) ● in synchronous write mode (psram devices), the output data changes on the falling ...

  • Page 499

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 499/1096 21.5.4 nor flash/psram controller asynchronous transactions asynchronous static memories (nor flash, sram) ● signals are synchronized by the internal clock hclk. This clock is not issued to the memory ● the fsmc always samp...

  • Page 500

    Flexible static memory controller (fsmc) rm0008 500/1096 doc id 13902 rev 12 figure 188. Mode1 write accesses the one hclk cycle at the end of the write transaction helps guarantee the address and data hold time after the nwe rising edge. Due to the presence of this one hclk cycle, the datast value ...

  • Page 501

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 501/1096 mode a - sram/psram (cram) oe toggling figure 189. Modea read accesses table 109. Fsmc_btrx bit fields bit number bit name value to set 31-16 0x0000 15-8 datast duration of the second access phase (datast+1 hclk cycles for ...

  • Page 502

    Flexible static memory controller (fsmc) rm0008 502/1096 doc id 13902 rev 12 figure 190. Modea write accesses the differences compared with mode1 are the toggling of noe and the independent read and write timings. Table 110. Fsmc_bcrx bit fields bit number bit name value to set 31-16 0x0000 15 async...

  • Page 503

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 503/1096 table 111. Fsmc_btrx bit fields bit number bit name value to set 31-30 0x0 29-28 accmod 0x0 27-16 0x000 15-8 datast duration of the second access phase (datast+3 hclk cycles) in read. This value cannot be 0 (minimum is 1) 7...

  • Page 504

    Flexible static memory controller (fsmc) rm0008 504/1096 doc id 13902 rev 12 mode 2/b - nor flash figure 191. Mode2/b read accesses figure 192. Mode2 write accesses a[25:0] noe (addset +1) (datast + 1) memory transaction data strobe nex d[15:0] hclk cycles hclk cycles nwe nadv data driven by memory ...

  • Page 505

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 505/1096 figure 193. Modeb write accesses the differences with mode1 are the toggling of nadv and the independent read and write timings when extended mode is set (mode b). Table 113. Fsmc_bcrx bit fields bit number bit name value t...

  • Page 506

    Flexible static memory controller (fsmc) rm0008 506/1096 doc id 13902 rev 12 note: the fsmc_bwtrx register is valid only if extended mode is set (mode b), otherwise all its content is don’t care. Table 114. Fsmc_btrx bit fields bit number bit name value to set 31-30 0x0 29-28 accmod 0x1 if extended ...

  • Page 507

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 507/1096 mode c - nor flash - oe toggling figure 194. Modec read accesses figure 195. Modec write accesses the differences compared with mode1 are the toggling of noe and nadv and the independent read and write timings. A[25:0] noe ...

  • Page 508

    Flexible static memory controller (fsmc) rm0008 508/1096 doc id 13902 rev 12 table 116. Fsmc_bcrx bit fields bit no. Bit name value to set 31-16 0x0000 15 asyncwait set to 1 if the memory supports this feature. Otherwise keep at 0. 14 extmod 0x1 13-10 0x0 9 waitpol meaningful only if bit 15 is 1 8 b...

  • Page 509

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 509/1096 mode d - asynchronous access with extended address figure 196. Moded read accesses moded write accessesthe differences with mode1 are the toggling of nadv, noe that goes on toggling after nadv changes and the independent re...

  • Page 510

    Flexible static memory controller (fsmc) rm0008 510/1096 doc id 13902 rev 12 table 119. Fsmc_bcrx bit fields bit no. Bit name value to set 31-16 0x0000 15 asyncwait set to 1 if the memory supports this feature. Otherwise keep at 0. 14 extmod 0x1 13-10 0x0 9 waitpol meaningful only if bit 15 is 1 8 b...

  • Page 511

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 511/1096 mode muxed - asynchronous access muxed nor flash figure 197. Muxed read accesses 1. The bus turnaround delay (busturn + 1) and the delay between side-by-side transactions overlap, so busturn ≤5 has not impact. Figure 198. M...

  • Page 512

    Flexible static memory controller (fsmc) rm0008 512/1096 doc id 13902 rev 12 wait management in asynchronous accesses if the asynchronous memory asserts a wait signal to advise that it's not yet ready to accept or to provide data, the asyncwait bit has to be set in fsmc_bcrx register. If the wait si...

  • Page 513

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 513/1096 1. Memory asserts the wait signal aligned to noe/nwe which toggles: data_setup phase >= 4 * hclk + max_wait_assertion_time 2. Memory asserts the wait signal aligned to nex (or noe/nwe not toggling) : if max_wait_assertion_t...

  • Page 514

    Flexible static memory controller (fsmc) rm0008 514/1096 doc id 13902 rev 12 figure 200. Asynchronous wait during a write access a[25:0] nwe memory transaction nwait d[15:0] nex data driven by fsmc ai15797 3hclk address phase don’t care data phase 1hclk.

  • Page 515

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 515/1096 21.5.5 synchronous burst transactions the memory clock, clk, is a submultiple of hclk according to the value of parameter clkdiv. Nor flash memories specify a minimum time from nadv assertion to clk high. To meet this const...

  • Page 516

    Flexible static memory controller (fsmc) rm0008 516/1096 doc id 13902 rev 12 during wait-state insertion via the nwait signal, the controller continues to send clock pulses to the memory, keeping the chip select and output enable signals valid, and does not consider the data valid. There are two tim...

  • Page 517

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 517/1096 figure 202. Synchronous multiplexed read mode - nor, psram (cram) 1. Byte lane outputs bl are not shown; for nor access, they are held high, and, for psram (cram) access, they are held low. !Ddr;= data data addr;= -emory (#...

  • Page 518

    Flexible static memory controller (fsmc) rm0008 518/1096 doc id 13902 rev 12 8 bursten 0x1 7 fwprlvl set to protect memory from accidental write access 6 faccen set according to memory support 5-4 mwid as needed 3-2 mtyp 0x1 or 0x2 1 muxen as needed 0 mbken 0x1 table 125. Fsmc_btrx bit fields bit no...

  • Page 519

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 519/1096 figure 203. Synchronous multiplexed write mode - psram (cram) 1. Memory must issue nwait signal one cycle in advance, accordingly waitcfg must be programmed to 0. 2. Byte lane (nbl) outputs are not shown, they are held low ...

  • Page 520

    Flexible static memory controller (fsmc) rm0008 520/1096 doc id 13902 rev 12 table 126. Fsmc_bcrx bit fields bit no. Bit name value to set 31-20 0x0000 19 cburstrw 0x1 18-15 0x0 14 extmod 0x0 13 waiten when high, the first data after latency period is taken as always valid, regardless of the wait fr...

  • Page 521

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 521/1096 21.5.6 nor/psram controller registers the peripheral registers have to be accessed by words (32-bit). Sram/nor-flash chip-select control registers 1..4 (fsmc_bcr1..4) address offset: 0xa000 0000 + 8 * (x – 1), x = 1...4 res...

  • Page 522

    Flexible static memory controller (fsmc) rm0008 522/1096 doc id 13902 rev 12 bit 11 waitcfg: wait timing configuration. For memory access in burst mode, the nwait signal indicates whether the data from the memory are valid or if a wait state must be inserted. This configuration bit determines if nwa...

  • Page 523

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 523/1096 sram/nor-flash chip-select timing registers 1..4 (fsmc_btr1..4) address offset: 0xa000 0000 + 0x04 + 8 * (x – 1), x = 1..4 reset value: 0x0fff ffff this register contains the control information of each memory bank, used fo...

  • Page 524

    Flexible static memory controller (fsmc) rm0008 524/1096 doc id 13902 rev 12 note: psrams (crams) have a variable latency due to internal refresh. Therefore these memories issue the nwait signal during the whole latency phase to prolong the latency as needed. With psrams (crams) the filed datlat mus...

  • Page 525

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 525/1096 sram/nor-flash write timing registers 1..4 (fsmc_bwtr1..4) address offset: 0xa000 0000 + 0x104 + 8 * (x – 1), x = 1...4 reset value: 0x0fff ffff this register contains the control information of each memory bank, used for s...

  • Page 526: 21.6

    Flexible static memory controller (fsmc) rm0008 526/1096 doc id 13902 rev 12 21.6 nand flash/pc card controller the fsmc generates the appropriate signal timings to drive the following types of device: ● nand flash – 8-bit – 16-bit ● 16-bit pc card compatible devices the nand/pc card controller can ...

  • Page 527

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 527/1096 21.6.1 external memory interface signals the following tables list the signals that are typically used to interface nand flash and pc card. Caution: when using a pc card or a compactflash in i/o mode, the nios16 input pin m...

  • Page 528

    Flexible static memory controller (fsmc) rm0008 528/1096 doc id 13902 rev 12 16-bit nand flash there is no theoretical capacity limitation as the fsmc can manage as many address cycles as needed. Table 130. 16-bit nand flash fsmc signal name i/o function a[17] o nand flash address latch enable (ale)...

  • Page 529

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 529/1096 21.6.2 nand flash / pc card supported memories and transactions table 132 below shows the supported devices, access modes and transactions. Transactions not allowed (or not supported) by the nand flash / pc card controller ...

  • Page 530

    Flexible static memory controller (fsmc) rm0008 530/1096 doc id 13902 rev 12 figure 204. Nand/pc card controller timing for common memory access 1. Noe remains high (inactive) during write access. Nwe remains high (inactive) during read access. 2. Ncex goes low as soon as nand access is requested an...

  • Page 531

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 531/1096 the start address for read operations. Using the attribute memory space makes it possible to use a different timing configuration of the fsmc, which can be used to implement the prewait functionality needed by some nand fla...

  • Page 532

    Flexible static memory controller (fsmc) rm0008 532/1096 doc id 13902 rev 12 when this functionality is needed, it can be guaranteed by programming the memhold value to meet the t wb timing, however any cpu read or write access to the nand flash then has the hold delay of (memhold + 1) hclk cycles i...

  • Page 533

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 533/1096 the odd byte on d15-8 and nce1 accesses the even byte on d7-0 if a0=0 or the odd byte on d7-0 if a0=1. The full word is accessed on d15-0 if both nce2 and nce1 are low. The memory space is selected by asserting low noe for ...

  • Page 534

    Flexible static memory controller (fsmc) rm0008 534/1096 doc id 13902 rev 12 the fsmc bank 4 gives access to those 3 memory spaces as described in section 21.4.2: nand/pc card address mapping - table 101: memory mapping and timing registers wait feature the compactflash storage or pc card may reques...

  • Page 535

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 535/1096 21.6.8 nand flash/pc card controller registers the peripheral registers have to be accessed by words (32-bit). Pc card/nand flash control registers 2..4 (fsmc_pcr2..4) address offset: 0xa0000000 + 0x40 + 0x20 * (x – 1), x =...

  • Page 536

    Flexible static memory controller (fsmc) rm0008 536/1096 doc id 13902 rev 12 fifo status and interrupt register 2..4 (fsmc_sr2..4) address offset: 0xa000 0000 + 0x44 + 0x20 * (x-1), x = 2..4 reset value: 0x0000 0040 this register contains information about fifo status and interrupt. The fsmc has a f...

  • Page 537

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 537/1096 common memory space timing register 2..4 (fsmc_pmem2..4) address offset: address: 0xa000 0000 + 0x48 + 0x20 * (x – 1), x = 2..4 reset value: 0xfcfc fcfc each fsmc_pmemx (x = 2..4) read/write register contains the timing inf...

  • Page 538

    Flexible static memory controller (fsmc) rm0008 538/1096 doc id 13902 rev 12 attribute memory space timing registers 2..4 (fsmc_patt2..4) address offset: 0xa000 0000 + 0x4c + 0x20 * (x – 1), x = 2..4 reset value: 0xfcfc fcfc each fsmc_pattx (x = 2..4) read/write register contains the timing informat...

  • Page 539

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 539/1096 i/o space timing register 4 (fsmc_pio4) address offset: 0xa000 0000 + 0xb0 reset value: 0xfcfcfcfc the fsmc_pio4 read/write registers contain the timing information used to gain access to the i/o space of the 16-bit pc card...

  • Page 540

    Flexible static memory controller (fsmc) rm0008 540/1096 doc id 13902 rev 12 ecc result registers 2/3 (fsmc_eccr2/3) address offset: 0xa000 0000 + 0x54 + 0x20 * (x – 1), x = 2 or 3 reset value: 0x0000 0000 these registers contain the current error correction code value computed by the ecc computatio...

  • Page 541

    Rm0008 flexible static memory controller (fsmc) doc id 13902 rev 12 541/1096 21.6.9 fsmc register map the following table summarizes the fsmc registers. Table 135. Fsmc register map offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0xa000 0000 fsmc...

  • Page 542

    Flexible static memory controller (fsmc) rm0008 542/1096 doc id 13902 rev 12 refer to table 3 on page 50 for the register boundary addresses. 0xa000 00a8 fsmc_pmem4 memhizx memholdx memwaitx memsetx 0xa000 006c fsmc_patt2 atthizx attholdx attwaitx attsetx 0xa000 008c fsmc_patt3 atthizx attholdx attw...

  • Page 543: 22.1

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 543/1096 22 secure digital input/output interface (sdio) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices ar...

  • Page 544: 22.2

    Secure digital input/output interface (sdio) rm0008 544/1096 doc id 13902 rev 12 interface using a protocol that utilizes the existing mmc access primitives. The interface electrical and signaling definition is as defined in the mmc reference. The multimediacard/sd bus connects cards to the controll...

  • Page 545

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 545/1096 figure 208. Sdio (multiple) block write operation note: the sdio will not send any data as long as the busy signal is asserted (sdio_d0 pulled low). Figure 209. Sdio sequential read operation figure 210. Sdio sequential...

  • Page 546: 22.3

    Secure digital input/output interface (sdio) rm0008 546/1096 doc id 13902 rev 12 22.3 sdio functional description the sdio consists of two parts: ● the sdio adapter block provides all functions specific to the mmc/sd/sd i/o card such as the clock generation unit, command and data transfer. ● the ahb...

  • Page 547

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 547/1096 22.3.1 sdio adapter figure 212 shows a simplified block diagram of an sdio adapter. Figure 212. Sdio adapter the sdio adapter is a multimedia/secure digital memory card bus master that provides an interface to a multime...

  • Page 548

    Secure digital input/output interface (sdio) rm0008 548/1096 doc id 13902 rev 12 control unit the control unit contains the power management functions and the clock divider for the memory card clock. There are three power phases: ● power-off ● power-up ● power-on figure 213. Control unit the control...

  • Page 549

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 549/1096 figure 214. Sdio adapter command path ● command path state machine (cpsm) – when the command register is written to and the enable bit is set, command transfer starts. When the command has been sent, the command path st...

  • Page 550

    Secure digital input/output interface (sdio) rm0008 550/1096 doc id 13902 rev 12 figure 215. Command path state machine (cpsm) when the wait state is entered, the command timer starts running. If the timeout is reached before the cpsm moves to the receive state, the timeout flag is set and the idle ...

  • Page 551

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 551/1096 figure 216. Sdio command transfer ● command format – command: a command is a token that starts an operation. Command are sent from the host either to a single card (addressed command) or to all connected cards (broadcas...

  • Page 552

    Secure digital input/output interface (sdio) rm0008 552/1096 doc id 13902 rev 12 the command register contains the command index (six bits sent to a card) and the command type. These determine whether the command requires a response, and whether the response is 48 or 136 bits long (see section 22.9....

  • Page 553

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 553/1096 data path the data path subunit transfers data to and from cards. Figure 217 shows a block diagram of the data path. Figure 217. Data path the card databus width can be programmed using the clock control register. If th...

  • Page 554

    Secure digital input/output interface (sdio) rm0008 554/1096 doc id 13902 rev 12 figure 218. Data path state machine (dpsm) ● idle: the data path is inactive, and the sdio_d[7:0] outputs are in hi-z. When the data control register is written and the enable bit is set, the dpsm loads the data counter...

  • Page 555

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 555/1096 note: the dpsm remains in the wait_s state for at least two clock periods to meet the n wr timing requirements, where n wr is the number of clock cycles between the reception of the card response and the start of the da...

  • Page 556

    Secure digital input/output interface (sdio) rm0008 556/1096 doc id 13902 rev 12 depending on the txact and rxact flags, the fifo can be disabled, transmit enabled, or receive enabled. Txact and rxact are driven by the data path subunit and are mutually exclusive: – the transmit fifo refers to the t...

  • Page 557

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 557/1096 22.3.2 sdio ahb interface the ahb interface generates the interrupt and dma requests, and accesses the sdio adapter registers and the data fifo. It consists of a data path, register decoder, and interrupt/dma logic. Sdi...

  • Page 558: 22.4

    Secure digital input/output interface (sdio) rm0008 558/1096 doc id 13902 rev 12 5. Send cmd24 (write_block) as follows: a) program the sdio data length register (sdio data timer register should be already programmed before the card identification process) b) program the sdio argument register with ...

  • Page 559

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 559/1096 by using these commands without including the voltage range as the operand, the sdio card host can query each card and determine the common voltage range before placing out- of-range cards in the inactive state. This qu...

  • Page 560

    Secure digital input/output interface (sdio) rm0008 560/1096 doc id 13902 rev 12 1. The bus is activated. 2. The sdio card host sends io_send_op_cond (cmd5). 3. The cards respond with the contents of their operation condition registers. 4. The incompatible cards are set to the inactive state. 5. The...

  • Page 561

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 561/1096 the host can abort reading at any time, within a multiple block operation, regardless of its type. Transaction abort is done by sending the stop transmission command. If the card detects an error (for example, out of ra...

  • Page 562

    Secure digital input/output interface (sdio) rm0008 562/1096 doc id 13902 rev 12 stream read (multimediacard only) read_dat_until_stop (cmd11) controls a stream-oriented data transfer. This command instructs the card to send its data, starting at a specified address, until the sdio card host sends s...

  • Page 563

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 563/1096 the card indicates that an erase is in progress by holding sdio_d low. The actual erase time may be quite long, and the host may issue cmd7 to deselect the card. 22.4.9 wide bus selection or deselection wide bus (4-bit ...

  • Page 564

    Secure digital input/output interface (sdio) rm0008 564/1096 doc id 13902 rev 12 the card must be selected before using it. The card lock/unlock commands have the structure and bus transaction types of a regular single-block write command. The transferred data block includes all of the required info...

  • Page 565

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 565/1096 resetting the password 1. Select a card (select/deselect_card, cmd7), if none is already selected. 2. Define the block length (set_blocklen, cmd16) to send, given by the 8-bit card lock/unlock mode, the 8-bit pwd_len, a...

  • Page 566

    Secure digital input/output interface (sdio) rm0008 566/1096 doc id 13902 rev 12 the unlocking function is only valid for the current power session. When the pwd field is not clear, the card is locked automatically on the next power-up. An attempt to unlock an unlocked card fails and the lock_unlock...

  • Page 567

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 567/1096 table 144. Card status bits identifier type value description clear condition 31 address_ out_of_range e r x ’0’= no error ’1’= error the command address argument was out of the allowed range for this card. A multiple b...

  • Page 568

    Secure digital input/output interface (sdio) rm0008 568/1096 doc id 13902 rev 12 19 error e x ’0’= no error ’1’= error (undefined by the standard) a generic card error related to the (and detected during) execution of the last host command (e.G. Read or write failures). C 18 reserved 17 reserved 16 ...

  • Page 569

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 569/1096 22.4.12 sd status register the sd status contains status bits that are related to the sd memory card proprietary features and may be used for future application-specific usage. The size of the sd status is one data bloc...

  • Page 570

    Secure digital input/output interface (sdio) rm0008 570/1096 doc id 13902 rev 12 size_of_protected_area setting this field differs between standard- and high-capacity cards. In the case of a standard-capacity card, the capacity of protected area is calculated as follows: protected area = size_of_pro...

  • Page 571

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 571/1096 performance_move this 8-bit field indicates pm (performance move) and the value can be set by 1 [mb/sec] steps. If the card does not move used rus (recording units), pm should be considered as infinity. Setting the fiel...

  • Page 572

    Secure digital input/output interface (sdio) rm0008 572/1096 doc id 13902 rev 12 the maximum au size, which depends on the card capacity, is defined in table 149 . The card can be set to any au size between ru size and maximum au size. Erase_size this 16-bit field indicates n erase . When n erase nu...

  • Page 573

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 573/1096 erase_offset this 2-bit field indicates t offset and one of four values can be selected. This field is meaningless if the erase_size and erase_timeout fields are set to 0. 22.4.13 sd i/o mode sd i/o interrupts to allow ...

  • Page 574

    Secure digital input/output interface (sdio) rm0008 574/1096 doc id 13902 rev 12 suspend/resume operation on the mmc/sd bus, the mmc/sd module performs the following steps: 1. Determines the function currently using the sdio_d [3:0] line(s) 2. Requests the lower-priority or slower transaction to sus...

  • Page 575

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 575/1096 the bus transaction for a gen_cmd is the same as the single-block read or write commands (write_block, cmd24 or read_single_block,cmd17). In this case, the argument denotes the direction of the data transfer rather than...

  • Page 576

    Secure digital input/output interface (sdio) rm0008 576/1096 doc id 13902 rev 12 table 154. Block-oriented write protection commands cmd index type argument response format abbreviation description cmd28 ac [31:0] data address r1b set_write_prot if the card has write protection features, this comman...

  • Page 577: 22.5 Response

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 577/1096 22.5 response formats all responses are sent via the mccmd command line sdio_cmd. The response transmission always starts with the left bit of the bit string corresponding to the response code word. The code length depe...

  • Page 578

    Secure digital input/output interface (sdio) rm0008 578/1096 doc id 13902 rev 12 22.5.1 r1 (normal response command) code length = 48 bits. The 45:40 bits indicate the index of the command to be responded to, this value being interpreted as a binary-coded number (between 0 and 63). The status of the...

  • Page 579

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 579/1096 22.5.5 r4 (fast i/o) code length: 48 bits. The argument field contains the rca of the addressed card, the register address to be read out or written to, and its content. 22.5.6 r4b for sd i/o only: an sdio card receivin...

  • Page 580

    Secure digital input/output interface (sdio) rm0008 580/1096 doc id 13902 rev 12 once an sd i/o card has received a cmd5, the i/o portion of that card is enabled to respond normally to all further commands. This i/o enable of the function within the i/o card will remain set until a reset, power cycl...

  • Page 581: 22.6

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 581/1096 the card [23:8] status bits are changed when cmd3 is sent to an i/o-only card. In this case, the 16 bits of response are the sd i/o-only values: ● bit [15] com_crc_error ● bit [14] illegal_command ● bit [13] error ● bit...

  • Page 582: 22.7 Ce-Ata

    Secure digital input/output interface (sdio) rm0008 582/1096 doc id 13902 rev 12 as sdio_ck is stopped, any command can be issued to the card. During a read/wait interval, the sdio can detect sdio interrupts on sdio_d1. 22.6.3 sdio suspend/resume operation while sending data to the card, the sdio ca...

  • Page 583: 22.8

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 583/1096 when ‘0’ is received on the cmd line, the cpsm enters the idle state. No new command can be sent for 7 bit cycles. Then, for the last 5 cycles (out of the 7) the cmd line is driven to ‘1’ in push-pull mode. 22.7.3 ce-at...

  • Page 584

    Secure digital input/output interface (sdio) rm0008 584/1096 doc id 13902 rev 12 22.9.1 sdio power control register (sdio_power) address offset: 0x00 reset value: 0x0000 0000 note: at least seven hclk clock periods are needed between two write accesses to this register. 22.9.2 sdi clock control regi...

  • Page 585

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 585/1096 note: 1 while the sd/sdio card or multimediacard is in identification mode, the sdio_ck frequency must be less than 400 khz. 2 the clock frequency can be changed to the maximum card bus frequency when relative card addr...

  • Page 586

    Secure digital input/output interface (sdio) rm0008 586/1096 doc id 13902 rev 12 22.9.4 sdio command register (sdio_cmd) address offset: 0x0c reset value: 0x0000 0000 the sdio_cmd register contains the command index and command type bits. The command index is sent to a card as part of a command mess...

  • Page 587

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 587/1096 argument can vary according to the type of response: the software will distinguish the type of response according to the sent command. Ce-ata devices send only short responses. 22.9.5 sdio command response register (sdi...

  • Page 588

    Secure digital input/output interface (sdio) rm0008 588/1096 doc id 13902 rev 12 22.9.7 sdio data timer register (sdio_dtimer) address offset: 0x24 reset value: 0x0000 0000 the sdio_dtimer register contains the data timeout period, in card bus clock periods. A counter loads the value from the sdio_d...

  • Page 589

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 589/1096 22.9.9 sdio data control register (sdio_dctrl) address offset: 0x2c reset value: 0x0000 0000 the sdio_dctrl register control the data path state machine (dpsm). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1...

  • Page 590

    Secure digital input/output interface (sdio) rm0008 590/1096 doc id 13902 rev 12 note: at least seven hclk clock periods are needed between two write accesses to this register. 22.9.10 sdio data counter register (sdio_dcount) address offset: 0x30 reset value: 0x0000 0000 the sdio_dcount register loa...

  • Page 591

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 591/1096 22.9.11 sdio status register (sdio_sta) address offset: 0x34 reset value: 0x0000 0000 the sdio_sta register is a read-only register. It contains two types of flag: ● static flags (bits [23:22,10:0]): these bits remain a...

  • Page 592

    Secure digital input/output interface (sdio) rm0008 592/1096 doc id 13902 rev 12 22.9.12 sdio interrupt clear register (sdio_icr) address offset: 0x38 reset value: 0x0000 0000 the sdio_icr register is a write-only register. Writing a bit with 1b clears the corresponding bit in the sdio_sta status re...

  • Page 593

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 593/1096 bit 7 cmdsentc: cmdsent flag clear bit set by software to clear the cmdsent flag. 0: cmdsent not cleared 1: cmdsent cleared bit 6 cmdrendc: cmdrend flag clear bit set by software to clear the cmdrend flag. 0: cmdrend no...

  • Page 594

    Secure digital input/output interface (sdio) rm0008 594/1096 doc id 13902 rev 12 22.9.13 sdio mask register (sdio_mask) address offset: 0x3c reset value: 0x0000 0000 the interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1b. 31 30 ...

  • Page 595

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 595/1096 bit 16 txfifofie: tx fifo full interrupt enable set and cleared by software to enable/disable interrupt caused by tx fifo full. 0: tx fifo full interrupt disabled 1: tx fifo full interrupt enabled bit 15 rxfifohfie: rx ...

  • Page 596

    Secure digital input/output interface (sdio) rm0008 596/1096 doc id 13902 rev 12 22.9.14 sdio fifo counter register (sdio_fifocnt) address offset: 0x48 reset value: 0x0000 0000 the sdio_fifocnt register contains the remaining number of words to be written to or read from the fifo. The fifo counter l...

  • Page 597

    Rm0008 secure digital input/output interface (sdio) doc id 13902 rev 12 597/1096 22.9.15 sdio data fifo register (sdio_fifo) address offset: 0x80 reset value: 0x0000 0000 the receive and transmit fifos can be read or written as 32-bit wide registers. The fifos contain 32 entries on 32 sequential add...

  • Page 598

    Secure digital input/output interface (sdio) rm0008 598/1096 doc id 13902 rev 12 refer to table 3 on page 50 for the register boundary addresses. 0x38 sdio_icr reser v ed cea t a e ndc sdi o it c reser v ed d b ckendc stbi terrc d a t a endc cmd s entc cmdrendc rxo v errc txunderrc dtime o utc ctime...

  • Page 599: 23.1 Usb

    Rm0008 universal serial bus full-speed device interface (usb) doc id 13902 rev 12 599/1096 23 universal serial bus full-speed device interface (usb) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Mediu...

  • Page 600

    Universal serial bus full-speed device interface (usb) rm0008 600/1096 doc id 13902 rev 12 figure 219. Usb peripheral block diagram the usb peripheral provides an usb compliant connection between the host pc and the function implemented by the microcontroller. Data transfer between the host pc and t...

  • Page 601

    Rm0008 universal serial bus full-speed device interface (usb) doc id 13902 rev 12 601/1096 proper handshake packet over the usb is generated or expected according to the direction of the transfer. At the end of the transaction, an endpoint-specific interrupt is generated, reading status registers an...

  • Page 602: 23.4 Programming

    Universal serial bus full-speed device interface (usb) rm0008 602/1096 doc id 13902 rev 12 ● control registers: these are the registers containing information about the status of the whole usb peripheral and used to force some usb events, such as resume and power-down. ● interrupt registers: these c...

  • Page 603

    Rm0008 universal serial bus full-speed device interface (usb) doc id 13902 rev 12 603/1096 23.4.2 system and power-on reset upon system and power-on reset, the first operation the application software should perform is to provide all required clock signals to the usb peripheral and subsequently de-a...

  • Page 604

    Universal serial bus full-speed device interface (usb) rm0008 604/1096 doc id 13902 rev 12 clock is fixed by the requirements of the usb standard at 48 mhz, and this can be different from the clock used for the interface to the apb1 bus. Different clock configurations are possible where the apb1 clo...

  • Page 605

    Rm0008 universal serial bus full-speed device interface (usb) doc id 13902 rev 12 605/1096 each packet buffer is used either during reception or transmission starting from the bottom. The usb peripheral will never change the contents of memory locations adjacent to the allocated memory buffers; if a...

  • Page 606

    Universal serial bus full-speed device interface (usb) rm0008 606/1096 doc id 13902 rev 12 condition: the usb host will retry the transaction until it succeeds. It is mandatory to execute the sequence of operations in the above mentioned order to avoid losing the notification of a second in transact...

  • Page 607

    Rm0008 universal serial bus full-speed device interface (usb) doc id 13902 rev 12 607/1096 stat_rx bits are equal to ‘10 (nak), any out request addressed to that endpoint is naked, indicating a flow control condition: the usb host will retry the transaction until it succeeds. It is mandatory to exec...

  • Page 608

    Universal serial bus full-speed device interface (usb) rm0008 608/1096 doc id 13902 rev 12 23.4.3 double-buffered endpoints all different endpoint types defined by the usb standard represent different traffic models, and describe the typical requirements of different kind of data transfer operations...

  • Page 609

    Rm0008 universal serial bus full-speed device interface (usb) doc id 13902 rev 12 609/1096 the memory buffer which is currently being used by the usb peripheral is defined by dtog buffer flag, while the buffer currently in use by application software is identified by sw_buf buffer flag. The relation...

  • Page 610

    Universal serial bus full-speed device interface (usb) rm0008 610/1096 doc id 13902 rev 12 dbl_buf setting, stat bit pair is not affected by the transaction termination and its value remains ‘11 (valid). However, as the token packet of a new transaction is received, the actual endpoint status will b...

  • Page 611

    Rm0008 universal serial bus full-speed device interface (usb) doc id 13902 rev 12 611/1096 as it happens with double-buffered bulk endpoints, the usb_epnr registers used to implement isochronous endpoints are forced to be used as unidirectional ones. In case it is required to have isochronous endpoi...

  • Page 612

    Universal serial bus full-speed device interface (usb) rm0008 612/1096 doc id 13902 rev 12 the actual procedure used to suspend the usb peripheral is device dependent since according to the device composition, different actions may be required to reduce the total consumption. A brief description of ...

  • Page 613: 23.5 Usb

    Rm0008 universal serial bus full-speed device interface (usb) doc id 13902 rev 12 613/1096 a device may require to exit from suspend mode as an answer to particular events not directly related to the usb protocol (e.G. A mouse movement wakes up the whole system). In this case, the resume sequence ca...

  • Page 614

    Universal serial bus full-speed device interface (usb) rm0008 614/1096 doc id 13902 rev 12 23.5.1 common registers these registers affect the general behavior of the usb peripheral defining operating mode, interrupt handling, device address and giving access to the current frame number updated by th...

  • Page 615

    Rm0008 universal serial bus full-speed device interface (usb) doc id 13902 rev 12 615/1096 bit 4 resume: resume request the microcontroller can set this bit to send a resume signal to the host. It must be activated, according to usb specifications, for no less than 1ms and no more than 15ms after wh...

  • Page 616

    Universal serial bus full-speed device interface (usb) rm0008 616/1096 doc id 13902 rev 12 usb interrupt status register (usb_istr) address offset: 0x44 reset value: 0x0000 0000 this register contains the status of all the interrupt sources allowing application software to determine, which events ca...

  • Page 617

    Rm0008 universal serial bus full-speed device interface (usb) doc id 13902 rev 12 617/1096 the following describes each bit in detail: bit 15 ctr: correct transfer this bit is set by the hardware to indicate that an endpoint has successfully completed a transaction; using dir and ep_id bits software...

  • Page 618

    Universal serial bus full-speed device interface (usb) rm0008 618/1096 doc id 13902 rev 12 bit 10 reset: usb reset request set when the usb peripheral detects an active usb reset signal at its inputs. The usb peripheral, in response to a reset, just resets its internal protocol state machine, genera...

  • Page 619

    Rm0008 universal serial bus full-speed device interface (usb) doc id 13902 rev 12 619/1096 usb frame number register (usb_fnr) address offset: 0x48 reset value: 0x0xxx where x is undefined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rxdp rxdm lck lsof[1:0] fn[10:0] r r r r r r r r r r r r r r r r bit 15 r...

  • Page 620

    Universal serial bus full-speed device interface (usb) rm0008 620/1096 doc id 13902 rev 12 usb device address (usb_daddr) address offset: 0x4c reset value: 0x0000 buffer table address (usb_btable) address offset: 0x50 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ef add6 add5 ad...

  • Page 621

    Rm0008 universal serial bus full-speed device interface (usb) doc id 13902 rev 12 621/1096 23.5.2 endpoint-specific registers the number of these registers varies according to the number of endpoints that the usb peripheral is designed to handle. The usb peripheral supports up to 8 bidirectional end...

  • Page 622

    Universal serial bus full-speed device interface (usb) rm0008 622/1096 doc id 13902 rev 12 bit 15 ctr_rx: correct transfer for reception this bit is set by the hardware when an out/setup transaction is successfully completed on this endpoint; the software can only clear this bit. If the ctrm bit in ...

  • Page 623

    Rm0008 universal serial bus full-speed device interface (usb) doc id 13902 rev 12 623/1096 bits 10:9 ep_type[1:0]: endpoint type these bits configure the behavior of this endpoint as described in table 173: endpoint type encoding on page 624 . Endpoint 0 must always be a control endpoint and each us...

  • Page 624

    Universal serial bus full-speed device interface (usb) rm0008 624/1096 doc id 13902 rev 12 bits 5:4 stat_tx [1:0]: status bits, for transmission transfers these bits contain the information about the endpoint status, listed in table 175 . These bits can be toggled by the software to initialize their...

  • Page 625

    Rm0008 universal serial bus full-speed device interface (usb) doc id 13902 rev 12 625/1096 23.5.3 buffer descriptor table although the buffer descriptor table is located inside the packet buffer memory, its entries can be considered as additional registers used to configure the location and size of ...

  • Page 626

    Universal serial bus full-speed device interface (usb) rm0008 626/1096 doc id 13902 rev 12 transmission byte count n (usb_countn_tx) address offset: [usb_btable] + n*16 + 4 usb local address: [usb_btable] + n*8 + 2 note: double-buffered and isochronous in endpoints have two usb_countn_tx registers: ...

  • Page 627

    Rm0008 universal serial bus full-speed device interface (usb) doc id 13902 rev 12 627/1096 reception byte count n (usb_countn_rx) address offset: [usb_btable] + n*16 + 12 usb local address: [usb_btable] + n*8 + 6 this table location is used to store two different values, both required during packet ...

  • Page 628

    Universal serial bus full-speed device interface (usb) rm0008 628/1096 doc id 13902 rev 12 23.5.4 usb register map the table below provides the usb register map and reset values. Table 176. Definition of allocated buffer memory value of num_block[4:0] memory allocated when bl_size=0 memory allocated...

  • Page 629

    Rm0008 universal serial bus full-speed device interface (usb) doc id 13902 rev 12 629/1096 note: refer to table 3 on page 50 for the register boundary addresses. 0x18 usb_ep6r reserved ctr_rx dt og_ rx stat_ rx [1:0] se tu p ep type [1:0] ep _ k in d ct r _ t x dt og_tx stat_ tx [1:0] ea[3:0] reset ...

  • Page 630: 24.1 Bxcan

    Controller area network (bxcan) rm0008 630/1096 doc id 13902 rev 12 24 controller area network (bxcan) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102xx...

  • Page 631: 24.3

    Rm0008 controller area network (bxcan) doc id 13902 rev 12 631/1096 time-triggered communication option ● disable automatic retransmission mode ● 16-bit free running timer ● time stamp sent in last two data bytes management ● maskable interrupts ● software-efficient mailbox mapping at a unique addre...

  • Page 632

    Controller area network (bxcan) rm0008 632/1096 doc id 13902 rev 12 24.3.1 can 2.0b active core the bxcan module handles the transmission and the reception of can messages fully autonomously. Standard identifiers (11-bit) and extended identifiers (29-bit) are fully supported by hardware. 24.3.2 cont...

  • Page 633: 24.4

    Rm0008 controller area network (bxcan) doc id 13902 rev 12 633/1096 figure 222. Dual can block diagram (connectivity devices) 24.4 bxcan operating modes bxcan has three main operating modes: initialization, normal and sleep. After a hardware reset, bxcan is in sleep mode to reduce power consumption ...

  • Page 634

    Controller area network (bxcan) rm0008 634/1096 doc id 13902 rev 12 to synchronize, bxcan waits until the can bus is idle, this means 11 consecutive recessive bits have been monitored on canrx. 24.4.1 initialization mode the software initialization can be done while the hardware is in initialization...

  • Page 635: 24.5 Test

    Rm0008 controller area network (bxcan) doc id 13902 rev 12 635/1096 on can bus activity detection, hardware automatically performs the wakeup sequence by clearing the sleep bit if the awum bit in the can_mcr register is set. If the awum bit is cleared, software has to clear the sleep bit when a wake...

  • Page 636

    Controller area network (bxcan) rm0008 636/1096 doc id 13902 rev 12 figure 224. Bxcan in silent mode 24.5.2 loop back mode the bxcan can be set in loop back mode by setting the lbkm bit in the can_btr register. In loop back mode, the bxcan treats its own transmitted messages as received messages and...

  • Page 637: 24.6

    Rm0008 controller area network (bxcan) doc id 13902 rev 12 637/1096 figure 226. Bxcan in combined mode 24.6 stm32f10xxx in debug mode when the microcontroller enters the debug mode (cortex-m3 core halted), the bxcan continues to work normally or stops, depending on: ● the dbg_can1_stop bit for can1 ...

  • Page 638

    Controller area network (bxcan) rm0008 638/1096 doc id 13902 rev 12 the transmit mailboxes can be configured as a transmit fifo by setting the txfp bit in the can_mcr register. In this mode the priority order is given by the transmit request order. This mode is very useful for segmented transmission...

  • Page 639

    Rm0008 controller area network (bxcan) doc id 13902 rev 12 639/1096 24.7.2 time triggered communication mode in this mode, the internal counter of the can hardware is activated and used to generate the time stamp value stored in the can_rdtxr/can_tdtxr registers, respectively (for rx and tx mailboxe...

  • Page 640

    Controller area network (bxcan) rm0008 640/1096 doc id 13902 rev 12 fifo management starting from the empty state, the first valid message received is stored in the fifo which becomes pending_1. The hardware signals the event setting the fmp[1:0] bits in the can_rfr register to the value 01b. The me...

  • Page 641

    Rm0008 controller area network (bxcan) doc id 13902 rev 12 641/1096 resources which would be otherwise needed to perform filtering by software. Each filter bankx consists of two 32-bit registers, can_fxr0 and can_fxr1. Scalable width to optimize and adapt the filters to the application needs, each f...

  • Page 642

    Controller area network (bxcan) rm0008 642/1096 doc id 13902 rev 12 figure 229. Filter bank scale configuration - register organization filter match index once a message has been received in the fifo it is available to the application. Typically, application data is copied into sram locations. To co...

  • Page 643

    Rm0008 controller area network (bxcan) doc id 13902 rev 12 643/1096 figure 230. Example of filter numbering filter priority rules depending on the filter combination it may occur that an identifier passes successfully through several filters. In this case the filter match value stored in the receive...

  • Page 644

    Controller area network (bxcan) rm0008 644/1096 doc id 13902 rev 12 figure 231. Filtering mechanism - example the example above shows the filtering principle of the bxcan. On reception of a message, the identifier is compared first with the filters configured in identifier list mode. If there is a m...

  • Page 645

    Rm0008 controller area network (bxcan) doc id 13902 rev 12 645/1096 receive mailbox when a message has been received, it is available to the software in the fifo output mailbox. Once the software has handled the message (e.G. Read it) the software must release the fifo output mailbox by means of the...

  • Page 646

    Controller area network (bxcan) rm0008 646/1096 doc id 13902 rev 12 24.7.6 error management the error management as described in the can protocol is handled entirely by hardware using a transmit error counter (tec value, in can_esr register) and a receive error counter (rec value, in the can_esr reg...

  • Page 647

    Rm0008 controller area network (bxcan) doc id 13902 rev 12 647/1096 a valid edge is defined as the first transition in a bit time from dominant to recessive bus level provided the controller itself does not send a recessive bit. If a valid edge is detected in bs1 instead of sync_seg, bs1 is extended...

  • Page 648: 24.8 Bxcan

    Controller area network (bxcan) rm0008 648/1096 doc id 13902 rev 12 figure 234. Can frames 24.8 bxcan interrupts four interrupt vectors are dedicated to bxcan. Each interrupt source can be independently enabled or disabled by means of the can interrupt enable register (can_ier). Data frame or remote...

  • Page 649

    Rm0008 controller area network (bxcan) doc id 13902 rev 12 649/1096 figure 235. Event flags and interrupt generation ● the transmit interrupt can be generated by the following events: – transmit mailbox 0 becomes empty, rqcp0 bit in the can_tsr register set. – transmit mailbox 1 becomes empty, rqcp1...

  • Page 650: 24.9 Can

    Controller area network (bxcan) rm0008 650/1096 doc id 13902 rev 12 ● the error and status change interrupt can be generated by the following events: – error condition, for more details on error conditions please refer to the can error status register (can_esr). – wakeup condition, sof monitored on ...

  • Page 651

    Rm0008 controller area network (bxcan) doc id 13902 rev 12 651/1096 bit 15 reset: bxcan software master reset 0: normal operation. 1: force a master reset of the bxcan -> sleep mode activated after reset (fmp bits and can_mcr register are initialized to the reset values). This bit is automatically r...

  • Page 652

    Controller area network (bxcan) rm0008 652/1096 doc id 13902 rev 12 can master status register (can_msr) address offset: 0x04 reset value: 0x0000 0c02 bit 0 inrq : initialization request the software clears this bit to switch the hardware into normal mode. Once 11 consecutive recessive bits have bee...

  • Page 653

    Rm0008 controller area network (bxcan) doc id 13902 rev 12 653/1096 can transmit status register (can_tsr) address offset: 0x08 reset value: 0x1c00 0000 bit 2 erri : error interrupt this bit is set by hardware when a bit of the can_esr has been set on error detection and the corresponding interrupt ...

  • Page 654

    Controller area network (bxcan) rm0008 654/1096 doc id 13902 rev 12 bit 27 tme1 : transmit mailbox 1 empty this bit is set by hardware when no transmit request is pending for mailbox 1. Bit 26 tme0 : transmit mailbox 0 empty this bit is set by hardware when no transmit request is pending for mailbox...

  • Page 655

    Rm0008 controller area network (bxcan) doc id 13902 rev 12 655/1096 can receive fifo 0 register (can_rf0r) address offset: 0x0c reset value: 0x00 bit 8 rqcp1 : request completed mailbox1 set by hardware when the last request (transmit or abort) has been performed. Cleared by software writing a “1” o...

  • Page 656

    Controller area network (bxcan) rm0008 656/1096 doc id 13902 rev 12 can receive fifo 1 register (can_rf1r) address offset: 0x10 reset value: 0x00 bit 4 fovr0 : fifo 0 overrun this bit is set by hardware when a new message has been received and passed the filter while the fifo was full. This bit is c...

  • Page 657

    Rm0008 controller area network (bxcan) doc id 13902 rev 12 657/1096 can interrupt enable register (can_ier) address offset: 0x14 reset value: 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved slkie wkuie rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 errie reserved lec ie bof ie epv ie ewg ...

  • Page 658

    Controller area network (bxcan) rm0008 658/1096 doc id 13902 rev 12 can error status register (can_esr) address offset: 0x18 reset value: 0x00 bit 4 fmpie1 : fifo message pending interrupt enable 0: no interrupt generated when state of fmp[1:0] bits are not 00b. 1: interrupt generated when state of ...

  • Page 659

    Rm0008 controller area network (bxcan) doc id 13902 rev 12 659/1096 can bit timing register (can_btr) address offset: 0x1c reset value: 0x0123 0000 note: this register can only be accessed by the software when the can hardware is in initialization mode. Bits 6:4 lec[2:0] : last error code this field...

  • Page 660

    Controller area network (bxcan) rm0008 660/1096 doc id 13902 rev 12 24.9.3 can mailbox registers this chapter describes the registers of the transmit and receive mailboxes. Refer to section 24.7.5: message storage on page 644 for detailed register mapping. Transmit and receive mailboxes have the sam...

  • Page 661

    Rm0008 controller area network (bxcan) doc id 13902 rev 12 661/1096 can tx mailbox identifier register (can_tixr) (x=0..2) address offsets: 0x180, 0x190, 0x1a0 reset value: undefined (except bit 0, txrq = 0) note: 1 all tx registers are write protected when the mailbox is pending transmission (tmex ...

  • Page 662

    Controller area network (bxcan) rm0008 662/1096 doc id 13902 rev 12 can mailbox data length control and time stamp register (can_tdtxr) (x=0..2) all bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x184, 0x194, 0x1a4 reset value: undefined 31 30 29 ...

  • Page 663

    Rm0008 controller area network (bxcan) doc id 13902 rev 12 663/1096 can mailbox data low register (can_tdlxr) (x=0..2) all bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x188, 0x198, 0x1a8 reset value: undefined can mailbox data high register (can...

  • Page 664

    Controller area network (bxcan) rm0008 664/1096 doc id 13902 rev 12 can receive fifo mailbox identifier register (can_rixr) (x=0..1) address offsets: 0x1b0, 0x1c0 reset value: undefined note: all rx registers are write protected. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 stid[10:0]/exid[28:18]...

  • Page 665

    Rm0008 controller area network (bxcan) doc id 13902 rev 12 665/1096 can receive fifo mailbox data length control and time stamp register (can_rdtxr) (x=0..1) address offsets: 0x1b4, 0x1c4 reset value: undefined note: all rx registers are write protected. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ...

  • Page 666

    Controller area network (bxcan) rm0008 666/1096 doc id 13902 rev 12 can receive fifo mailbox data low register (can_rdlxr) (x=0..1) all bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x1b8, 0x1c8 reset value: undefined note: all rx registers are wr...

  • Page 667

    Rm0008 controller area network (bxcan) doc id 13902 rev 12 667/1096 24.9.4 can filter registers can filter master register (can_fmr) address offset: 0x200 reset value: 0x2a1c 0e01 note: all bits of this register are set and cleared by software. Bits 15:8 data5[7:0] : data byte 5 data byte 1 of the m...

  • Page 668

    Controller area network (bxcan) rm0008 668/1096 doc id 13902 rev 12 can filter mode register (can_fm1r) address offset: 0x204 reset value: 0x00 note: this register can be written only when the filter initialization mode is set (finit=1) in the can_fmr register. Note: please refer to figure 229: filt...

  • Page 669

    Rm0008 controller area network (bxcan) doc id 13902 rev 12 669/1096 can filter fifo assignment register (can_ffa1r) address offset: 0x214 reset value: 0x00 note: this register can be written only when the filter initialization mode is set (finit=1) in the can_fmr register. Can filter activation regi...

  • Page 670

    Controller area network (bxcan) rm0008 670/1096 doc id 13902 rev 12 filter bank i register x (can_firx) (i=0..27 in connectivity line devices,, x=1, 2) address offsets: 0x240..0x31c reset value: undefined note: in connectivity line devices there are 28 filter banks, i=0 .. 27, in other devices there...

  • Page 671

    Rm0008 controller area network (bxcan) doc id 13902 rev 12 671/1096 24.9.5 bxcan register map refer to table 3 on page 50 for the register boundary addresses. In connectivity line devices, the registers from offset 0x200 to 31c are present only in can1. Table 180. Bxcan register map and reset values...

  • Page 672

    Controller area network (bxcan) rm0008 672/1096 doc id 13902 rev 12 0x194 can_tdt1r time[15:0] reserved tg t reserved dlc[3:0] reset value x x x x x x x x x x x x x x x x x x x x x 0x198 can_tdl1r data3[7:0] data2[7:0] data1[7:0] data0[7:0] reset value x x x x x x x x x x x x x x x x x x x x x x x x...

  • Page 673

    Rm0008 controller area network (bxcan) doc id 13902 rev 12 673/1096 0x200 can_fmr reserved can2sb[5:0] reserved fi nit reset value 0 0 1 1 1 0 1 0x204 can_fm1r reserved fbm[27:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x208 reserved 0x20c can_fs1r reserved fsc[27:0] rese...

  • Page 674: 25.1 Spi

    Serial peripheral interface (spi) rm0008 674/1096 doc id 13902 rev 12 25 serial peripheral interface (spi) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f1...

  • Page 675: 25.2

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 675/1096 25.2 spi and i 2 s main features 25.2.1 spi features ● full-duplex synchronous transfers on three lines ● simplex synchronous transfers on two lines with or without a bidirectional data line ● 8- or 16-bit transfer frame format se...

  • Page 676

    Serial peripheral interface (spi) rm0008 676/1096 doc id 13902 rev 12 25.2.2 i 2 s features ● simplex communication (only transmitter or receiver) ● master or slave operations ● 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from 8 khz to 96 khz) ● data format may be...

  • Page 677: 25.3

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 677/1096 25.3 spi functional description 25.3.1 general description the block diagram of the spi is shown in figure 236 . Figure 236. Spi block diagram usually, the spi is connected to external devices through 4 pins: ● miso: master in / s...

  • Page 678

    Serial peripheral interface (spi) rm0008 678/1096 doc id 13902 rev 12 a basic example of interconnections between a single master and a single slave is illustrated in figure 237 . Figure 237. Single master/ single slave application 1. Here, the nss pin is configured as an input. The mosi pins are co...

  • Page 679

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 679/1096 figure 238. Hardware/software slave select management clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits in the spi_cr1 register. The cpol (clock polarity) bit...

  • Page 680

    Serial peripheral interface (spi) rm0008 680/1096 doc id 13902 rev 12 figure 239. Data clock timing diagram 1. These timings are shown with the lsbfirst bit reset in the spi_cr1 register. Data frame format data can be shifted out either msb-first or lsb-first depending on the value of the lsbfirst b...

  • Page 681

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 681/1096 procedure 1. Set the dff bit to define 8- or 16-bit data frame format 2. Select the cpol and cpha bits to define one of the four relationships between the data transfer and the serial clock (see figure 239 ). For correct data tran...

  • Page 682

    Serial peripheral interface (spi) rm0008 682/1096 doc id 13902 rev 12 25.3.3 configuring the spi in master mode in the master configuration, the serial clock is generated on the sck pin. Procedure 1. Select the br[2:0] bits to define the serial clock baud rate (see spi_cr1 register). 2. Select the c...

  • Page 683

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 683/1096 25.3.4 configuring the spi for simplex communication the spi is capable of operating in simplex mode in 2 configurations. ● 1 clock and 1 bidirectional data wire ● 1 clock and 1 data wire (receive-only or transmit-only) 1 clock an...

  • Page 684

    Serial peripheral interface (spi) rm0008 684/1096 doc id 13902 rev 12 start sequence in master mode ● in full-duplex (bidimode=0 and rxonly=0) – the sequence begins when data are written into the spi_dr register (tx buffer). – the data are then parallel loaded from the tx buffer into the 8-bit shift...

  • Page 685

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 685/1096 ● in bidirectional mode, when transmitting (bidimode=1 and bidioe=1) – the sequence begins when the slave device receives the clock signal and the first bit in the tx buffer is transmitted on the miso pin. – the data are then para...

  • Page 686

    Serial peripheral interface (spi) rm0008 686/1096 doc id 13902 rev 12 figure 240. Txe/rxne/bsy behavior in master / full-duplex mode (bidimode=0 and rxonly=0) in the case of continuous transfers figure 241. Txe/rxne/bsy behavior in slave / full-duplex mode (bidimode=0, rxonly=0) in the case of conti...

  • Page 687

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 687/1096 transmit-only procedure (bidimode=0 rxonly=0) in this mode, the procedure can be reduced as described below and the bsy bit can be used to wait until the completion of the transmission (see figure 242 and figure 243 ). 1. Enable t...

  • Page 688

    Serial peripheral interface (spi) rm0008 688/1096 doc id 13902 rev 12 figure 243. Txe/bsy in slave transmit-only mode (bidimode=0 and rxonly=0) in the case of continuous transfers bidirectional transmit procedure (bidimode=1 and bidioe=1) in this mode, the procedure is similar to the procedure in tr...

  • Page 689

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 689/1096 figure 244. Rxne behavior in receive-only mode (bidirmode=0 and rxonly=1) in the case of continuous transfers bidirectional receive procedure (bidimode=1 and bidioe=0) in this mode, the procedure is similar to the receive-only mod...

  • Page 690

    Serial peripheral interface (spi) rm0008 690/1096 doc id 13902 rev 12 figure 245. Txe/bsy behavior when transmitting (bidirmode=0 and rxonly=0) in the case of discontinuous transfers 25.3.6 crc calculation a crc calculator has been implemented for communication reliability. Separate crc calculators ...

  • Page 691

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 691/1096 spi communication using crc is possible through the following procedure: ● program the cpol, cpha, lsbfirst, br, ssm, ssi and mstr values ● program the polynomial in the spi_crcpr register ● enable the crc calculation by setting t...

  • Page 692

    Serial peripheral interface (spi) rm0008 692/1096 doc id 13902 rev 12 25.3.7 status flags three status flags are provided for the application to completely monitor the state of the spi bus. Tx buffer empty flag (txe) when it is set, this flag indicates that the tx buffer is empty and the next data t...

  • Page 693

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 693/1096 25.3.8 disabling the spi when a transfer is terminated, the application can stop the communication by disabling the spi peripheral. This is done by clearing the spe bit. For some configurations, disabling the spi and entering the ...

  • Page 694

    Serial peripheral interface (spi) rm0008 694/1096 doc id 13902 rev 12 25.3.9 spi communication using dma (direct memory addressing) to operate at its maximum speed, the spi needs to be fed with the data for transmission and the data received on the rx buffer should be read to avoid overrun. To facil...

  • Page 695

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 695/1096 figure 247. Reception using dma dma capability with crc when spi communication is enabled with crc communication and dma mode,the transmission and reception of the crc at the end of communication are automatic i.E. Without using t...

  • Page 696

    Serial peripheral interface (spi) rm0008 696/1096 doc id 13902 rev 12 as a security, hardware does not allow the setting of the spe and mstr bits while the modf bit is set. In a slave device the modf bit cannot be set. However, in a multimaster configuration, the device can be in slave mode with thi...

  • Page 697: 25.4 I

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 697/1096 25.4 i 2 s functional description the i 2 s audio protocol is not available in low- and medium-density devices. This section concerns only high-density, xl-density and connectivity line devices. 25.4.1 i 2 s general description th...

  • Page 698

    Serial peripheral interface (spi) rm0008 698/1096 doc id 13902 rev 12 the i 2 s shares three common pins with the spi: ● sd: serial data (mapped on the mosi pin) to transmit or receive the two time- multiplexed data channels (in simplex mode only). ● ws: word select (mapped on the nss pin) is the da...

  • Page 699

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 699/1096 the i 2 s interface supports four audio standards, configurable using the i2sstd[1:0] and pcmsync bits in the spi_i2scfgr register. I 2 s phillips standard for this standard, the ws signal is used to indicate which channel is bein...

  • Page 700

    Serial peripheral interface (spi) rm0008 700/1096 doc id 13902 rev 12 figure 251. Transmitting 0x8eaa33 ● in reception mode: if data 0x8eaa33 is received: figure 252. Receiving 0x8eaa33 figure 253. I 2 s phillips standard (16-bit extended to 32-bit packet frame with cpol = 0) when 16-bit data frame ...

  • Page 701

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 701/1096 figure 254. Example for transmission, each time an msb is written to spi_dr, the txe flag is set and its interrupt, if allowed, is generated to load spi_dr with the new value to send. This takes place even if 0x0000 have not yet b...

  • Page 702

    Serial peripheral interface (spi) rm0008 702/1096 doc id 13902 rev 12 figure 256. Msb justified 24-bit frame length with cpol = 0 figure 257. Msb justified 16-bit extended to 32-bit packet frame with cpol = 0 lsb justified standard this standard is similar to the msb justified standard (no differenc...

  • Page 703

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 703/1096 figure 259. Lsb justified 24-bit frame length with cpol = 0 ● in transmission mode: if data 0x3478ae have to be transmitted, two write operations to the spi_dr register are required from software or by dma. The operations are show...

  • Page 704

    Serial peripheral interface (spi) rm0008 704/1096 doc id 13902 rev 12 figure 262. Lsb justified 16-bit extended to 32-bit packet frame with cpol = 0 when 16-bit data frame extended to 32-bit channel frame is selected during the i 2 s configuration phase, only one access to spi_dr is required. The 16...

  • Page 705

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 705/1096 figure 264. Pcm standard waveforms (16-bit) for long frame synchronization, the ws signal assertion time is fixed 13 bits in master mode. For short frame synchronization, the ws synchronization signal is only one cycle long. Figur...

  • Page 706

    Serial peripheral interface (spi) rm0008 706/1096 doc id 13902 rev 12 it will be: i 2 s bitrate = 32 x 2 x f s if the packet length is 32-bit wide. Figure 266. Audio sampling frequency definition when the master mode is configured, a specific action needs to be taken to properly program the linear d...

  • Page 707

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 707/1096 note: other configurations are possible that allow optimum clock precision. Table 182. Audio-frequency precision using standard 8 mhz hse (high-density and xl-density devices only) sysclk (mhz) i2s_div i2s_odd mclk target f s (hz)...

  • Page 708

    Serial peripheral interface (spi) rm0008 708/1096 doc id 13902 rev 12 table 183. Audio-frequency precision using standard 25 mhz and pll3 (connectivity line devices only) data length prediv2 pll3mul i2sdiv i2sodd mclk target fs(hz) real fs (khz) error 32 6 14 9 1 no 96000 95942.9825 0.0594% 16 6 14 ...

  • Page 709

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 709/1096 table 184. Audio-frequency precision using standard 14.7456 mhz and pll3 (connectivity line devices only) data length prediv2 pll3mul i2sdiv i2sodd mclk target fs(hz) real fs (khz) error 16 3 10 16 0 no 96000 96000 0.0000% 32 3 10...

  • Page 710

    Serial peripheral interface (spi) rm0008 710/1096 doc id 13902 rev 12 25.4.4 i 2 s master mode the i 2 s can be configured in master mode. This means that the serial clock is generated on the ck pin as well as the word select signal ws. Master clock (mck) may be output or not, thanks to the mckoe bi...

  • Page 711

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 711/1096 reception sequence the operating mode is the same as for the transmission mode except for the point 3 (refer to the procedure described in section 25.4.4: i2s master mode ), where the configuration should set the master reception ...

  • Page 712

    Serial peripheral interface (spi) rm0008 712/1096 doc id 13902 rev 12 clock and ws signals are input from the external master connected to the i 2 s interface. There is then no need, for the user, to configure the clock. The configuration steps to follow are listed below: 1. Set the i2smod bit in th...

  • Page 713

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 713/1096 reception sequence the operating mode is the same as for the transmission mode except for the point 1 (refer to the procedure described in section 25.4.5: i2s slave mode ), where the configuration should set the master reception m...

  • Page 714

    Serial peripheral interface (spi) rm0008 714/1096 doc id 13902 rev 12 tx buffer empty flag (txe) when set, this flag indicates that the tx buffer is empty and the next data to be transmitted can then be loaded into it. The txe flag is reset when the tx buffer already contains data to be transmitted....

  • Page 715

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 715/1096 1. 2. 25.4.8 i 2 s interrupts table 185 provides the list of i 2 s interrupts. 25.4.9 dma features dma is working in exactly the same way as for the spi mode. There is no difference on the i 2 s. Only the crc feature is not availa...

  • Page 716: 25.5

    Serial peripheral interface (spi) rm0008 716/1096 doc id 13902 rev 12 25.5 spi and i 2 s registers refer to section 2.1 on page 45 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 25.5.1 spi control register...

  • Page 717

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 717/1096 bit 10 rxonly: receive only this bit combined with the bidimode bit selects the direction of transfer in 2-line unidirectional mode. This bit is also useful in a multislave system in which this particular slave is not accessed, th...

  • Page 718

    Serial peripheral interface (spi) rm0008 718/1096 doc id 13902 rev 12 bit1 cpol: clock polarity 0: ck to 0 when idle 1: ck to 1 when idle note: this bit should not be changed when communication is ongoing. Not used in i 2 s mode bit 0 cpha: clock phase 0: the first clock transition is the first data...

  • Page 719

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 719/1096 25.5.2 spi control register 2 (spi_cr2) address offset: 0x04 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved txeie rxneie errie res. Res. Ssoe txdmaen rxdmaen rw rw rw rw rw rw bits 15:8 reserved. Forced to 0 by...

  • Page 720

    Serial peripheral interface (spi) rm0008 720/1096 doc id 13902 rev 12 25.5.3 spi status register (spi_sr) address offset: 0x08 reset value: 0x0002 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved bsy ovr modf crc err udr chsid e txe rxne r r r rc_w0 r r r r bits 15:8 reserved. Forced to 0 by hardware....

  • Page 721

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 721/1096 25.5.4 spi data register (spi_dr) address offset: 0x0c reset value: 0x0000 25.5.5 spi crc polynomial register (spi_crcpr) (not used in i 2 s mode) address offset: 0x10 reset value: 0x0007 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dr[1...

  • Page 722

    Serial peripheral interface (spi) rm0008 722/1096 doc id 13902 rev 12 25.5.6 spi rx crc register (spi_rxcrcr) (not used in i 2 s mode) address offset: 0x14 reset value: 0x0000 25.5.7 spi tx crc register (spi_txcrcr) (not used in i 2 s mode) address offset: 0x18 reset value: 0x0000 15 14 13 12 11 10 ...

  • Page 723

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 723/1096 25.5.8 spi_i 2 s configuration register (spi_i2scfgr) address offset: 0x1c reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved i2smod i2se i2scfg pcmsy nc reserved i2sstd ckpol datlen chlen rw rw rw rw rw rw rw rw r...

  • Page 724

    Serial peripheral interface (spi) rm0008 724/1096 doc id 13902 rev 12 25.5.9 spi_i 2 s prescaler register (spi_i2spr) address offset: 0x20 reset value: 0000 0010 (0x0002) bit 2:1 datlen: data length to be transferred 00: 16-bit data length 01: 24-bit data length 10: 32-bit data length 11: not allowe...

  • Page 725

    Rm0008 serial peripheral interface (spi) doc id 13902 rev 12 725/1096 25.5.10 spi register map the table provides shows the spi register map and reset values. Refer to table 3: register boundary addresses for the register boundary addresses. Table 186. Spi register map and reset values offset regist...

  • Page 726: Inter-Integrated Circuit (I

    Inter-integrated circuit (i 2 c) interface rm0008 726/1096 doc id 13902 rev 12 26 inter-integrated circuit (i 2 c) interface low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are st...

  • Page 727: 26.3 I

    Rm0008 inter-integrated circuit (i 2 c) interface doc id 13902 rev 12 727/1096 – i 2 c busy flag ● error flags: – arbitration lost condition for master mode – acknowledgement failure after address/ data transmission – detection of misplaced start or stop condition – overrun/underrun if clock stretch...

  • Page 728

    Inter-integrated circuit (i 2 c) interface rm0008 728/1096 doc id 13902 rev 12 communication flow in master mode, the i 2 c interface initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and s...

  • Page 729

    Rm0008 inter-integrated circuit (i 2 c) interface doc id 13902 rev 12 729/1096 figure 269. I 2 c block diagram 1. Smba is an optional signal in smbus mode. This signal is not applicable if smbus is disabled. 26.3.2 i 2 c slave mode by default the i 2 c interface operates in slave mode. To switch fro...

  • Page 730

    Inter-integrated circuit (i 2 c) interface rm0008 730/1096 doc id 13902 rev 12 address matched: the interface generates in sequence: ● an acknowledge pulse if the ack bit is set ● the addr bit is set by hardware and an interrupt is generated if the itevfen bit is set. ● if endual=1, the software has...

  • Page 731

    Rm0008 inter-integrated circuit (i 2 c) interface doc id 13902 rev 12 731/1096 slave receiver following the address reception and after clearing addr, the slave receives bytes from the sda line into the dr register via the internal shift register. After each byte the interface generates in sequence:...

  • Page 732

    Inter-integrated circuit (i 2 c) interface rm0008 732/1096 doc id 13902 rev 12 the following is the required sequence in master mode. ● program the peripheral input clock in i2c_cr2 register in order to generate correct timings ● configure the clock control registers ● configure the rise time regist...

  • Page 733

    Rm0008 inter-integrated circuit (i 2 c) interface doc id 13902 rev 12 733/1096 start condition setting the start bit causes the interface to generate a start condition and to switch to master mode (m/sl bit set) when the busy bit is cleared. Note: in master mode, setting the start bit causes the int...

  • Page 734

    Inter-integrated circuit (i 2 c) interface rm0008 734/1096 doc id 13902 rev 12 master transmitter following the address transmission and after clearing addr, the master sends bytes from the dr register to the sda line via the internal shift register. The master waits until the first data byte is wri...

  • Page 735

    Rm0008 inter-integrated circuit (i 2 c) interface doc id 13902 rev 12 735/1096 master receiver following the address transmission and after clearing addr, the i 2 c interface enters master receiver mode. In this mode the interface receives bytes from the sda line into the dr register via the interna...

  • Page 736

    Inter-integrated circuit (i 2 c) interface rm0008 736/1096 doc id 13902 rev 12 figure 273. Method 1: transfer sequence diagram for master receiver 1. If a single byte is received, it is na. 2. The ev5, ev6 and ev9 events stretch scl low until the end of the corresponding software sequence. 3. The ev...

  • Page 737

    Rm0008 inter-integrated circuit (i 2 c) interface doc id 13902 rev 12 737/1096 figure 274. Method 2: transfer sequence diagram for master receiver when n>2 1. The ev5, ev6 and ev9 events stretch scl low until the end of the corresponding software sequence. 2. The ev7 software sequence must complete ...

  • Page 738

    Inter-integrated circuit (i 2 c) interface rm0008 738/1096 doc id 13902 rev 12 the procedure described above is valid for n>2. The cases where a single byte or two bytes are to be received should be handled differently, as described below: ● case of a single byte to be received: – in the addr event,...

  • Page 739

    Rm0008 inter-integrated circuit (i 2 c) interface doc id 13902 rev 12 739/1096 figure 276. Method 2: transfer sequence diagram for master receiver when n=1 1. The ev5, ev6 and ev9 events stretch scl low until the end of the corresponding software sequence. 26.3.4 error conditions the following are t...

  • Page 740

    Inter-integrated circuit (i 2 c) interface rm0008 740/1096 doc id 13902 rev 12 arbitration lost (arlo) this error occurs when the i 2 c interface detects an arbitration lost condition. In this case, ● the arlo bit is set by hardware (and an interrupt is generated if the iterren bit is set) ● the i 2...

  • Page 741

    Rm0008 inter-integrated circuit (i 2 c) interface doc id 13902 rev 12 741/1096 26.3.6 smbus introduction the system management bus (smbus) is a two-wire interface through which various devices can communicate with each other and with the rest of the system. It is based on i 2 c principles of operati...

  • Page 742

    Inter-integrated circuit (i 2 c) interface rm0008 742/1096 doc id 13902 rev 12 bus protocols the smbus specification supports up to 9 bus protocols. For more details of these protocols and smbus address types, refer to smbus specification ver. 2.0 ( http://smbus.Org/specs/ ). These protocols should ...

  • Page 743

    Rm0008 inter-integrated circuit (i 2 c) interface doc id 13902 rev 12 743/1096 timeout error there are differences in the timing specifications between i 2 c and smbus. Smbus defines a clock low timeout, timeout of 35 ms. Also smbus specifies tlow: sext as the cumulative clock low extend time for a ...

  • Page 744

    Inter-integrated circuit (i 2 c) interface rm0008 744/1096 doc id 13902 rev 12 1. Set the i2c_dr register address in the dma_cparx register. The data will be moved to this address from the memory after each txe event. 2. Set the memory address in the dma_cmarx register. The data will be loaded into ...

  • Page 745: 26.4 I

    Rm0008 inter-integrated circuit (i 2 c) interface doc id 13902 rev 12 745/1096 26.3.8 packet error checking a pec calculator has been implemented to improve the reliability of communication. The pec is calculated by using the c(x) = x 8 + x 2 + x + 1 crc-8 polynomial serially on each bit. ● pec calc...

  • Page 746

    Inter-integrated circuit (i 2 c) interface rm0008 746/1096 doc id 13902 rev 12 note: 1 sb, addr, add10, stopf, btf, rxne and txe are logically ored on the same interrupt channel. 2 berr, arlo, af, ovr, pecerr, timeout and smbalert are logically ored on the same interrupt channel. Figure 277. I 2 c i...

  • Page 747: 26.5 I

    Rm0008 inter-integrated circuit (i 2 c) interface doc id 13902 rev 12 747/1096 26.5 i 2 c debug mode when the microcontroller enters the debug mode (cortex-m3 core halted), the smbus timeout either continues to work normally or stops, depending on the dbg_i2cx_smbus_timeout configuration bits in the...

  • Page 748

    Inter-integrated circuit (i 2 c) interface rm0008 748/1096 doc id 13902 rev 12 bit 11 pos: acknowledge/pec position (for data reception) this bit is set and cleared by software and cleared by hardware when pe=0. 0: ack bit controls the (n)ack of the current byte being received in the shift register....

  • Page 749

    Rm0008 inter-integrated circuit (i 2 c) interface doc id 13902 rev 12 749/1096 26.6.2 control register 2 (i2c_cr2) address offset: 0x04 reset value: 0x0000 bit 4 enarp: arp enable 0: arp disable 1: arp enable smbus device default address recognized if smbtype=0 smbus host address recognized if smbty...

  • Page 750

    Inter-integrated circuit (i 2 c) interface rm0008 750/1096 doc id 13902 rev 12 26.6.3 own address register 1 (i2c_oar1) address offset: 0x08 reset value: 0x0000 bit 9 itevten:event interrupt enable 0: event interrupt disabled 1: event interrupt enabled this interrupt is generated when: –sb = 1 (mast...

  • Page 751

    Rm0008 inter-integrated circuit (i 2 c) interface doc id 13902 rev 12 751/1096 26.6.4 own address register 2 (i2c_oar2) address offset: 0x0c reset value: 0x0000 26.6.5 data register (i2c_dr) address offset: 0x10 reset value: 0x0000 bits 13:10 reserved, forced by hardware to 0. Bits 9:8 add[9:8]: int...

  • Page 752

    Inter-integrated circuit (i 2 c) interface rm0008 752/1096 doc id 13902 rev 12 26.6.6 status register 1 (i2c_sr1) address offset: 0x14 reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smb alert time out res. Pec err ovr af arlo berr txe rxne res. Stopf add10 btf addr sb rc_w0 rc_w0 rc_w0 rc...

  • Page 753

    Rm0008 inter-integrated circuit (i 2 c) interface doc id 13902 rev 12 753/1096 bit 10 af:acknowledge failure 0: no acknowledge failure 1: acknowledge failure –set by hardware when no acknowledge is returned. –cleared by software writing 0, or by hardware when pe=0. Bit 9 arlo:arbitration lost (maste...

  • Page 754

    Inter-integrated circuit (i 2 c) interface rm0008 754/1096 doc id 13902 rev 12 bit 3 add10:10-bit header sent (master mode) 0: no add10 event occurred. 1: master has sent first address byte (header). –set by hardware when the master has sent the first byte in 10-bit address mode. –cleared by softwar...

  • Page 755

    Rm0008 inter-integrated circuit (i 2 c) interface doc id 13902 rev 12 755/1096 26.6.7 status register 2 (i2c_sr2) address offset: 0x18 reset value:0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pec[7:0] dualf smb host smbde fault gen call res. Tra busy msl r r r r r r r r r r r r r r r bits 15:8 pec[7...

  • Page 756

    Inter-integrated circuit (i 2 c) interface rm0008 756/1096 doc id 13902 rev 12 26.6.8 clock control register (i2c_ccr) address offset: 0x1c reset value: 0x0000 note: 1 to use the i2c at 400 khz (in fast mode), the pclk1 frequency (i2c peripheral input clock) must be a multiple of 10 mhz. 2 the ccr r...

  • Page 757

    Rm0008 inter-integrated circuit (i 2 c) interface doc id 13902 rev 12 757/1096 26.6.9 trise register (i2c_trise) address offset: 0x20 reset value: 0x0002 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved trise[5:0] rw rw rw rw rw rw bits 15:6 reserved, forced by hardware to 0. Bits 5:0 trise[5:0]: maxi...

  • Page 758

    Inter-integrated circuit (i 2 c) interface rm0008 758/1096 doc id 13902 rev 12 26.6.10 i 2 c register map the table below provides the i 2 c register map and reset values. Refer to table 3: register boundary addresses for the register boundary addresses table. Table 189. I 2 c register map and reset...

  • Page 759: Transmitter (Usart)

    Rm0008 universal synchronous asynchronous receiver transmitter (usart) doc id 13902 rev 12 759/1096 27 universal synchronous asynchronous receiver transmitter (usart) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 an...

  • Page 760: 27.2

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 760/1096 doc id 13902 rev 12 27.2 usart main features ● full duplex, asynchronous communications ● nrz standard format (mark/space) ● fractional baud rate generator systems – a common programmable transmit and receive baud rates ...

  • Page 761: 27.3

    Rm0008 universal synchronous asynchronous receiver transmitter (usart) doc id 13902 rev 12 761/1096 ● parity control: – transmits parity bit – checks parity of received data byte ● four error detection flags: – overrun error – noise error – frame error – parity error ● ten interrupt sources with fla...

  • Page 762

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 762/1096 doc id 13902 rev 12 through these pins, serial data is transmitted and received in normal usart mode as frames comprising: ● an idle line prior to transmission or reception ● a start bit ● a data word (8 or 9 bits) least...

  • Page 763

    Rm0008 universal synchronous asynchronous receiver transmitter (usart) doc id 13902 rev 12 763/1096 27.3.1 usart block diagram usart character description word length may be selected as being either 8 or 9 bits by programming the m bit in the usart_cr1 register (see figure 278 ). The tx pin is in lo...

  • Page 764

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 764/1096 doc id 13902 rev 12 a break character is interpreted on receiving “0”s for a frame period. At the end of the break frame the transmitter inserts either 1 or 2 stop bits (logic “1” bit) to acknowledge the start bit. Trans...

  • Page 765

    Rm0008 universal synchronous asynchronous receiver transmitter (usart) doc id 13902 rev 12 765/1096 27.3.2 transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. When the transmit enable bit (te) is set, the data in the transmit shift register is output ...

  • Page 766

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 766/1096 doc id 13902 rev 12 figure 279. Configurable stop bits procedure: 1. Enable the usart by writing the ue bit in usart_cr1 register to 1. 2. Program the m bit in usart_cr1 to define the word length. 3. Program the number o...

  • Page 767

    Rm0008 universal synchronous asynchronous receiver transmitter (usart) doc id 13902 rev 12 767/1096 when a transmission is taking place, a write instruction to the usart_dr register stores the data in the tdr register and which is copied in the shift register at the end of the current transmission. ...

  • Page 768

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 768/1096 doc id 13902 rev 12 27.3.3 receiver the usart can receive data words of either 8 or 9 bits depending on the m bit in the usart_cr1 register. Start bit detection in the usart, the start bit is detected when a specific seq...

  • Page 769

    Rm0008 universal synchronous asynchronous receiver transmitter (usart) doc id 13902 rev 12 769/1096 character reception during a usart reception, data shifts in least significant bit first through the rx pin. In this mode, the usart_dr register consists of a buffer (rdr) between the internal bus and...

  • Page 770

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 770/1096 doc id 13902 rev 12 the rxne flag is set after every byte received. An overrun error occurs if rxne flag is set when the next data is received or the previous dma request has not been serviced. When an overrun error occu...

  • Page 771

    Rm0008 universal synchronous asynchronous receiver transmitter (usart) doc id 13902 rev 12 771/1096 when noise is detected in a frame: ● the ne is set at the rising edge of the rxne bit. ● the invalid data is transferred from the shift register to the usart_dr register. ● no interrupt is generated i...

  • Page 772

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 772/1096 doc id 13902 rev 12 configurable stop bits during reception the number of stop bits to be received can be configured through the control bits of control register 2 - it can be either 1 or 2 in normal mode and 0.5 or 1.5 ...

  • Page 773

    Rm0008 universal synchronous asynchronous receiver transmitter (usart) doc id 13902 rev 12 773/1096 this leads to: div_fraction = 16*0d0.62 = 0d9.92 the nearest real number is 0d10 = 0xa div_mantissa = mantissa (0d25.620) = 0d25 = 0x19 then, usart_brr = 0x19a hence usartdiv = 0d25.625 example 3: to ...

  • Page 774

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 774/1096 doc id 13902 rev 12 27.3.5 usart receiver’s tolerance to clock deviation the usart’s asynchronous receiver works correctly only if the total clock system deviation is smaller than the usart receiver’s tolerance. The caus...

  • Page 775

    Rm0008 universal synchronous asynchronous receiver transmitter (usart) doc id 13902 rev 12 775/1096 the non addressed devices may be placed in mute mode by means of the muting function. In mute mode: ● none of the reception status bits can be set. ● all the receive interrupts are inhibited. ● the rw...

  • Page 776

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 776/1096 doc id 13902 rev 12 figure 284. Mute mode using address mark detection 27.3.7 parity control parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the pce bi...

  • Page 777

    Rm0008 universal synchronous asynchronous receiver transmitter (usart) doc id 13902 rev 12 777/1096 27.3.8 lin (local interconnection network) mode the lin mode is selected by setting the linen bit in the usart_cr2 register. In lin mode, the following bits must be kept cleared: ● clken in the usart_...

  • Page 778

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 778/1096 doc id 13902 rev 12 figure 285. Break detection in lin mode (11-bit break length - lbdl bit is set) case 1: break signal not long enough => break discarded, lbd is not set break frame rx line break state machine capture ...

  • Page 779

    Rm0008 universal synchronous asynchronous receiver transmitter (usart) doc id 13902 rev 12 779/1096 figure 286. Break detection in lin mode vs. Framing error detection 27.3.9 usart synchronous mode the synchronous mode is selected by writing the clken bit in the usart_cr2 register to 1. In synchrono...

  • Page 780

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 780/1096 doc id 13902 rev 12 note: 1 the ck pin works in conjunction with the tx pin. Thus, the clock is provided only if the transmitter is enabled (te=1) and a data is being transmitted (the data register usart_dr has been writ...

  • Page 781

    Rm0008 universal synchronous asynchronous receiver transmitter (usart) doc id 13902 rev 12 781/1096 figure 289. Usart data clock timing diagram (m=1) figure 290. Rx data setup/hold time note: the function of ck is different in smartcard mode. Refer to the smartcard mode chapter for more details. 27....

  • Page 782

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 782/1096 doc id 13902 rev 12 apart from this, the communications are similar to what is done in normal usart mode. The conflicts on the line must be managed by the software (by the use of a centralized arbiter, for instance). In ...

  • Page 783

    Rm0008 universal synchronous asynchronous receiver transmitter (usart) doc id 13902 rev 12 783/1096 smartcard is a single wire half duplex communication protocol. ● transmission of data from the transmit shift register is guaranteed to be delayed by a minimum of 1/2 baud clock. In normal operation a...

  • Page 784

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 784/1096 doc id 13902 rev 12 figure 292. Parity error detection using the 1.5 stop bits the usart can provide a clock to the smartcard through the ck output. In smartcard mode, ck is not associated to the communication but is sim...

  • Page 785

    Rm0008 universal synchronous asynchronous receiver transmitter (usart) doc id 13902 rev 12 785/1096 ● irda is a half duplex communication protocol. If the transmitter is busy (i.E. The usartsends data to the irda encoder), any data on the irda receive line is ignored by the irda decoder and if the r...

  • Page 786

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 786/1096 doc id 13902 rev 12 figure 293. Irda sir endec- block diagram figure 294. Irda data modulation (3/16) -normal mode 27.3.13 continuous communication using dma the usart is capable of continuing communication using the dma...

  • Page 787

    Rm0008 universal synchronous asynchronous receiver transmitter (usart) doc id 13902 rev 12 787/1096 1. Write the usart_dr register address in the dma control register to configure it as the destination of the transfer. The data will be moved to this address from memory after each txe event. 2. Write...

  • Page 788

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 788/1096 doc id 13902 rev 12 reception using dma dma mode can be enabled for reception by setting the dmar bit in usart_cr3 register. Data is loaded from the usart_dr register to a sram area configured using the dma peripheral (r...

  • Page 789

    Rm0008 universal synchronous asynchronous receiver transmitter (usart) doc id 13902 rev 12 789/1096 27.3.14 hardware flow control it is possible to control the serial data flow between 2 devices by using the ncts input and the nrts output. The figure 297 shows how to connect 2 devices in this mode: ...

  • Page 790: 27.4 Usart

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 790/1096 doc id 13902 rev 12 figure 299. Cts flow control 27.4 usart interrupts the usart interrupt events are connected to the same interrupt vector (see figure 300 ). ● during transmission: transmission complete, clear to send ...

  • Page 791: 27.5

    Rm0008 universal synchronous asynchronous receiver transmitter (usart) doc id 13902 rev 12 791/1096 figure 300. Usart interrupt mapping diagram 27.5 usart mode configuration 27.6 usart registers refer to section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral...

  • Page 792

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 792/1096 doc id 13902 rev 12 27.6.1 status register (usart_sr) address offset: 0x00 reset value: 0x00c0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved cts lbd txe tc rxne i...

  • Page 793

    Rm0008 universal synchronous asynchronous receiver transmitter (usart) doc id 13902 rev 12 793/1096 bit 4 idle: idle line detected this bit is set by hardware when an idle line is detected. An interrupt is generated if the idleie=1 in the usart_cr1 register. It is cleared by a software sequence (an ...

  • Page 794

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 794/1096 doc id 13902 rev 12 27.6.2 data register (usart_dr) address offset: 0x04 reset value: undefined 27.6.3 baud rate register (usart_brr) note: the baud counters stop counting if the te or re bits are disabled respectively. ...

  • Page 795

    Rm0008 universal synchronous asynchronous receiver transmitter (usart) doc id 13902 rev 12 795/1096 27.6.4 control register 1 (usart_cr1) address offset: 0x0c reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ue m wake pce ps ...

  • Page 796

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 796/1096 doc id 13902 rev 12 bit 6 tcie: transmission complete interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: a usart interrupt is generated whenever tc=1 in the usart_sr register bit 5 rxn...

  • Page 797

    Rm0008 universal synchronous asynchronous receiver transmitter (usart) doc id 13902 rev 12 797/1096 27.6.5 control register 2 (usart_cr2) address offset: 0x10 reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res. Linen stop[1:0] clk e...

  • Page 798

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 798/1096 doc id 13902 rev 12 note: these 3 bits (cpol, cpha, lbcl) should not be written while the transmitter is enabled. 27.6.6 control register 3 (usart_cr3) address offset: 0x14 reset value: 0x0000 bit 8 lbcl: last bit clock ...

  • Page 799

    Rm0008 universal synchronous asynchronous receiver transmitter (usart) doc id 13902 rev 12 799/1096 bit 8 rtse: rts enable 0: rts hardware flow control disabled 1: rts interrupt enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease a...

  • Page 800

    Universal synchronous asynchronous receiver transmitter (usart) rm0008 800/1096 doc id 13902 rev 12 27.6.7 guard time and prescaler register (usart_gtpr) address offset: 0x18 reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gt[7:0] ps...

  • Page 801

    Rm0008 universal synchronous asynchronous receiver transmitter (usart) doc id 13902 rev 12 801/1096 27.6.8 usart register map the table below gives the usart register map and reset values. Refer to table 3 on page 50 for the register boundary addresses. Table 197. Usart register map and reset values...

  • Page 802: 28.1 Otg_Fs

    Usb on-the-go full-speed (otg_fs) rm0008 802/1096 doc id 13902 rev 12 28 usb on-the-go full-speed (otg_fs) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f1...

  • Page 803: 28.2 Otg_Fs

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 803/1096 28.2 otg_fs main features the main features can be divided into three categories: general, host-mode and device- mode features. 28.2.1 general features the otg_fs interface general features are the following: ● it is usb-if certif...

  • Page 804

    Usb on-the-go full-speed (otg_fs) rm0008 804/1096 doc id 13902 rev 12 28.2.2 host-mode features the otg_fs interface main features and requirements in host-mode are the following: ● external charge pump for v bus voltage generation. ● up to 8 host channels (pipes): each channel is dynamically reconf...

  • Page 805: 28.3

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 805/1096 28.3 otg_fs functional description figure 301. Block diagram 28.3.1 otg full-speed core the usb otg fs receives the 48 mhz ±0.25% clock from the reset and clock controller (rcc), via an external quartz. The usb clock is used for d...

  • Page 806: 28.4

    Usb on-the-go full-speed (otg_fs) rm0008 806/1096 doc id 13902 rev 12 the physical support to usb connectivity. The full-speed otg phy includes the following components: ● fs/ls transceiver module used by both host and device. It directly drives transmission and reception on the single-ended usb lin...

  • Page 807

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 807/1096 28.4.1 id line detection the host or peripheral (the default) role is assumed depending on the id input pin. The id line status is determined on plugging in the usb, depending on which side of the usb cable is connected to the mic...

  • Page 808: 28.5 Usb

    Usb on-the-go full-speed (otg_fs) rm0008 808/1096 doc id 13902 rev 12 28.5 usb peripheral this section gives the functional description of the otg_fs in the usb peripheral mode. The otg_fs works as an usb peripheral in the following circumstances: ● otg b-peripheral – otg b-device default state if b...

  • Page 809

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 809/1096 in this way, it allows the remote a-device to save power by switching off v bus while the usb session is suspended. The srp peripheral mode program model is described in detail in the b-device session request protocol section. 28....

  • Page 810

    Usb on-the-go full-speed (otg_fs) rm0008 810/1096 doc id 13902 rev 12 when a resume signaling is detected from the host, the resume interrupt (rwusig bit in otg_fs_gintsts) is generated and the device suspend bit is automatically cleared. 28.5.3 peripheral endpoints the otg_fs core instantiates the ...

  • Page 811

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 811/1096 endpoint control ● the following endpoint controls are available to the application through the device endpoint-x in/out control register (diepctlx/doepctlx): – endpoint enable/disable – endpoint activate in current configuration ...

  • Page 812: 28.6 Usb

    Usb on-the-go full-speed (otg_fs) rm0008 812/1096 doc id 13902 rev 12 the peripheral core provides the following status checks and interrupt generation: ● transfer completed interrupt, indicating that data transfer was completed on both the application (ahb) and usb sides ● setup stage has been done...

  • Page 813

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 813/1096 figure 304. Usb host-only connection 1. Stmps2141str needed only if the application has to support a v bus powered device. A basic power switch can be used if 5 v are available on the application board. 28.6.1 srp-capable host srp...

  • Page 814

    Usb on-the-go full-speed (otg_fs) rm0008 814/1096 doc id 13902 rev 12 when v bus is at a valid level and a remote b-device is attached, the otg_fs core issues a host port interrupt triggered by the device connected bit in the host port control and status register (pcdet bit in otg_fs_hprt). Host det...

  • Page 815

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 815/1096 each host channel can be configured to support in/out and any type of periodic/nonperiodic transaction. Each host channel makes us of proper control (hccharx), transfer configuration (hctsizx) and status/interrupt (hcintx) registe...

  • Page 816

    Usb on-the-go full-speed (otg_fs) rm0008 816/1096 doc id 13902 rev 12 corresponding bits in the haint and gintsts registers. The mask bits for each interrupt source of each channel are also available in the otg_fs_hcintmsk-x register. ● the host core provides the following status checks and interrup...

  • Page 817: 28.7 Sof

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 817/1096 ptxqsav bits in the otg_fs_hnptxsts register or nptqxsav bits in the otg_fs_hnptxsts register. 28.7 sof trigger figure 305. Sof connectivity the otg fs core provides means to monitor, track and configure sof framing in the host an...

  • Page 818: 28.8 Power

    Usb on-the-go full-speed (otg_fs) rm0008 818/1096 doc id 13902 rev 12 register (sofouten bit in otg_fs_gccfg). The sof pulse signal is also internally connected to the tim2 input trigger, so that the input capture feature, the output compare feature and the timer can be triggered by the sof pulse. T...

  • Page 819: 28.9

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 819/1096 to save dynamic power, the usb data fifo is clocked only when accessed by the otg_fs core. 28.9 dynamic update of the otg_fs_hfir register the usb core embeds a dynamic trimming capability of micro-sof framing period in host mode ...

  • Page 820: 28.11 Peripheral

    Usb on-the-go full-speed (otg_fs) rm0008 820/1096 doc id 13902 rev 12 28.11 peripheral fifo architecture figure 307. Device-mode fifo address mapping and ahb fifo access mapping 28.11.1 peripheral rx fifo the otg peripheral uses a single receive fifo that receives the data directed to all out endpoi...

  • Page 821: 28.12

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 821/1096 28.11.2 peripheral tx fifos the core has a dedicated fifo for each in endpoint. The application configures fifo sizes by writing the non periodic transmit fifo size register (otg_fs_tx0fsiz) for in endpoint0 and the device in endp...

  • Page 822: 28.13

    Usb on-the-go full-speed (otg_fs) rm0008 822/1096 doc id 13902 rev 12 28.12.2 host tx fifos the host uses one transmit fifo for all non-periodic (control and bulk) out transactions and one transmit fifo for all periodic (isochronous and interrupt) out transactions. Fifos are used as transmit buffers...

  • Page 823: 28.14 Usb

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 823/1096 transmit fifo ram allocation: the minimum ram space required for each in endpoint transmit fifo is the maximum packet size for that particular in endpoint. Note: more space allocated in the transmit in endpoint fifo results in bet...

  • Page 824: 28.15 Otg_Fs

    Usb on-the-go full-speed (otg_fs) rm0008 824/1096 doc id 13902 rev 12 otg_fs to fill in the available ram space at best regardless of the current usb sequence. With these features: ● the application gains good margins to calibrate its intervention in order to optimize the cpu bandwidth usage: – it c...

  • Page 825

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 825/1096 figure 309. Interrupt hierarchy 1. The core interrupt register bits are shown in otg_fs core interrupt register (otg_fs_gintsts) on page 840 . 31 30 29 28 27 26 25 24 23 20 19 18 17:10 9 8 7:3 2 1 0 and or interrupt global interru...

  • Page 826: 28.16

    Usb on-the-go full-speed (otg_fs) rm0008 826/1096 doc id 13902 rev 12 28.16 otg_fs control and status registers by reading from and writing to the control and status registers (csrs) through the ahb slave interface, the application controls the otg_fs controller. These registers are 32 bits wide, an...

  • Page 827

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 827/1096 28.16.1 csr memory map the host and device mode registers occupy different addresses. All registers are implemented in the ahb clock domain. Figure 310. Csr memory map 1. X = 3 in device mode and x = 7 in host mode. Global csr map...

  • Page 828

    Usb on-the-go full-speed (otg_fs) rm0008 828/1096 doc id 13902 rev 12 host-mode csr map these registers must be programmed every time the core changes to host mode. Otg_fs_gintsts 0x014 otg_fs core interrupt register (otg_fs_gintsts) on page 840 otg_fs_gintmsk 0x018 otg_fs interrupt mask register (o...

  • Page 829

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 829/1096 device-mode csr map these registers must be programmed every time the core changes to device mode. Otg_fs_hprt 0x440 otg_fs host port control and status register (otg_fs_hprt) on page 856 otg_fs_hccharx 0x500 0x520 ... 0x6e0h otg_...

  • Page 830

    Usb on-the-go full-speed (otg_fs) rm0008 830/1096 doc id 13902 rev 12 data fifo (dfifo) access register map these registers, available in both host and device modes, are used to read or write the fifo space for a specific endpoint or a channel, in a given direction. If a host channel is of type in, ...

  • Page 831

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 831/1096 power and clock gating csr map there is a single register for power and clock gating. It is available in both host and device modes. 28.16.2 otg_fs global registers these registers are available in both host and device modes, and ...

  • Page 832

    Usb on-the-go full-speed (otg_fs) rm0008 832/1096 doc id 13902 rev 12 bit 19 bsvld: b-session valid indicates the device mode transceiver status. 0: b-session is not valid. 1: b-session is valid. In otg mode, you can use this bit to determine if the device is connected or disconnected. Note: only ac...

  • Page 833

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 833/1096 otg_fs interrupt register (otg_fs_gotgint) address offset: 0x04 reset value: 0x0000 0000 the application reads this register whenever there is an otg interrupt and clears the bits in this register to clear the otg interrupt. Bit 8...

  • Page 834

    Usb on-the-go full-speed (otg_fs) rm0008 834/1096 doc id 13902 rev 12 bit 18 adtochg: a-device timeout change the core sets this bit to indicate that the a-device has timed out while waiting for the b-device to connect. Note: accessible in both device and host modes. Bit 17 hngdet: host negotiation ...

  • Page 835

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 835/1096 otg_fs ahb configuration register (otg_fs_gahbcfg) address offset: 0x008 reset value: 0x0000 0000 this register can be used to configure the core after power-on or a change in mode. This register mainly contains ahb system-related...

  • Page 836

    Usb on-the-go full-speed (otg_fs) rm0008 836/1096 doc id 13902 rev 12 otg_fs usb configuration register (otg_fs_gusbcfg) address offset: 0x00c reset value: 0x0000 0a00 this register can be used to configure the core after power-on or a changing to host mode or device mode. It contains usb and usb-ph...

  • Page 837

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 837/1096 bit 8 srpcap: srp-capable the application uses this bit to control the otg_fs controller’s srp capabilities. If the core operates as a non-srp-capable b-device, it cannot request the connected a-device (host) to activate v bus and...

  • Page 838

    Usb on-the-go full-speed (otg_fs) rm0008 838/1096 doc id 13902 rev 12 otg_fs reset register (otg_fs_grstctl) address offset: 0x10 reset value: 0x2000 0000 the application uses this register to reset various hardware features inside the core. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1...

  • Page 839

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 839/1096 bit 3 reserved bit 2 fcrst: host frame counter reset the application writes this bit to reset the frame number counter inside the core. When the frame counter is reset, the subsequent sof sent out by the core has a frame number of...

  • Page 840

    Usb on-the-go full-speed (otg_fs) rm0008 840/1096 doc id 13902 rev 12 otg_fs core interrupt register (otg_fs_gintsts) address offset: 0x014 reset value: 0x0400 0020 this register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in th...

  • Page 841

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 841/1096 bit 25 hcint: host channels interrupt the core sets this bit to indicate that an interrupt is pending on one of the channels of the core (in host mode). The application must read the otg_fs_haint register to determine the exact nu...

  • Page 842

    Usb on-the-go full-speed (otg_fs) rm0008 842/1096 doc id 13902 rev 12 bit 14 isoodrp: isochronous out packet dropped interrupt the core sets this bit when it fails to write an isochronous out packet into the rxfifo because the rxfifo does not have enough space to accommodate a maximum size packet fo...

  • Page 843

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 843/1096 bit 3 sof: start of frame in host mode, the core sets this bit to indicate that an sof (fs), or keep-alive (ls) is transmitted on the usb. The application must write a 1 to this bit to clear the interrupt. In device mode, in the c...

  • Page 844

    Usb on-the-go full-speed (otg_fs) rm0008 844/1096 doc id 13902 rev 12 otg_fs interrupt mask register (otg_fs_gintmsk) address offset: 0x018 reset value: 0x0000 0000 this register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt assoc...

  • Page 845

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 845/1096 bits 23:22 reserved bit 21 ipxfrm: incomplete periodic transfer mask 0: masked interrupt 1: unmasked interrupt note: only accessible in host mode. Iisooxfrm: incomplete isochronous out transfer mask 0: masked interrupt 1: unmasked...

  • Page 846

    Usb on-the-go full-speed (otg_fs) rm0008 846/1096 doc id 13902 rev 12 bit 11 usbsuspm: usb suspend mask 0: masked interrupt 1: unmasked interrupt note: only accessible in device mode. Bit 10 esuspm: early suspend mask 0: masked interrupt 1: unmasked interrupt note: only accessible in device mode. Bi...

  • Page 847

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 847/1096 otg_fs receive status debug read/otg status read and pop registers (otg_fs_grxstsr/otg_fs_grxstsp) address offset for read: 0x01c address offset for pop: 0x020 reset value: 0x0000 0000 a read to the receive status debug read regis...

  • Page 848

    Usb on-the-go full-speed (otg_fs) rm0008 848/1096 doc id 13902 rev 12 device mode: otg_fs receive fifo size register (otg_fs_grxfsiz) address offset: 0x024 reset value: 0x0000 0200 the application can program the ram size that must be allocated to the rxfifo. 31 30 29 28 27 26 25 24 23 22 21 20 19 1...

  • Page 849

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 849/1096 otg_fs host non-periodic transmit fifo size register (otg_fs_hnptxfsiz)/endpoint 0 transmit fifo size (otg_fs_dieptxf0) address offset: 0x028 reset value: 0x0000 0200 host mode device mode otg_fs non-periodic transmit fifo/queue s...

  • Page 850

    Usb on-the-go full-speed (otg_fs) rm0008 850/1096 doc id 13902 rev 12 otg_fs general core configuration register (otg_fs_gccfg) address offset: 0x038 reset value: 0x0000 0000 bits 30:24 nptxqtop: top of the non-periodic transmit request queue entry in the non-periodic tx request queue that is curren...

  • Page 851

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 851/1096 otg_fs core id register (otg_fs_cid) address offset: 0x03c reset value:0x00001000 this is a read only register containing the product id. Otg_fs host periodic transmit fifo size register (otg_fs_hptxfsiz) address offset: 0x100 res...

  • Page 852

    Usb on-the-go full-speed (otg_fs) rm0008 852/1096 doc id 13902 rev 12 otg_fs device in endpoint transmit fifo size register (otg_fs_dieptxfx) (x = 1..3, where x is the fifo_number) address offset: 0x104 + (fifo_number – 1) × 0x04 reset value: 0x02000400 28.16.3 host-mode registers bit values in the ...

  • Page 853

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 853/1096 otg_fs host frame interval register (otg_fs_hfir) address offset: 0x404 reset value: 0x0000 ea60 this register stores the frame interval information for the current speed to which the otg_fs controller has enumerated. Bits 1:0 fsl...

  • Page 854

    Usb on-the-go full-speed (otg_fs) rm0008 854/1096 doc id 13902 rev 12 otg_fs host frame number/frame time remaining register (otg_fs_hfnum) address offset: 0x408 reset value: 0x0000 3fff this register indicates the current frame number. It also indicates the time remaining (in terms of the number of...

  • Page 855

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 855/1096 otg_fs host all channels interrupt register (otg_fs_haint) address offset: 0x414 reset value: 0x0000 000 when a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the h...

  • Page 856

    Usb on-the-go full-speed (otg_fs) rm0008 856/1096 doc id 13902 rev 12 otg_fs host all channels interrupt mask register (otg_fs_haintmsk) address offset: 0x418 reset value: 0x0000 0000 the host all channel interrupt mask register works with the host all channel interrupt register to interrupt the app...

  • Page 857

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 857/1096 bits 16:13 ptctl: port test control the application writes a nonzero value to this field to put the port into a test mode, and the corresponding pattern is signaled on the port. 0000: test mode disabled 0001: test_j mode 0010: tes...

  • Page 858

    Usb on-the-go full-speed (otg_fs) rm0008 858/1096 doc id 13902 rev 12 bit 6 pres: port resume the application sets this bit to drive resume signaling on the port. The core continues to drive the resume signal until the application clears this bit. If the core detects a usb remote wakeup sequence, as...

  • Page 859

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 859/1096 otg_fs host channel-x characteristics register (otg_fs_hccharx) (x = 0..7, where x = channel_number) address offset: 0x500 + (channel_number × 0x20) reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13...

  • Page 860

    Usb on-the-go full-speed (otg_fs) rm0008 860/1096 doc id 13902 rev 12 otg_fs host channel-x interrupt register (otg_fs_hcintx) (x = 0..7, where x = channel_number) address offset: 0x508 + (channel_number × 0x20) reset value: 0x0000 0000 this register indicates the status of a channel with respect to...

  • Page 861

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 861/1096 otg_fs host channel-x interrupt mask register (otg_fs_hcintmskx) (x = 0..7, where x = channel_number) address offset: 0x50c + (channel_number × 0x20) reset value: 0x0000 0000 this register reflects the mask for each channel status...

  • Page 862

    Usb on-the-go full-speed (otg_fs) rm0008 862/1096 doc id 13902 rev 12 otg_fs host channel-x transfer size register (otg_fs_hctsizx) (x = 0..7, where x = channel_number) address offset: 0x510 + (channel_number × 0x20) reset value: 0x0000 0000 bit 2 reserved bit 1 chhm: channel halted mask 0: masked i...

  • Page 863

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 863/1096 28.16.4 device-mode registers otg_fs device configuration register (otg_fs_dcfg) address offset: 0x800 reset value: 0x0220 0000 this register configures the core in device mode after power-on or after certain control commands or e...

  • Page 864

    Usb on-the-go full-speed (otg_fs) rm0008 864/1096 doc id 13902 rev 12 otg_fs device control register (otg_fs_dctl) address offset: 0x804 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved pop r gdne cgona k sgo n ak cginak sgi n ak...

  • Page 865

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 865/1096 table 203 contains the minimum duration (according to device state) for which the soft disconnect (sdis) bit must be set for the usb host to detect a device disconnect. To accommodate clock jitter, it is recommended that the appli...

  • Page 866

    Usb on-the-go full-speed (otg_fs) rm0008 866/1096 doc id 13902 rev 12 otg_fs device in endpoint common interrupt mask register (otg_fs_diepmsk) address offset: 0x810 reset value: 0x0000 0000 this register works with each of the otg_fs_diepintx registers for all endpoints to generate an interrupt per...

  • Page 867

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 867/1096 otg_fs device out endpoint common interrupt mask register (otg_fs_doepmsk) address offset: 0x814 reset value: 0x0000 0000 this register works with each of the otg_fs_doepintx registers for all endpoints to generate an interrupt pe...

  • Page 868

    Usb on-the-go full-speed (otg_fs) rm0008 868/1096 doc id 13902 rev 12 otg_fs device all endpoints interrupt register (otg_fs_daint) address offset: 0x818 reset value: 0x0000 0000 when a significant event occurs on an endpoint, a otg_fs_daint register interrupts the application using the device out e...

  • Page 869

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 869/1096 otg_fs all endpoints interrupt mask register (otg_fs_daintmsk) address offset: 0x81c reset value: 0x0000 0000 the otg_fs_daintmsk register works with the device endpoint interrupt register to interrupt the application when an even...

  • Page 870

    Usb on-the-go full-speed (otg_fs) rm0008 870/1096 doc id 13902 rev 12 otg_fs device v bus pulsing time register (otg_fs_dvbuspulse) address offset: 0x082c reset value: 0x0000 05b8 this register specifies the v bus pulsing time during srp. Otg_fs device in endpoint fifo empty interrupt mask register:...

  • Page 871

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 871/1096 otg_fs device control in endpoint 0 control register (otg_fs_diepctl0) address offset: 0x900 reset value: 0x0000 0000 this section describes the otg_fs_diepctl0 register. Nonzero control endpoints use registers for endpoints 1–3. ...

  • Page 872

    Usb on-the-go full-speed (otg_fs) rm0008 872/1096 doc id 13902 rev 12 otg device endpoint-x control register (otg_fs_diepctlx) (x = 1..3, where x = endpoint_number) address offset: 0x900 + (endpoint_number × 0x20) reset value: 0x0000 0000 the application uses this register to control the behavior of...

  • Page 873

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 873/1096 bit 30 epdis: endpoint disable the application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt...

  • Page 874

    Usb on-the-go full-speed (otg_fs) rm0008 874/1096 doc id 13902 rev 12 bit 17 naksts: nak status it indicates the following: 0: the core is transmitting non-nak handshakes based on the fifo status. 1: the core is transmitting nak handshakes on this endpoint. When either the application or the core se...

  • Page 875

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 875/1096 otg_fs device control out endpoint 0 control register (otg_fs_doepctl0) address offset: 0xb00 reset value: 0x0000 8000 this section describes the otg_fs_doepctl0 register. Nonzero control endpoints use registers for endpoints 1–3....

  • Page 876

    Usb on-the-go full-speed (otg_fs) rm0008 876/1096 doc id 13902 rev 12 otg_fs device endpoint-x control register (otg_fs_doepctlx) (x = 1..3, where x = endpoint_number) address offset for out endpoints: 0xb00 + (endpoint_number × 0x20) reset value: 0x0000 0000 the application uses this register to co...

  • Page 877

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 877/1096 bit 30 epdis: endpoint disable the application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt...

  • Page 878

    Usb on-the-go full-speed (otg_fs) rm0008 878/1096 doc id 13902 rev 12 bit 17 naksts: nak status indicates the following: 0: the core is transmitting non-nak handshakes based on the fifo status. 1: the core is transmitting nak handshakes on this endpoint. When either the application or the core sets ...

  • Page 879

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 879/1096 otg_fs device endpoint-x interrupt register (otg_fs_diepintx) (x = 0..3, where x = endpoint_number) address offset: 0x908 + (endpoint_number × 0x20) reset value: 0x0000 0080 this register indicates the status of an endpoint with r...

  • Page 880

    Usb on-the-go full-speed (otg_fs) rm0008 880/1096 doc id 13902 rev 12 otg_fs device endpoint-x interrupt register (otg_fs_doepintx) (x = 0..3, where x = endpoint_number) address offset: 0xb08 + (endpoint_number × 0x20) reset value: 0x0000 0080 this register indicates the status of an endpoint with r...

  • Page 881

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 881/1096 otg_fs device in endpoint 0 transfer size register (otg_fs_dieptsiz0) address offset: 0x910 reset value: 0x0000 0000 the application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using the endpoi...

  • Page 882

    Usb on-the-go full-speed (otg_fs) rm0008 882/1096 doc id 13902 rev 12 otg_fs device out endpoint 0 transfer size register (otg_fs_doeptsiz0) address offset: 0xb10 reset value: 0x0000 0000 the application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using the endpo...

  • Page 883

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 883/1096 otg_fs device endpoint-x transfer size register (otg_fs_dieptsizx) (x = 1..3, where x = endpoint_number) address offset: 0x910 + (endpoint_number × 0x20) reset value: 0x0000 0000 the application must modify this register before en...

  • Page 884

    Usb on-the-go full-speed (otg_fs) rm0008 884/1096 doc id 13902 rev 12 otg_fs device in endpoint transmit fifo status register (otg_fs_dtxfstsx) (x = 0..3, where x = endpoint_number) address offset for in endpoints: 0x918 + (endpoint_number × 0x20) this read-only register contains the free space info...

  • Page 885

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 885/1096 28.16.5 otg_fs power and clock gating control register (otg_fs_pcgcctl) address offset: 0xe00 reset value: 0x0000 0000 this register is available in host and device modes. Stupcnt: setup packet count applies to control out endpoin...

  • Page 886

    Usb on-the-go full-speed (otg_fs) rm0008 886/1096 doc id 13902 rev 12 28.16.6 otg_fs register map the table below gives the usb otg register map and reset values. Table 204. Otg_fs register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6...

  • Page 887

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 887/1096 0x028 otg_fs_hnpt xfsiz/ otg_fs_diep txf0 nptxfd/tx0fd nptxfsa/tx0fsa reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0x02c otg_fs_hnpt xsts res . Nptxqtop nptqxsav nptxfsav reset value 0 0 0 0 0 0 0 0 ...

  • Page 888

    Usb on-the-go full-speed (otg_fs) rm0008 888/1096 doc id 13902 rev 12 0x560 otg_fs_hcc har3 chena chdis oddfrm dad mcnt ep ty p ls d e v re se rv e d ep dir epnum mpsiz reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x580 otg_fs_hcc har4 chena chdis oddfrm dad mcnt ep ty p...

  • Page 889

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 889/1096 0x54c otg_fs_hcin tmsk2 reserved dte r rm frmo rm bberrm txe rrm nyet ac k m nakm st al lm reser v e d chhm xfr c m reset value 0 0 0 0 0 0 0 0 0 0 0x56c otg_fs_hcin tmsk3 reserved dterrm frmo rm b berrm txerrm ny et ac k m na km ...

  • Page 890

    Usb on-the-go full-speed (otg_fs) rm0008 890/1096 doc id 13902 rev 12 0x804 otg_fs_dctl reserved po p r gd n e cgonak s gona k cginak sg ina k tc t l go nst s gi nst s sdi s rw u s ig reset value 0 0 0 0 0 0 0 0 0 0 0 0 0x808 otg_fs_dsts reserved fnsof reserved ee r r enumspd su sp s t s reset value...

  • Page 891

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 891/1096 0x960 otg_fs_diep ctl3 epe na ep dis soddfrm sd0pi d /sevnfrm snak cnak txfnum st all reser v e d ep ty p na ksts eo n u m /d pi d usbae p reserved mpsiz reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x978 tg_f...

  • Page 892: 28.17 Otg_Fs

    Usb on-the-go full-speed (otg_fs) rm0008 892/1096 doc id 13902 rev 12 refer to table 3 on page 50 for the register boundary addresses. 28.17 otg_fs programming model 28.17.1 core initialization the application must perform the core initialization sequence. If the cable is connected during power-up, ...

  • Page 893

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 893/1096 this section explains the initialization of the otg_fs controller after power-on. The application must follow the initialization sequence irrespective of host or device mode operation. All core global registers are initialized acc...

  • Page 894

    Usb on-the-go full-speed (otg_fs) rm0008 894/1096 doc id 13902 rev 12 28.17.2 host initialization to initialize the core as host, the application must perform the following steps: 1. Program the hprtint in the otg_fs_gintmsk register to unmask 2. Program the otg_fs_hcfg register to select full-speed...

  • Page 895

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 895/1096 register to determine the enumeration speed and perform the steps listed in endpoint initialization on enumeration completion on page 912 . At this point, the device is ready to accept sof packets and perform control transfers on ...

  • Page 896

    Usb on-the-go full-speed (otg_fs) rm0008 896/1096 doc id 13902 rev 12 1. When an stall, txerr, bberr or dterr interrupt in otg_fs_hcintx is received for an in or out channel. The application must be able to receive other interrupts (dterr, nak, data, txerr) for the same channel before receiving the ...

  • Page 897

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 897/1096 ● reading the receive fifo the application must ignore all packet statuses other than in data packet (bx0010). Figure 312. Receive fifo read task ● bulk and control out/setup transactions a typical bulk or control out/setup pipeli...

  • Page 898

    Usb on-the-go full-speed (otg_fs) rm0008 898/1096 doc id 13902 rev 12 setup transaction operates in the same way but has only one packet. The assumptions are: – the application is attempting to send two maximum-packet-size packets (transfer size = 1, 024 bytes). – the non-periodic transmit fifo can ...

  • Page 899

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 899/1096 figure 313. Normal bulk/control out/setup and bulk/control in transactions the channel-specific interrupt service routine for bulk and control out/setup transactions is shown in the following code samples. ● interrupt service rout...

  • Page 900

    Usb on-the-go full-speed (otg_fs) rm0008 900/1096 doc id 13902 rev 12 de-allocate channel } else if (stall) { transfer done = 1 unmask chh disable channel } else if (nak or txerr ) { rewind buffer pointers unmask chh disable channel if (txerr) { increment error count unmask ack } else { reset error ...

  • Page 901

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 901/1096 reset error count mask ack } else if (txerr or bberr or stall) { unmask chh disable channel if (txerr) { increment error count unmask ack } } else if (chh) { mask chh if (transfer done or (error_count == 3)) { de-allocate channel ...

  • Page 902

    Usb on-the-go full-speed (otg_fs) rm0008 902/1096 doc id 13902 rev 12 figure 314. Bulk/control in transactions the sequence of operations is as follows: a) initialize channel 2. B) set the chena bit in hcchar2 to write an in request to the non-periodic request queue. C) the core attempts to send an ...

  • Page 903

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 903/1096 f) the core generates the rxflvl interrupt for the transfer completion status entry in the receive fifo. G) the application must read and ignore the receive packet status when the receive packet status is not an in data packet (pk...

  • Page 904

    Usb on-the-go full-speed (otg_fs) rm0008 904/1096 doc id 13902 rev 12 figure 315. Normal interrupt out/in transactions ● interrupt service routine for interrupt out/in transactions a) interrupt out unmask (nak/txerr/stall/xfrc/frmor) if (xfrc) { reset error count mask ack de-allocate channel } else ...

  • Page 905

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 905/1096 disable channel if (stall) { transfer done = 1 } } else if (nak or txerr) { rewind buffer pointers reset error count mask ack unmask chh disable channel } else if (chh) { mask chh if (transfer done or (error_count == 3)) { de-allo...

  • Page 906

    Usb on-the-go full-speed (otg_fs) rm0008 906/1096 doc id 13902 rev 12 } } else if (stall or frmor or nak or dterr or bberr) { mask ack unmask chh disable channel if (stall or bberr) { reset error count transfer done = 1 } else if (!Frmor) { reset error count } } else if (txerr) { increment error cou...

  • Page 907

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 907/1096 ● interrupt in transactions the assumptions are: – the application is attempting to receive one packet (up to 1 maximum packet size) in every frame, starting with odd (transfer size = 1 024 bytes). – the receive fifo can hold at l...

  • Page 908

    Usb on-the-go full-speed (otg_fs) rm0008 908/1096 doc id 13902 rev 12 ● isochronous out transactions a typical isochronous out operation is shown in figure 316 . The assumptions are: – the application is attempting to send one packet every frame (up to 1 maximum packet size), starting with an odd fr...

  • Page 909

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 909/1096 figure 316. Normal isochronous out/in transactions ● interrupt service routine for isochronous out/in transactions code sample: isochronous out unmask (frmor/xfrc) if (xfrc) { de-allocate channel } else if (frmor) { unmask chh dis...

  • Page 910

    Usb on-the-go full-speed (otg_fs) rm0008 910/1096 doc id 13902 rev 12 else if (chh) { mask chh de-allocate channel } code sample: isochronous in unmask (txerr/xfrc/frmor/bberr) if (xfrc or frmor) { if (xfrc and (otg_fs_hctsizx.Pktcnt == 0)) { reset error count de-allocate channel } else { unmask chh...

  • Page 911

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 911/1096 ● isochronous in transactions the assumptions are: – the application is attempting to receive one packet (up to 1 maximum packet size) in every frame starting with the next odd frame (transfer size = 1 024 bytes). – the receive fi...

  • Page 912

    Usb on-the-go full-speed (otg_fs) rm0008 912/1096 doc id 13902 rev 12 the channel. Port babble occurs if the core continues to receive data from the device at eof2 (the end of frame 2, which is very close to sof). When otg_fs controller detects a packet babble, it stops writing data into the rx buff...

  • Page 913

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 913/1096 at this point, the device is ready to receive sof packets and is configured to perform control transfers on control endpoint 0. Endpoint initialization on setaddress command this section describes what the application must do when...

  • Page 914

    Usb on-the-go full-speed (otg_fs) rm0008 914/1096 doc id 13902 rev 12 1. In the endpoint to be deactivated, clear the usb active endpoint bit in the otg_fs_diepctlx register (for in or bidirectional endpoints) or the otg_fs_doepctlx register (for out or bidirectional endpoints). 2. Once the endpoint...

  • Page 915

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 915/1096 completed. After this entry is popped from the receive fifo, the core asserts a transfer completed interrupt on the specified out endpoint. 5. After the data payload is popped from the receive fifo, the rxflvl interrupt (otg_fs_gi...

  • Page 916

    Usb on-the-go full-speed (otg_fs) rm0008 916/1096 doc id 13902 rev 12 determine the correct number of setup packets received in the setup stage of a control transfer. – stupcnt = 3 in otg_fs_doeptsizx 2. The application must always allocate some extra space in the receive data fifo, to be able to re...

  • Page 917

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 917/1096 figure 318. Processing a setup packet ● handling more than three back-to-back setup packets per the usb 2.0 specification, normally, during a setup packet error, a host does not send more than three back-to-back setup packets to t...

  • Page 918

    Usb on-the-go full-speed (otg_fs) rm0008 918/1096 doc id 13902 rev 12 1. To stop receiving any kind of data in the receive fifo, the application must set the global out nak bit by programming the following field: – sgonak = 1 in otg_fs_dctl 2. Wait for the assertion of the gonakeff interrupt in otg_...

  • Page 919

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 919/1096 1. Before setting up an out transfer, the application must allocate a buffer in the memory to accommodate all data to be received as part of the out transfer. 2. For out transfers, the transfer size field in the endpoint’s transfe...

  • Page 920

    Usb on-the-go full-speed (otg_fs) rm0008 920/1096 doc id 13902 rev 12 6. The out data transfer completed pattern for an out endpoint is written to the receive fifo on one of the following conditions: – the transfer size is 0 and the packet count is 0 – the last out data packet written to the receive...

  • Page 921

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 921/1096 otg_fs_doeptsizx with the data pid of the last isochronous out data packet read from the receive fifo. Application programming sequence: 1. Program the otg_fs_doeptsizx register for the transfer size and the corresponding packet c...

  • Page 922

    Usb on-the-go full-speed (otg_fs) rm0008 922/1096 doc id 13902 rev 12 (iisooxfrm in otg_fs_gintsts), indicating that an xfrc interrupt (in otg_fs_doepintx) is not asserted on at least one of the isochronous out endpoints. At this point, the endpoint with the incomplete transfer remains enabled, but ...

  • Page 923

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 923/1096 examples this section describes and depicts some fundamental transfer types and scenarios. ● bulk out transaction figure 319 depicts the reception of a single bulk out data packet from the usb to the ahb and describes the events i...

  • Page 924

    Usb on-the-go full-speed (otg_fs) rm0008 924/1096 doc id 13902 rev 12 in data transfers ● packet write this section describes how the application writes data packets to the endpoint fifo when dedicated transmit fifos are enabled. 1. The application can either choose the polling or the interrupt mode...

  • Page 925

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 925/1096 1. To stop transmitting any data on a particular in endpoint, the application must set the in nak bit. To set this bit, the following field must be programmed. – snak = 1 in otg_fs_diepctlx 2. Wait for assertion of the inepne inte...

  • Page 926

    Usb on-the-go full-speed (otg_fs) rm0008 926/1096 doc id 13902 rev 12 ● generic non-periodic in data transfers application requirements: 1. Before setting up an in transfer, the application must ensure that all data to be transmitted as part of the in transfer are part of a single buffer. 2. For in ...

  • Page 927

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 927/1096 handshake, the packet count for the endpoint is decremented by one, until the packet count is zero. The packet count is not decremented on a timeout. 5. For zero length packets (indicated by an internal zero length flag), the core...

  • Page 928

    Usb on-the-go full-speed (otg_fs) rm0008 928/1096 doc id 13902 rev 12 2. The application can only schedule data transfers one frame at a time. – (mcnt – 1) × mpsiz ≤ xfersiz ≤ mcnt × mpsiz – pktcnt = mcnt (in otg_fs_dieptsizx) – if xfersiz packet. – note that: mcnt is in otg_fs_dieptsizx, mpsiz is i...

  • Page 929

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 929/1096 application programming sequence: 1. Program the otg_fs_diepctlx register with the endpoint characteristics and set the cnak and epena bits. 2. Write the data to be transmitted in the next frame to the transmit fifo. 3. Asserting ...

  • Page 930

    Usb on-the-go full-speed (otg_fs) rm0008 930/1096 doc id 13902 rev 12 application programming sequence: 1. The application can ignore the in token received when txfifo empty interrupt in otg_fs_diepintx on any isochronous in endpoint, as it eventually results in an incomplete isochronous in transfer...

  • Page 931

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 931/1096 application receives this interrupt, it must set the stall bit in the corresponding endpoint control register, and clear this interrupt. 28.17.7 worst case response time when the otg_fs controller acts as a device, there is a wors...

  • Page 932

    Usb on-the-go full-speed (otg_fs) rm0008 932/1096 doc id 13902 rev 12 figure 320. Trdt max timing case 28.17.8 otg programming model the otg_fs controller is an otg device supporting hnp and srp. When the core is connected to an “a” plug, it is referred to as an a-device. When the core is connected ...

  • Page 933

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 933/1096 figure 321. A-device srp 1. Drv_vbus = v bus drive signal to the phy vbus_valid = v bus valid signal from phy a_valid = a-peripheral v bus level signal to phy d+ = data plus line d- = data minus line 1. To save power, the applicat...

  • Page 934

    Usb on-the-go full-speed (otg_fs) rm0008 934/1096 doc id 13902 rev 12 figure 322. B-device srp 1. Vbus_valid = v bus valid signal from phy b_valid = b-peripheral valid session to phy dischrg_vbus = discharge signal to phy sess_end = session end signal to phy chrg_vbus = charge v bus signal to phy dp...

  • Page 935

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 935/1096 a-device host negotiation protocol hnp switches the usb host role from the a-device to the b-device. The application must set the hnp-capable bit in the core usb configuration register to enable the otg_fs controller to perform hn...

  • Page 936

    Usb on-the-go full-speed (otg_fs) rm0008 936/1096 doc id 13902 rev 12 6. In negotiated mode, the otg_fs controller detects the suspend, disconnects, and switches back to the host role. The otg_fs controller asserts the dm pull down and dm pull down in the phy to indicate its assumption of the host r...

  • Page 937

    Rm0008 usb on-the-go full-speed (otg_fs) doc id 13902 rev 12 937/1096 the a-device responds by activating its otg_fs_dp pull-up resistor within 3 ms of detecting se0. The otg_fs controller detects this as a connect. The otg_fs controller sets the host negotiation success status change interrupt in t...

  • Page 938: Dma Controller

    Ethernet (eth): media access control (mac) with dma controller rm0008 938/1096 doc id 13902 rev 12 29 ethernet (eth): media access control (mac) with dma controller low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and ...

  • Page 939

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 939/1096 29.2.1 mac core features ● supports 10/100 mbit/s data transfer rates with external phy interfaces ● ieee 802.3-compliant mii interface to communicate with an external fast ethernet phy ● supports both...

  • Page 940

    Ethernet (eth): media access control (mac) with dma controller rm0008 940/1096 doc id 13902 rev 12 ● option to filter all error frames on reception and not forward them to the application in store-and-forward mode ● option to forward under-sized good frames ● supports statistics by generating pulses...

  • Page 941: 29.3 Ethernet

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 941/1096 29.3 ethernet pins table 205 shows the mac signals and the corresponding mii/rmii default or remapped signals. It also indicates the pins onto which the signals are input or output, and the pin configu...

  • Page 942: 29.4

    Ethernet (eth): media access control (mac) with dma controller rm0008 942/1096 doc id 13902 rev 12 29.4 ethernet functional description: smi, mii and rmii the ethernet peripheral consists of a mac 802.3 (media access control) with a dedicated dma controller. It supports both default media-independen...

  • Page 943

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 943/1096 the application can select one of the 32 phys and one of the 32 registers within any phy and send control data or receive status information. Only one register in one phy can be addressed at any given ...

  • Page 944

    Ethernet (eth): media access control (mac) with dma controller rm0008 944/1096 doc id 13902 rev 12 drives high-impedance on the mdio line for the 2 bits of ta. The phy device must drive a high-impedance state on the first bit of ta, a zero bit on the second one. For a write transaction, the mac cont...

  • Page 945

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 945/1096 figure 328. Mdio timing and frame structure - read cycle smi clock selection the mac initiates the management write/read operation. The smi clock is a divided clock whose source is the application cloc...

  • Page 946

    Ethernet (eth): media access control (mac) with dma controller rm0008 946/1096 doc id 13902 rev 12 figure 329. Media independent interface signals ● mii_tx_clk: continuous clock that provides the timing reference for the tx data transfer. The nominal frequency is: 2.5 mhz at 10 mbit/s speed; 25 mhz ...

  • Page 947

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 947/1096 that follows the final nibble. In order to receive the frame correctly, the mii_rx_dv signal must encompass the frame, starting no later than the sfd field. ● mii_rx_er: receive error must be asserted ...

  • Page 948

    Ethernet (eth): media access control (mac) with dma controller rm0008 948/1096 doc id 13902 rev 12 figure 330. Mii clock sources 29.4.3 reduced media-independent interface: rmii the reduced media-independent interface (rmii) specification reduces the pin count between the stm32f100xx ethernet periph...

  • Page 949

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 949/1096 rmii clock sources as described in the rmii clock sources section, the stm32f107xx could provide this 50 mhz clock signal on its mco output pin and you then have to configure this output value through ...

  • Page 950: 29.5

    Ethernet (eth): media access control (mac) with dma controller rm0008 950/1096 doc id 13902 rev 12 to save a pin, the two input clock signals, rmii_ref_ck and mii_rx_clk, are multiplexed on the same gpio pin. 29.5 ethernet functional description: mac 802.3 the ieee 802.3 international standard for l...

  • Page 951

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 951/1096 figure 335 and figure 336 describe the frame structure (untagged and tagged) that includes the following fields: ● preamble: 7-byte field used for synchronization purposes (pls circuitry) hexadecimal v...

  • Page 952

    Ethernet (eth): media access control (mac) with dma controller rm0008 952/1096 doc id 13902 rev 12 hexadecimal). This constant field is used to distinguish tagged and untagged mac frames. – 2-byte field containing the tag control information field subdivided as follows: a 3- bit user priority, a can...

  • Page 953

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 953/1096 figure 335. Mac frame format figure 336. Tagged mac frame format each byte of the mac frame, except the fcs field, is transmitted low-order bit first. An invalid mac frame is defined by one of the foll...

  • Page 954

    Ethernet (eth): media access control (mac) with dma controller rm0008 954/1096 doc id 13902 rev 12 29.5.2 mac frame transmission the dma controls all transactions for the transmit path. Ethernet frames read from the system memory are pushed into the fifo by the dma. The frames are then popped out an...

  • Page 955

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 955/1096 the crc generator calculates the 32-bit crc for the fcs field of the ethernet frame. The encoding is defined by the following polynomial. Transmit protocol the mac controls the operation of ethernet fr...

  • Page 956

    Ethernet (eth): media access control (mac) with dma controller rm0008 956/1096 doc id 13902 rev 12 configured for 96 bit times, the mac follows the rule of deference specified in section 4.2.3.2.1 of the ieee 802.3 specification. The mac resets its ifg counter if a carrier is detected during the fir...

  • Page 957

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 957/1096 frame is being transmitted. As soon as the first frame has been transferred and the status is received from the mac, it is pushed to the dma. If the dma has already completed sending the second packet ...

  • Page 958

    Ethernet (eth): media access control (mac) with dma controller rm0008 958/1096 doc id 13902 rev 12 2 you must make sure the transmit fifo is deep enough to store a complete frame before that frame is transferred to the mac core transmitter. If the fifo depth is less than the input ethernet frame siz...

  • Page 959

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 959/1096 the checksum is calculated for the tcp, udp, or icmp payload and inserted into its corresponding field in the header. It can work in the following two modes: – in the first mode, the tcp, udp, or icmpv...

  • Page 960

    Ethernet (eth): media access control (mac) with dma controller rm0008 960/1096 doc id 13902 rev 12 mii/rmii transmit timing diagrams figure 338. Transmission with no collision figure 339. Transmission with collision figure 340 shows a frame transmission in mii and rmii. Mii_tx_clk mii_tx_en mii_txd[...

  • Page 961

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 961/1096 figure 340. Frame transmission in mmi and rmii modes 29.5.3 mac frame reception the mac received frames are pushes into the rx fifo. The status (fill level) of this fifo is indicated to the dma once it...

  • Page 962

    Ethernet (eth): media access control (mac) with dma controller rm0008 962/1096 doc id 13902 rev 12 if the received frame length/type field is less than 0x600 and if the mac is programmed for the auto crc/pad stripping option, the mac sends the data of the frame to rxfifo up to the count specified in...

  • Page 963

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 963/1096 receive frame controller if the ra bit is reset in the mac csr frame filter register, the mac performs frame filtering based on the destination/source address (the application still needs to perform an...

  • Page 964

    Ethernet (eth): media access control (mac) with dma controller rm0008 964/1096 doc id 13902 rev 12 meanwhile, if another pause frame is detected with a zero pause time value, the mac resets the pause time and manages this new pause request. If the received control frame matches neither the type fiel...

  • Page 965

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 965/1096 figure 341. Receive bit order figure 342. Reception with no error figure 343. Reception with errors d0 d1 d2 d3 lsb mii_rxd[3:0] msb d0 d1 lsb msb rmii_rxd[1:0] di-bit stream nibble stream ai15633 mii_...

  • Page 966

    Ethernet (eth): media access control (mac) with dma controller rm0008 966/1096 doc id 13902 rev 12 figure 344. Reception with false carrier indication 29.5.4 mac interrupts interrupts can be generated from the mac core as a result of various events. The eth_macsr register describes the events that c...

  • Page 967

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 967/1096 unicast destination address filter the mac supports up to 4 mac addresses for unicast perfect filtering. If perfect filtering is selected (hu bit in the frame filter register is reset), the mac compare...

  • Page 968

    Ethernet (eth): media access control (mac) with dma controller rm0008 968/1096 doc id 13902 rev 12 broadcast address filter the mac does not filter any broadcast frames in the default mode. However, if the mac is programmed to reject all broadcast frames by setting the bfd bit in the frame filter re...

  • Page 969

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 969/1096 29.5.6 mac loopback mode the mac supports loopback of transmitted frames onto its receiver. By default, the mac loopback function is disabled, but this feature can be enabled by programming the loopbac...

  • Page 970

    Ethernet (eth): media access control (mac) with dma controller rm0008 970/1096 doc id 13902 rev 12 section 29.8: ethernet register descriptions describes the various counters and lists the addresses of each of the statistics counters. This address is used for read/write accesses to the desired trans...

  • Page 971

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 971/1096 wakeup frame filter register to reach the last register. Each read/write points the wakeup frame filter register to the next filter register. Figure 346. Wakeup frame filter register ● filter i byte ma...

  • Page 972

    Ethernet (eth): media access control (mac) with dma controller rm0008 972/1096 doc id 13902 rev 12 mask determines which bytes of the frame must be examined. The thirty-first bit of byte mask must be set to zero. The wakeup frame is checked only for length error, fcs error, dribble bit error, mii er...

  • Page 973

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 973/1096 1. Disable the transmit dma and wait for any previous frame transmissions to complete. These transmissions can be detected when the transmit interrupt eth_dmasr register[0] is received. 2. Disable the ...

  • Page 974

    Ethernet (eth): media access control (mac) with dma controller rm0008 974/1096 doc id 13902 rev 12 figure 347. Networked time synchronization 1. The master broadcasts ptp sync messages to all its nodes. The sync message contains the master’s reference time information. The time at which this message...

  • Page 975

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 975/1096 be greater than or equal to the resolution of time stamp counter. The synchronization accuracy target between the master node and the slaves is around 100 ns. The generation, update and modification of...

  • Page 976

    Ethernet (eth): media access control (mac) with dma controller rm0008 976/1096 doc id 13902 rev 12 the accumulator and the addend are 32-bit registers. Here, the accumulator acts as a high- precision frequency multiplier or divider. Figure 348 shows this algorithm. Figure 348. System time update usi...

  • Page 977

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 977/1096 the algorithm is as follows: ● at time mastersynctime (n) the master sends the slave clock a sync message. The slave receives this message when its local clock is slaveclocktime (n) and computes master...

  • Page 978

    Ethernet (eth): media access control (mac) with dma controller rm0008 978/1096 doc id 13902 rev 12 programming steps for system time update in the coarse correction method to synchronize or update the system time in one process (coarse correction method), perform the following steps: 1. Write the of...

  • Page 979: 29.6

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 979/1096 ptp pulse-per-second output signal this ptp pulse output is used to check the synchronization between all nodes in the network. To be able to test the difference between the local slave clock and the m...

  • Page 980

    Ethernet (eth): media access control (mac) with dma controller rm0008 980/1096 doc id 13902 rev 12 figure 351. Descriptor ring and chain structure 29.6.1 initialization of a transfer using dma initialization for the mac is as follows: 1. Write to eth_dmabmr to set stm32f107xx bus access parameters. ...

  • Page 981

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 981/1096 incr4, incr8, incr16 and single transactions. Otherwise (no fixed-length burst), it transfers data using incr (undefined length) and single transactions. The receive dma initiates a data transfer only ...

  • Page 982

    Ethernet (eth): media access control (mac) with dma controller rm0008 982/1096 doc id 13902 rev 12 databus width. If a descriptor is marked as last, then the buffer may not be full (as indicated by the buffer size in rdes1). To compute the amount of valid data in this final buffer, the driver must r...

  • Page 983

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 983/1096 unavailable (eth_dmasr register[2]) and normal interrupt summary (eth_dmasr register[16]) bits are set. The transmit engine proceeds to step 9. 4. If the acquired descriptor is flagged as owned by dma ...

  • Page 984

    Ethernet (eth): media access control (mac) with dma controller rm0008 984/1096 doc id 13902 rev 12 figure 352. Txdma operation in default mode txdma operation: osf mode while in the run state, the transmit process can simultaneously acquire two frames without closing the status descriptor of the fir...

  • Page 985

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 985/1096 1. The dma operates as described in steps 1–6 of the txdma (default mode). 2. Without closing the previous frame’s last descriptor, the dma fetches the next descriptor. 3. If the dma owns the acquired ...

  • Page 986

    Ethernet (eth): media access control (mac) with dma controller rm0008 986/1096 doc id 13902 rev 12 figure 353. Txdma operation in osf mode transmit frame processing the transmit dma expects that the data buffers contain complete ethernet frames, excluding preamble, pad bytes, and fcs fields. The da,...

  • Page 987

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 987/1096 indicates the last buffer of the frame. After the last buffer of the frame has been transmitted, the dma writes back the final status information to the transmit descriptor 0 (tdes0) word of the descri...

  • Page 988

    Ethernet (eth): media access control (mac) with dma controller rm0008 988/1096 doc id 13902 rev 12 ● tdes0: transmit descriptor word0 the application software has to program the control bits [30:26]+[23:20] plus the own bit [31] during descriptor initialization. When the dma updates the descriptor (...

  • Page 989

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 989/1096 bit 20 tch: second address chained when set, this bit indicates that the second address in the descriptor is the next descriptor address rather than the second buffer address. When tdes0[20] is set, tb...

  • Page 990

    Ethernet (eth): media access control (mac) with dma controller rm0008 990/1096 doc id 13902 rev 12 ● tdes1: transmit descriptor word1 bit 10 nc: no carrier when set, this bit indicates that the carrier sense signal form the phy was not asserted during transmission. Bit 9 lco: late collision when set...

  • Page 991

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 991/1096 ● tdes2: transmit descriptor word2 tdes2 contains the address pointer to the first buffer of the descriptor or it contains time stamp data. ● tdes3: transmit descriptor word3 tdes3 contains the address...

  • Page 992

    Ethernet (eth): media access control (mac) with dma controller rm0008 992/1096 doc id 13902 rev 12 1. The cpu sets up receive descriptors (rdes0-rdes3) and sets the own bit (rdes0[31]). 2. Once the sr (eth_dmaomr register[1]) bit is set, the dma enters the run state. While in the run state, the dma ...

  • Page 993

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 993/1096 figure 355. Receive dma operation (re-)fetch next descriptor (ahb) error? No own bit set? Yes yes stop rxdma start rxdma start (ahb) error? No rxdma suspended yes frame data available ? Wait for frame ...

  • Page 994

    Ethernet (eth): media access control (mac) with dma controller rm0008 994/1096 doc id 13902 rev 12 receive descriptor acquisition the receive engine always attempts to acquire an extra descriptor in anticipation of an incoming frame. Descriptor acquisition is attempted if any of the following condit...

  • Page 995

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 995/1096 rx dma descriptors the descriptor structure consists of four 32-bit words (16 bytes). These are shown in figure 356 . The bit descriptions of rdes0, rdes1, rdes2 and rdes3 are given below. Figure 356. ...

  • Page 996

    Ethernet (eth): media access control (mac) with dma controller rm0008 996/1096 doc id 13902 rev 12 bit 15 es: error summary indicates the logical or of the following bits: – rdes0[1]: crc error – rdes0[3]: receive error – rdes0[4]: watchdog timeout – rdes0[6]: late collision – rdes0[7]: giant frame ...

  • Page 997

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 997/1096 bits 5, 7, and 0 reflect the conditions discussed in table 213 . Bit 3 re: receive error when set, this bit indicates that the rx_err signal is asserted while rx_dv is asserted during frame reception. ...

  • Page 998

    Ethernet (eth): media access control (mac) with dma controller rm0008 998/1096 doc id 13902 rev 12 ● rdes1: receive descriptor word1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dic rbs2 rbs2 rer rch reser v ed rbs rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw...

  • Page 999

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 999/1096 ● rdes2: receive descriptor word2 rdes2 contains the address pointer to the first data buffer in the descriptor, or it contains time stamp data. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13...

  • Page 1000

    Ethernet (eth): media access control (mac) with dma controller rm0008 1000/1096 doc id 13902 rev 12 ● rdes3: receive descriptor word3 rdes3 contains the address pointer either to the second data buffer in the descriptor or to the next descriptor, or it contains time stamp data. 29.6.9 dma interrupts...

  • Page 1001: 29.7 Ethernet

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 1001/1096 interrupt. Even then, a new interrupt is generated, due to the active or pending receive buffer unavailable interrupt. Figure 357. Interrupt scheme 29.7 ethernet interrupts the ethernet controller has...

  • Page 1002: 29.8

    Ethernet (eth): media access control (mac) with dma controller rm0008 1002/1096 doc id 13902 rev 12 eth_dmaier register. This timer is disabled before it runs out, when a frame is transferred to memory and the rs is set because it is enabled for that descriptor. Note: reading the pmt control and sta...

  • Page 1003

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 1003/1096 bits 19:17 ifg: interframe gap these bits control the minimum interframe gap between frames during transmission. 000: 96 bit times 001: 88 bit times 010: 80 bit times …. 111: 40 bit times note: in hal...

  • Page 1004

    Ethernet (eth): media access control (mac) with dma controller rm0008 1004/1096 doc id 13902 rev 12 bit 7 apcs: automatic pad/crc stripping when this bit is set, the mac strips the pad/fcs field on incoming frames only if the length’s field value is less than or equal to 1 500 bytes. All received fr...

  • Page 1005

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 1005/1096 ethernet mac frame filter register (eth_macffr) address offset: 0x0004 reset value: 0x0000 0000 the mac frame filter register contains the filter controls for receiving frames. Some of the controls fr...

  • Page 1006

    Ethernet (eth): media access control (mac) with dma controller rm0008 1006/1096 doc id 13902 rev 12 ethernet mac hash table high register (eth_machthr) address offset: 0x0008 reset value: 0x0000 0000 the 64-bit hash table is used for group address filtering. For hash filtering, the contents of the d...

  • Page 1007

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 1007/1096 the hash table high register contains the higher 32 bits of the multicast hash table. Ethernet mac hash table low register (eth_machtlr) address offset: 0x000c reset value: 0x0000 0000 the hash table ...

  • Page 1008

    Ethernet (eth): media access control (mac) with dma controller rm0008 1008/1096 doc id 13902 rev 12 ethernet mac mii data register (eth_macmiidr) address offset: 0x0014 reset value: 0x0000 0000 the mac mii data register stores write data to be written to the phy register located at the address speci...

  • Page 1009

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 1009/1096 transferred onto the cable. The host must make sure that the busy bit is cleared before writing to the register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p...

  • Page 1010

    Ethernet (eth): media access control (mac) with dma controller rm0008 1010/1096 doc id 13902 rev 12 ethernet mac vlan tag register (eth_macvlantr) address offset: 0x001c reset value: 0x0000 0000 the vlan tag register contains the ieee 802.1q vlan tag to identify the vlan frames. The mac compares the...

  • Page 1011

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 1011/1096 ethernet mac remote wakeup frame filter register (eth_macrwuffr) address offset: 0x0028 reset value: 0x0000 0000 this is the address through which the remote wakeup frame filter registers are written/...

  • Page 1012

    Ethernet (eth): media access control (mac) with dma controller rm0008 1012/1096 doc id 13902 rev 12 ethernet mac pmt control and status register (eth_macpmtcsr) address offset: 0x002c reset value: 0x0000 0000 the eth_macpmtcsr programs the request wakeup events and monitors the wakeup events. 31 30 ...

  • Page 1013

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 1013/1096 ethernet mac interrupt status register (eth_macsr) address offset: 0x0038 reset value: 0x0000 0000 the eth_macsr register contents identify the events in the mac that can generate an interrupt. 15 14 ...

  • Page 1014

    Ethernet (eth): media access control (mac) with dma controller rm0008 1014/1096 doc id 13902 rev 12 ethernet mac interrupt mask register (eth_macimr) address offset: 0x003c reset value: 0x0000 0000 the eth_macimr register bits make it possible to mask the interrupt signal due to the corresponding ev...

  • Page 1015

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 1015/1096 ethernet mac address 0 low register (eth_maca0lr) address offset: 0x0044 reset value: 0xffff ffff the mac address 0 low register holds the lower 32 bits of the 6-byte first mac address of the station....

  • Page 1016

    Ethernet (eth): media access control (mac) with dma controller rm0008 1016/1096 doc id 13902 rev 12 ethernet mac address1 low register (eth_maca1lr) address offset: 0x004c reset value: 0xffff ffff the mac address 1 low register holds the lower 32 bits of the 6-byte second mac address of the station....

  • Page 1017

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 1017/1096 ethernet mac address 2 low register (eth_maca2lr) address offset: 0x0054 reset value: 0xffff ffff the mac address 2 low register holds the lower 32 bits of the 6-byte second mac address of the station...

  • Page 1018

    Ethernet (eth): media access control (mac) with dma controller rm0008 1018/1096 doc id 13902 rev 12 ethernet mac address 3 low register (eth_maca3lr) address offset: 0x005c reset value: 0xffff ffff the mac address 3 low register holds the lower 32 bits of the 6-byte second mac address of the station...

  • Page 1019

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 1019/1096 29.8.2 mmc register description ethernet mmc control register (eth_mmccr) address offset: 0x0100 reset value: 0x0000 0000 the ethernet mmc control register establishes the operating mode of the manage...

  • Page 1020

    Ethernet (eth): media access control (mac) with dma controller rm0008 1020/1096 doc id 13902 rev 12 ethernet mmc transmit interrupt register (eth_mmctir) address offset: 0x0108 reset value: 0x0000 0000 the ethernet mmc transmit interrupt register maintains the interrupts generated when transmit stat...

  • Page 1021

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 1021/1096 ethernet mmc receive interrupt mask register (eth_mmcrimr) address offset: 0x010c reset value: 0x0000 0000 the ethernet mmc receive interrupt mask register maintains the masks for interrupts generated...

  • Page 1022

    Ethernet (eth): media access control (mac) with dma controller rm0008 1022/1096 doc id 13902 rev 12 ethernet mmc transmitted good frames after a single collision counter register (eth_mmctgfsccr) address offset: 0x014c reset value: 0x0000 0000 this register contains the number of successfully transm...

  • Page 1023

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 1023/1096 ethernet mmc transmitted good frames counter register (eth_mmctgfcr) address offset: 0x0168 reset value: 0x0000 0000 this register contains the number of good frames transmitted. Ethernet mmc received...

  • Page 1024

    Ethernet (eth): media access control (mac) with dma controller rm0008 1024/1096 doc id 13902 rev 12 mmc received good unicast frames counter register (eth_mmcrgufcr) address offset: 0x01c4 reset value: 0x0000 0000 this register contains the number of good unicast frames received. 29.8.3 ieee 1588 ti...

  • Page 1025

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 1025/1096 address offset: 0x0704 reset value: 0x0000 0000 this register contains the 8-bit value by which the subsecond register is incremented. In coarse update mode (tsfcu bit in eth_ptptscr), the value in th...

  • Page 1026

    Ethernet (eth): media access control (mac) with dma controller rm0008 1026/1096 doc id 13902 rev 12 ethernet ptp time stamp low register (eth_ptptslr) address offset: 0x070c reset value: 0x0000 0000 this register contains the least significant (lower) 32 time bits. This read-only register contains t...

  • Page 1027

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 1027/1096 ethernet ptp time stamp low update register (eth_ptptslur) address offset: 0x0714 reset value: 0x0000 0000 this register contains the least significant (lower) 32 bits of the time to be written to, ad...

  • Page 1028

    Ethernet (eth): media access control (mac) with dma controller rm0008 1028/1096 doc id 13902 rev 12 ethernet ptp target time high register (eth_ptptthr) address offset: 0x071c reset value: 0x0000 0000 this register contains the higher 32 bits of time to be compared with the system time for interrupt...

  • Page 1029

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 1029/1096 ethernet dma bus mode register (eth_dmabmr) address offset: 0x1000 reset value: 0x0000 2101 the bus mode register establishes the bus operating modes for the dma. 31 30 29 28 27 26 25 24 23 22 21 20 1...

  • Page 1030

    Ethernet (eth): media access control (mac) with dma controller rm0008 1030/1096 doc id 13902 rev 12 ethernet dma transmit poll demand register (eth_dmatpdr) address offset: 0x1004 reset value: 0x0000 0000 this register is used by the application to instruct the dma to poll the transmit descriptor li...

  • Page 1031

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 1031/1096 ehernet dma receive poll demand register (eth_dmarpdr) address offset: 0x1008 reset value: 0x0000 0000 this register is used by the application to instruct the dma to poll the receive descriptor list....

  • Page 1032

    Ethernet (eth): media access control (mac) with dma controller rm0008 1032/1096 doc id 13902 rev 12 transmission has stopped. Once transmission has stopped, the eth_dmatdlar register can be written before the transmission start command is given. Ethernet dma status register (eth_dmasr) address offse...

  • Page 1033

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 1033/1096 bits 25:23 ebs: error bits status these bits indicate the type of error that caused a bus error (error response on the ahb interface). Valid only with the fatal bus error bit (eth_dmasr register [13])...

  • Page 1034

    Ethernet (eth): media access control (mac) with dma controller rm0008 1034/1096 doc id 13902 rev 12 bit 15 ais: abnormal interrupt summary the abnormal interrupt summary bit value is the logical or of the following when the corresponding interrupt bits are enabled in the eth_dmaier register: – eth_d...

  • Page 1035

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 1035/1096 ethernet dma operation mode register (eth_dmaomr) address offset: 0x1018 reset value: 0x0000 0000 the operation mode register establishes the transmit and receive operating modes and commands. The eth...

  • Page 1036

    Ethernet (eth): media access control (mac) with dma controller rm0008 1036/1096 doc id 13902 rev 12 bit 21 tsf: transmit store and forward when this bit is set, transmission starts when a full frame resides in the transmit fifo. When this bit is set, the ttc values specified by the eth_dmaomr regist...

  • Page 1037

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 1037/1096 bit 6 fugf: forward undersized good frames when this bit is set, the rx fifo forwards undersized frames (frames with no error and length less than 64 bytes) including pad-bytes and crc). When this bit...

  • Page 1038

    Ethernet (eth): media access control (mac) with dma controller rm0008 1038/1096 doc id 13902 rev 12 ethernet dma interrupt enable register (eth_dmaier) address offset: 0x101c reset value: 0x0000 0000 the interrupt enable register enables the interrupts reported by eth_dmasr. Setting a bit to 1 enabl...

  • Page 1039

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 1039/1096 the ethernet interrupt is generated only when the tsts or pmts bits of the dma status register is asserted with their corresponding interrupt are unmasked, or when the nis/ais status bit is asserted a...

  • Page 1040

    Ethernet (eth): media access control (mac) with dma controller rm0008 1040/1096 doc id 13902 rev 12 ethernet dma missed frame and buffer overflow counter register (eth_dmamfbocr) address offset: 0x1020 reset value: 0x0000 0000 the dma maintains two counters to track the number of missed frames durin...

  • Page 1041

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 1041/1096 ethernet dma current host receive descriptor register (eth_dmachrdr) address offset: 0x104c reset value: 0x0000 0000 the current host receive descriptor register points to the start address of the cur...

  • Page 1042

    Ethernet (eth): media access control (mac) with dma controller rm0008 1042/1096 doc id 13902 rev 12 29.8.5 ethernet register maps table 214 gives the eth register map and reset values. Table 214. Ethernet register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1...

  • Page 1043

    Rm0008 ethernet (eth): media access control (mac) with dma controller doc id 13902 rev 12 1043/1096 0x58 eth_maca3 hr ae sa mbc reserved maca3h reset value 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x5c eth_maca3 lr maca3l reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1...

  • Page 1044

    Ethernet (eth): media access control (mac) with dma controller rm0008 1044/1096 doc id 13902 rev 12 refer to table 3 on page 50 for the register boundary addresses. 0x718 eth_ptpts ar tsa reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x71c eth_ptptt hr ttsh reset value ...

  • Page 1045: Device Electronic Signature

    Rm0008 device electronic signature doc id 13902 rev 12 1045/1096 30 device electronic signature low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102xx and st...

  • Page 1046: 30.2

    Device electronic signature rm0008 1046/1096 doc id 13902 rev 12 30.2 unique device id register (96 bits) the unique device identifier is ideally suited: ● for use as serial numbers (for example usb string serial numbers or other end applications) ● for use as security keys in order to increase the ...

  • Page 1047

    Rm0008 device electronic signature doc id 13902 rev 12 1047/1096 address offset: 0x08 read only = 0xxxxx xxxx where x is factory-programmed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 u_id(95:80) r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 u_id(79:64) r r r r r r r r r ...

  • Page 1048: Debug Support (Dbg)

    Debug support (dbg) rm0008 1048/1096 doc id 13902 rev 12 31 debug support (dbg) low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. Medium-density devices are stm32f101xx, stm32f102xx and stm32f103xx microc...

  • Page 1049

    Rm0008 debug support (dbg) doc id 13902 rev 12 1049/1096 figure 359. Block diagram of stm32f10xxx-level and cortex-m3-level debug support note: the debug features embedded in the cortex-m3 core are a subset of the arm coresight design kit. The arm cortex-m3 core provides integrated on-chip debug sup...

  • Page 1050: 31.2

    Debug support (dbg) rm0008 1050/1096 doc id 13902 rev 12 31.2 reference arm documentation ● cortex™-m3 r1p1 technical reference manual (trm) it is available from: http://infocenter.Arm.Com/help/topic/com.Arm.Doc.Ddi0337e/ddi0337e_cortex_m3_r1p1_trm.Pdf ● arm debug interface v5 ● arm coresight design...

  • Page 1051: 31.4

    Rm0008 debug support (dbg) doc id 13902 rev 12 1051/1096 if the debugger host wants to switch to the sw-dp, it must provide a dedicated jtag sequence on tms/tck (respectively mapped to swdio and swclk) which disables the jtag-dp and enables the sw-dp. This way it is possible to activate the swdp usi...

  • Page 1052

    Debug support (dbg) rm0008 1052/1096 doc id 13902 rev 12 31.4.1 swj debug port pins five pins are used as outputs from the stm32f10xxx for the swj-dp as alternate functions of general-purpose ios. These pins are available on all packages. 31.4.2 flexible swj-dp pin assignment after reset (sysresetn ...

  • Page 1053

    Rm0008 debug support (dbg) doc id 13902 rev 12 1053/1096 note: when the apb bridge write buffer is full, it takes one extra apb cycle when writing the afio_mapr register. This is because the deactivation of the jtagsw pins is done in two cycles to guarantee a clean level on the ntrst and tck input s...

  • Page 1054: 31.5

    Debug support (dbg) rm0008 1054/1096 doc id 13902 rev 12 31.4.4 using serial wire and releasing the unused debug pins as gpios to use the serial wire dp to release some gpios, the user software must set swj_cfg=010 just after reset. This releases pa15, pb3 and pb4 which now become available as gpios...

  • Page 1055: 31.6

    Rm0008 debug support (dbg) doc id 13902 rev 12 1055/1096 figure 361. Jtag tap connections 31.6 id codes and locking mechanism there are several id codes inside the stm32f10xxx mcus. St strongly recommends tools designers to lock their debuggers using the mcu device id code located in the external pp...

  • Page 1056

    Debug support (dbg) rm0008 1056/1096 doc id 13902 rev 12 31.6.2 boundary scan tap jtag id code the tap of the stm32f10xxx bsc (boundary scan) integrates a jtag id code equal to ● in low-density devices: – 0x06412041 = revision a ● in medium-density devices: – 0x06410041 = revision a – 0x16410041 = r...

  • Page 1057: 31.7

    Rm0008 debug support (dbg) doc id 13902 rev 12 1057/1096 31.6.3 cortex-m3 tap the tap of the arm cortex-m3 integrates a jtag id code. This id code is the arm default one and has not been modified. This code is only accessible by the jtag debug port. This code is 0x3ba00477 (corresponds to cortex-m3 ...

  • Page 1058

    Debug support (dbg) rm0008 1058/1096 doc id 13902 rev 12 1011 apacc [35 bits] access port access register initiates an access port and allows access to an access port register. – when transferring data in: bits 34:3 = data[31:0] = 32-bit data to shift in for a write request bits 2:1 = a[3:2] = 2-bit...

  • Page 1059: 31.8

    Rm0008 debug support (dbg) doc id 13902 rev 12 1059/1096 31.8 sw debug port 31.8.1 sw protocol introduction this synchronous serial protocol uses two pins: ● swclk: clock from host to target ● swdio: bidirectional the protocol allows two banks of registers (dpacc registers and apacc registers) to be...

  • Page 1060

    Debug support (dbg) rm0008 1060/1096 doc id 13902 rev 12 the ack response must be followed by a turnaround time only if it is a read transaction or if a wait or fault acknowledge has been received. The data transfer must be followed by a turnaround time only if it is a read transaction. 31.8.3 sw-dp...

  • Page 1061

    Rm0008 debug support (dbg) doc id 13902 rev 12 1061/1096 idcode read or ctrl/stat read or abort write which are accepted even if the write buffer is full. ● because of the asynchronous clock domains swclk and hclk, two extra swclk cycles are needed after a write transaction (after the parity bit) to...

  • Page 1062: 31.9

    Debug support (dbg) rm0008 1062/1096 doc id 13902 rev 12 there are many ap registers (see ahb-ap) addressed as the combination of: ● the shifted value a[3:2] ● the current value of the dp select register 31.9 ahb-ap (ahb access port) - valid for both jtag-dp and sw-dp features: ● system access is in...

  • Page 1063: 31.10 Core

    Rm0008 debug support (dbg) doc id 13902 rev 12 1063/1096 31.10 core debug core debug is accessed through the core debug registers. Debug access to these registers is by means of the advanced high-performance bus (ahb-ap) port. The processor can access these registers directly over the internal priva...

  • Page 1064: 31.12

    Debug support (dbg) rm0008 1064/1096 doc id 13902 rev 12 note: it is highly recommended for the debugger host to connect (set a breakpoint in the reset vector) under system reset. 31.12 fpb (flash patch breakpoint) the fpb unit: ● implements hardware breakpoints ● patches code and data from code spa...

  • Page 1065: 31.14 Itm

    Rm0008 debug support (dbg) doc id 13902 rev 12 1065/1096 31.14 itm (instrumentation trace macrocell) 31.14.1 general description the itm is an application-driven trace source that supports printf style debugging to trace operating system (os) and application events, and emits diagnostic system infor...

  • Page 1066

    Debug support (dbg) rm0008 1066/1096 doc id 13902 rev 12 example of configuration to output a simple value to the tpiu: ● configure the tpiu and assign trace ios by configuring the dbgmcu_cr (refer to section 31.17.2: trace pin assignment and section 31.16.3: debug mcu configuration register ) ● wri...

  • Page 1067: 31.15

    Rm0008 debug support (dbg) doc id 13902 rev 12 1067/1096 31.15 etm (embedded trace macrocell) 31.15.1 general description the etm enables the reconstruction of program execution. Data are traced using the data watchpoint and trace (dwt) component or the instruction trace macrocell (itm) whereas inst...

  • Page 1068: 31.16

    Debug support (dbg) rm0008 1068/1096 doc id 13902 rev 12 31.15.4 configuration example to output a simple value to the tpiu: ● configure the tpiu and enable the i/io_tracen to assign trace ios in the xl- and high-density device’s debug configuration register. ● write 0xc5acce55 to the etm lock acces...

  • Page 1069

    Rm0008 debug support (dbg) doc id 13902 rev 12 1069/1096 for the i 2 c, the user can choose to block the smbus timeout during a breakpoint. 31.16.3 debug mcu configuration register this register allows the configuration of the mcu under debug. This concerns: ● low-power mode support ● timer and watc...

  • Page 1070

    Debug support (dbg) rm0008 1070/1096 doc id 13902 rev 12 bit 16 dbg_i2c2_smbus_timeout: smbus timeout mode stopped when core is halted 0: same behavior as in normal mode 1: the smbus timeout is frozen bit 15 dbg_i2c1_smbus_timeout: smbus timeout mode stopped when core is halted 0: same behavior as i...

  • Page 1071

    Rm0008 debug support (dbg) doc id 13902 rev 12 1071/1096 bit 0 dbg_sleep:debug sleep mode 0: (fclk=on, hclk=off) in sleep mode, fclk is clocked by the system clock as previously configured by the software while hclk is disabled. In sleep mode, the clock controller configuration is not reset and rema...

  • Page 1072: 31.17

    Debug support (dbg) rm0008 1072/1096 doc id 13902 rev 12 31.17 tpiu (trace port interface unit) 31.17.1 introduction the tpiu acts as a bridge between the on-chip trace data from the itm and the etm. The output data stream encapsulates the trace source id, that is then captured by a trace port analy...

  • Page 1073

    Rm0008 debug support (dbg) doc id 13902 rev 12 1073/1096 tpui trace pin assignment by default, these pins are not assigned. They can be assigned by setting the trace_ioen and trace_mode bits in the mcu debug component configuration register. This configuration has to be done by the debugger host. In...

  • Page 1074

    Debug support (dbg) rm0008 1074/1096 doc id 13902 rev 12 note: by default, the traceclkin input clock of the tpiu is tied to gnd. It is assigned to hclk two clock cycles after the bit trace_ioen has been set. The debugger must then program the trace mode by writing the protocol[1:0] bits in the spp_...

  • Page 1075

    Rm0008 debug support (dbg) doc id 13902 rev 12 1075/1096 31.17.4 tpui frame synchronization packets the tpui can generate two types of synchronization packets: ● the frame synchronization packet (or full word synchronization packet) it consists of the word: 0x7f_ff_ff_ff (lsb emitted first). This se...

  • Page 1076

    Debug support (dbg) rm0008 1076/1096 doc id 13902 rev 12 31.17.7 asynchronous mode this is a low cost alternative to output the trace using only 1 pin: this is the asynchronous output pin traceswo. Obviously there is a limited bandwidth. Traceswo is multiplexed with jtdo when using the sw-dp pin. Th...

  • Page 1077

    Rm0008 debug support (dbg) doc id 13902 rev 12 1077/1096 31.17.9 tpiu registers the tpiu apb registers can be read and written only if the bit trcena of the debug exception and monitor control register (demcr) is set. Otherwise, the registers are read as zero (the output of this bit enables the pclk...

  • Page 1078: 31.18

    Debug support (dbg) rm0008 1078/1096 doc id 13902 rev 12 31.17.10 example of configuration ● set the bit trcena in the debug exception and monitor control register (demcr) ● write the tpiu current port size register to the desired value (default is 0x1 for a 1-bit port size) ● write tpiu formatter a...

  • Page 1079: 32 Revision

    Rm0008 revision history doc id 13902 rev 12 1079/1096 32 revision history table 232. Document revision history date revision changes 19-oct-2007 1 document reference number changed from um0306 to rm008. The changes below were made with reference to revision 1 of 01-jun-2007 of um0306. Extsel[2:0] an...

  • Page 1080

    Revision history rm0008 1080/1096 doc id 13902 rev 12 19-oct-2007 continued 1 continued figure 114: counter timing diagram, internal clock divided by 1, timx_arr=0x6 and figure 129: output compare mode, toggle on oc1. Modified. Ckd definition modified in section 15.4.1: timx control register 1 (timx...

  • Page 1081

    Rm0008 revision history doc id 13902 rev 12 1081/1096 20-nov-2007 2 figure 27.3.1: usart block diagramusart character description modified. Procedure modified in character reception on page 769 . In section 27.3.4: fractional baud rate generation : – equation legend modified – table 191: error calcu...

  • Page 1082

    Revision history rm0008 1082/1096 doc id 13902 rev 12 08-feb-2008 3 figure 4: power supply overview on page 66 modified. Section 7.1.2: power reset on page 88 modified. Section 7.2: clocks on page 89 modified. Definition of bits 26:24 modified in section 9.4.2: af remap and debug i/o configuration r...

  • Page 1083

    Rm0008 revision history doc id 13902 rev 12 1083/1096 22-may-2008 continued 4 continued in section 7: low-, medium-, high- and xl-density reset and clock control (rcc) on page 87 : – lsi calibration on page 93 added – figure 7: simplified diagram of the reset circuit on page 88 updated – apb2 periph...

  • Page 1084

    Revision history rm0008 1084/1096 doc id 13902 rev 12 22-may-2008 continued 4 continued figure 234: can frames on page 648 modified. Bits 31:21 and bits 20:3 modified in can tx mailbox identifier register (can_tixr) (x=0..2) on page 661 . Bits 31:21 and bits 20:3 modified in can receive fifo mailbox...

  • Page 1085

    Rm0008 revision history doc id 13902 rev 12 1085/1096 26-sep-2008 6 this reference manual also applies to low-density stm32f101xx, stm32f102xx and stm32f103xx devices, and to medium-density stm32f102xx devices. In all sections, definitions of low-density and medium-density devices updated. Section 2...

  • Page 1086

    Revision history rm0008 1086/1096 doc id 13902 rev 12 23-dec-2008 7 memory map figure removed from reference manual. Section 3.1: system architecture on page 47 modified. Section 3.4: boot configuration on page 60 modified. Exiting sleep mode on page 71 modified. Section 6.3.2: rtc calibration on pa...

  • Page 1087

    Rm0008 revision history doc id 13902 rev 12 1087/1096 11-feb-2009 8 reset value corrected in section 4.4.1: data register (crc_dr) . Section 11.10: temperature sensor modified. Reset value corrected in section 11.12.7: adc watchdog high threshold register (adc_htr) . Section 12.3.9: triangle-wave ge...

  • Page 1088

    Revision history rm0008 1088/1096 doc id 13902 rev 12 22-jun-2009 9 reference manual updated to support also stm32f105xx/stm32f107xx connectivity line devices. Memory and bus architecture section: embedded boot loader updated. Section 4.3: crc functional description updated. Note modified in section...

  • Page 1089

    Rm0008 revision history doc id 13902 rev 12 1089/1096 04-dec-2009 10 (to be continued on next page) references to the stm32f10xxx cortex-m3 programming manual (pm0056) made throughout the document. The gpio, afio, exti, adc, dac, can, fsmc, sdio, usb_otg registers are accessed by words (32 bits). Th...

  • Page 1090

    Revision history rm0008 1090/1096 doc id 13902 rev 12 04-dec-2009 10 continued txfelvl bit description modified in otg_fs ahb configuration register (otg_fs_gahbcfg) . Nptxfe bit description modified in otg_fs core interrupt register (otg_fs_gintsts) . Nptxfem bit description modified in otg_fs inte...

  • Page 1091

    Rm0008 revision history doc id 13902 rev 12 1091/1096 23-apr-2010 11 continued updated section 21: flexible static memory controller (fsmc) , updated section 21.3: ahb interface on page 490 updated wrap support for nor flash/psram on page 493 added asyncwait, in table 108: fsmc_bcrx bit fields on pa...

  • Page 1092: Index

    Rm0008 index doc id 13902 rev 12 1092/1096 index a adc_cr1 . . . . . . . . . . . . . . . . . . . . . . . . . . .228 adc_cr2 . . . . . . . . . . . . . . . . . . . . . . . . . . .230 adc_dr . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 adc_htr . . . . . . . . . . . . . . . . . . . . . . ....

  • Page 1093

    Rm0008 index doc id 13902 rev 12 1093/1096 eth_macmiiar . . . . . . . . . . . . . . . . . . . . .1007 eth_macmiidr . . . . . . . . . . . . . . . . . . . . .1008 eth_macpmtcsr . . . . . . . . . . . . . . . . . . .1012 eth_macrwuffr . . . . . . . . . . . . . . . . . .1011 eth_macsr . . . . . . . . . ....

  • Page 1094

    Rm0008 index doc id 13902 rev 12 1094/1096 otg_fs_hcfg . . . . . . . . . . . . . . . . . . . . . . .852 otg_fs_hcintmskx . . . . . . . . . . . . . . . . .861 otg_fs_hcintx . . . . . . . . . . . . . . . . . . . . .860 otg_fs_hctsizx . . . . . . . . . . . . . . . . . . . .862 otg_fs_hfir . . . . . . ....

  • Page 1095

    Rm0008 index doc id 13902 rev 12 1095/1096 w wwdg_cfr . . . . . . . . . . . . . . . . . . . . . . . . .486 wwdg_cr . . . . . . . . . . . . . . . . . . . . . . . . . .485 wwdg_sr . . . . . . . . . . . . . . . . . . . . . . . . . .486.

  • Page 1096

    Rm0008 1096/1096 doc id 13902 rev 12 please read carefully: information in this document is provided solely in connection with st products. Stmicroelectronics nv and its subsidiaries (“st”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the produ...