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ST STM32F3 Series Programming Manual

Manual is about: Cortex-M4

Summary of STM32F3 Series

  • Page 1

    October 2017 docid022708 rev 6 1/260 1 pm0214 programming manual stm32f3 series, stm32f4 series, stm32l4 series and stm32l4+ series cortex ® -m4 programming manual introduction this programming manual provides information for application and system-level software developers. It gives a full descript...

  • Page 2: Contents

    Contents pm0214 2/260 docid022708 rev 6 contents 1 about this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.1 typographical conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.2 list of abbreviations for registers . ....

  • Page 3

    Docid022708 rev 6 3/260 pm0214 contents 8 2.4 fault handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.4.1 fault types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.4.2 fault escalation and ha...

  • Page 4

    Contents pm0214 4/260 docid022708 rev 6 3.5.3 asr, lsl, lsr, ror, and rrx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.5.4 clz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.5.5 cmp and cmn . . . . . . . . . . . . . . ...

  • Page 5

    Docid022708 rev 6 5/260 pm0214 contents 8 3.7.2 ssat16 and usat16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 3.7.3 qadd and qsub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 3.7.4 qasx and qsax . . . . . . . . . . . . . . . . ...

  • Page 6

    Contents pm0214 6/260 docid022708 rev 6 3.10.18 vmov arm core register to scalar . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 3.10.19 vmrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 3.10.20 vmsr . . . . . . . . . . . . . . . . ....

  • Page 7

    Docid022708 rev 6 7/260 pm0214 contents 8 4.2.9 mpu region attribute and size register (mpu_rasr) . . . . . . . . . . . . . 203 4.2.10 mpu register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 4.3 nested vectored interrupt controller (nvic) . . . . . . . . ...

  • Page 8

    Contents pm0214 8/260 docid022708 rev 6 4.5.3 systick current value register (stk_val) . . . . . . . . . . . . . . . . . . . . . . 248 4.5.4 systick calibration value register (stk_calib) . . . . . . . . . . . . . . . . . 249 4.5.5 systick design hints and tips . . . . . . . . . . . . . . . . . . . ...

  • Page 9: List of Tables

    Docid022708 rev 6 9/260 pm0214 list of tables 10 list of tables table 1. Summary of processor mode, execution privilege level, and stack usage . . . . . . . . . . . . . 17 table 2. Core register set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

  • Page 10

    List of tables pm0214 10/260 docid022708 rev 6 table 49. Summary of the system control block registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 table 50. Priority grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

  • Page 11: List of Figures

    Docid022708 rev 6 11/260 pm0214 list of figures 11 list of figures figure 1. Stm32 cortex-m4 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 2. Processor core registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

  • Page 12: 1 About

    About this document pm0214 12/260 docid022708 rev 6 1 about this document this document provides the information required for application and system-level software development. It does not provide information on debug components, features, or operation. This material is for microcontroller software ...

  • Page 13: 1.3

    Docid022708 rev 6 13/260 pm0214 about this document 259 1.3 about the stm32 cortex-m4 processor and core peripherals the cortex-m4 processor is a high performance 32-bit processor designed for the microcontroller market. It offers significant benefits to developers, including: • outstanding processi...

  • Page 14

    About this document pm0214 14/260 docid022708 rev 6 integration of the processor core and nvic provides fast execution of interrupt service routines (isrs), dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the ability to suspend load-multi...

  • Page 15

    Docid022708 rev 6 15/260 pm0214 about this document 259 1.3.4 cortex-m4 core peripherals the peripherals are: nested vectored interrupt controller the nested vectored interrupt controller (nvic) is an embedded interrupt controller that supports low latency interrupt processing. System control block ...

  • Page 16: The Cortex-M4 Processor

    The cortex-m4 processor pm0214 16/260 docid022708 rev 6 2 the cortex-m4 processor 2.1 programmers model this section describes the cortex-m4 programmer’s model. In addition to the individual core register descriptions, it contains information about the processor modes and privilege levels for softwa...

  • Page 17

    Docid022708 rev 6 17/260 pm0214 the cortex-m4 processor 259 2.1.3 core registers figure 2. Processor core registers table 1. Summary of processor mode, execution privilege level, and stack usage processor mode used to execute privilege level for software execution stack used thread applications priv...

  • Page 18

    The cortex-m4 processor pm0214 18/260 docid022708 rev 6 general-purpose registers r0-r12 are 32-bit general-purpose registers for data operations. Stack pointer the stack pointer (sp) is register r13. In thread mode, bit[1] of the control register indicates the stack pointer to use: • 0: main stack ...

  • Page 19

    Docid022708 rev 6 19/260 pm0214 the cortex-m4 processor 259 these registers are mutually exclusive bitfields in the 32-bit psr. The bit assignments are as shown in figure 3 and figure 4 . Figure 3. Apsr, ipsr and epsr bit assignments figure 4. Psr bit assignments access these registers individually ...

  • Page 20

    The cortex-m4 processor pm0214 20/260 docid022708 rev 6 application program status register the apsr contains the current state of the condition flags from previous instruction executions. See the register summary in table 2 on page 17 for its attributes. The bit assignments are: table 4. Apsr bit d...

  • Page 21

    Docid022708 rev 6 21/260 pm0214 the cortex-m4 processor 259 interrupt program status register the ipsr contains the exception type number of the current interrupt service routine (isr). See the register summary in table 2 on page 17 for its attributes. The bit assignments are: execution program stat...

  • Page 22

    The cortex-m4 processor pm0214 22/260 docid022708 rev 6 attempts to read the epsr directly through application software using the msr instruction always return zero. Attempts to write the epsr using the msr instruction in application software are ignored. Fault handlers can examine epsr value in the...

  • Page 23

    Docid022708 rev 6 23/260 pm0214 the cortex-m4 processor 259 to access the exception mask registers use the msr and mrs instructions, or the cps instruction to change the value of primask or faultmask. See mrs on page 185 , msr on page 186 , and cps on page 181 for more information. Priority mask reg...

  • Page 24

    The cortex-m4 processor pm0214 24/260 docid022708 rev 6 base priority mask register the basepri register defines the minimum priority for exception processing. When basepri is set to a nonzero value, it prevents the activation of all exceptions with same or lower priority level as the basepri value....

  • Page 25

    Docid022708 rev 6 25/260 pm0214 the cortex-m4 processor 259 handler mode always uses the msp, so the processor ignores explicit writes to the active stack pointer bit of the control register when in handler mode. The exception entry and return mechanisms update the control register. In an os environ...

  • Page 26

    The cortex-m4 processor pm0214 26/260 docid022708 rev 6 the cmsis includes address definitions and data structures for the core peripherals in the cortex-m4 processor. Cmsis simplifies software development by enabling the reuse of template code and the combination of cmsis-compliant software compone...

  • Page 27: 2.2 Memory

    Docid022708 rev 6 27/260 pm0214 the cortex-m4 processor 259 2.2 memory model this section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4 gb of addressable memory. Figure 8. Memory map the r...

  • Page 28

    The cortex-m4 processor pm0214 28/260 docid022708 rev 6 2.2.1 memory regions, types and attributes the memory map and the programming of the mpu splits the memory map into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attribut...

  • Page 29

    Docid022708 rev 6 29/260 pm0214 the cortex-m4 processor 259 2.2.3 behavior of memory accesses the behavior of accesses to each region in the memory map is: the code, sram, and external ram regions can hold programs. However, it is recommended that programs always use the code region. The reason of t...

  • Page 30

    The cortex-m4 processor pm0214 30/260 docid022708 rev 6 2.2.4 software ordering of memory accesses the order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions. The reason for this is that: • the processor can reorder some memory accesses...

  • Page 31

    Docid022708 rev 6 31/260 pm0214 the cortex-m4 processor 259 2.2.5 bit-banding a bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band regions occupy the lowest 1 mbyte of the sram and peripheral memory regions. The memory map has two 32 mbyte ...

  • Page 32

    The cortex-m4 processor pm0214 32/260 docid022708 rev 6 where: • bit_word_offset is the position of the target bit in the bit-band memory region. • bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit. • bit_band_base is the starting address of the alias ...

  • Page 33

    Docid022708 rev 6 33/260 pm0214 the cortex-m4 processor 259 reading a word in the alias region: • 0x00000000 indicates that the targeted bit in the bit-band region is set to zero • 0x00000001 indicates that the targeted bit in the bit-band region is set to 1 directly accessing a bit-band region beha...

  • Page 34

    The cortex-m4 processor pm0214 34/260 docid022708 rev 6 the pairs of load-exclusive and store-exclusive instructions are: • the word instructions ldrex and strex • the halfword instructions ldrexh and strexh • the byte instructions ldrexb and strexb. Software must use a load-exclusive instruction wi...

  • Page 35

    Docid022708 rev 6 35/260 pm0214 the cortex-m4 processor 259 2.2.8 programming hints for the synchronization primitives iso/iec c cannot directly generate the exclusive access instructions. Cmsis provides intrinsic functions for generation of these instructions: for example: uint16_t value; uint16_t ...

  • Page 36: 2.3 Exception

    The cortex-m4 processor pm0214 36/260 docid022708 rev 6 2.3 exception model this section describes the exception model. 2.3.1 exception states each exception is in one of the following states: 2.3.2 exception types the exception types are: inactive the exception is not active and not pending. Pendin...

  • Page 37

    Docid022708 rev 6 37/260 pm0214 the cortex-m4 processor 259 bus fault a bus fault is an exception that occurs because of a memory related fault for an instruction or data memory transaction. This might be from an error detected on a bus in the memory system. Usage fault a usage fault is an exception...

  • Page 38

    The cortex-m4 processor pm0214 38/260 docid022708 rev 6 for an asynchronous exception other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler. Privileged software can disable the exceptions that table...

  • Page 39

    Docid022708 rev 6 39/260 pm0214 the cortex-m4 processor 259 2.3.4 vector table the vector table contains the reset value of the stack pointer, and the start addresses, also called exception vectors, for all exception handlers. Figure 11 on page 39 shows the order of the exception vectors in the vect...

  • Page 40

    The cortex-m4 processor pm0214 40/260 docid022708 rev 6 2.3.5 exception priorities table 16 on page 37 shows that all exceptions have an associated priority, in details: • a lower priority value indicating a higher priority • configurable priorities for all exceptions except reset, hard fault, and n...

  • Page 41

    Docid022708 rev 6 41/260 pm0214 the cortex-m4 processor 259 2.3.7 exception entry and return descriptions of exception handling use the following terms: exception entry exception entry occurs when there is a pending exception with sufficient priority and either: • the processor is in thread mode • t...

  • Page 42

    The cortex-m4 processor pm0214 42/260 docid022708 rev 6 stack frame is the same as that of armv7-m implementations without an fpu. Figure 12 on page 42 also shows this stack frame. Figure 12. Cortex-m4 stack frame layout immediately after stacking, the stack pointer indicates the lowest address in t...

  • Page 43: 2.4 Fault

    Docid022708 rev 6 43/260 pm0214 the cortex-m4 processor 259 exception return exception return occurs when the processor is in handler mode and executes one of the following instructions to load the exc_return value into the pc: • an ldm or pop instruction that loads the pc • an ldr instruction with ...

  • Page 44

    The cortex-m4 processor pm0214 44/260 docid022708 rev 6 2.4.1 fault types table 18 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the register bit that indicates that the fault has occurred. See configurable fault status register (cfsr; ufsr+bf...

  • Page 45

    Docid022708 rev 6 45/260 pm0214 the cortex-m4 processor 259 2.4.2 fault escalation and hard faults all faults exceptions except for hard fault have configurable exception priority, as described in system handler priority registers (shprx) on page 232 . Software can disable execution of the handlers ...

  • Page 46: 2.5 Power

    The cortex-m4 processor pm0214 46/260 docid022708 rev 6 2.4.3 fault status registers and fault address registers the fault status registers indicate the cause of a fault. For bus faults and memory management faults, the fault address register indicates the address accessed by the operation that caus...

  • Page 47

    Docid022708 rev 6 47/260 pm0214 the cortex-m4 processor 259 2.5.1 entering sleep mode this section describes the mechanisms software can use to put the processor into sleep mode. The system can generate spurious wakeup events, for example a debug operation that wakes up the processor. Therefore soft...

  • Page 48

    The cortex-m4 processor pm0214 48/260 docid022708 rev 6 wakeup from wfe the processor wakes up if: • it detects an exception with sufficient priority to cause exception entry • it detects an external event signal, see section 2.5.3: external event input / extended interrupt and event input • in a mu...

  • Page 49: 3.1 Instruction

    Docid022708 rev 6 49/260 pm0214 the stm32 cortex-m4 instruction set 259 3 the stm32 cortex-m4 instruction set this chapter is the reference material for the cortex-m4 instruction set description in a user guide. The following sections give general information: section 3.1: instruction set summary on...

  • Page 50

    The stm32 cortex-m4 instruction set pm0214 50/260 docid022708 rev 6 and, ands {rd,} rn, op2 logical and n,z,c 3.5.2 on page 84 asr, asrs rd, rm, arithmetic shift right n,z,c 3.5.3 on page 85 b label branch — 3.9.5 on page 141 bfc rd, #lsb, #width bit field clear — 3.9.1 on page 138 bfi rd, rn, #lsb,...

  • Page 51

    Docid022708 rev 6 51/260 pm0214 the stm32 cortex-m4 instruction set 259 ldrexb rt, [rn] load register exclusive with byte — 3.4.8 on page 78 ldrexh rt, [rn] load register exclusive with halfword — 3.4.8 on page 78 ldrh, ldrht rt, [rn, #offset] load register with halfword — 3.4 on page 68 ldrsb, ldrs...

  • Page 52

    The stm32 cortex-m4 instruction set pm0214 52/260 docid022708 rev 6 qdadd {rd,} rn, rm saturating add 3.7.5 on page 129 qdsub {rd,} rn, rm saturating double and subtract 3.7.5 on page 129 qsax {rd,} rn, rm saturating subtract and add with exchange 3.7.4 on page 128 qsub {rd,} rn, rm saturating subtr...

  • Page 53

    Docid022708 rev 6 53/260 pm0214 the stm32 cortex-m4 instruction set 259 smlal rdlo, rdhi, rn, rm signed multiply with accumulate (32 x 32 + 64), 64- bit result — 3.6.2 on page 110 smlalbb, smlalbt, smlaltb, smlaltt rdlo, rdhi, rn, rm signed multiply accumulate long, halfwords — 3.6.5 on page 114 sml...

  • Page 54

    The stm32 cortex-m4 instruction set pm0214 54/260 docid022708 rev 6 strd rt, rt2, [rn, #offset] store register two words — 3.4.2 on page 70 strex rd, rt, [rn, #offset] store register exclusive — 3.4.8 on page 78 strexb rd, rt, [rn] store register exclusive byte — 3.4.8 on page 78 strexh rd, rt, [rn]...

  • Page 55

    Docid022708 rev 6 55/260 pm0214 the stm32 cortex-m4 instruction set 259 udiv {rd,} rn, rm unsigned divide — 3.6.3 on page 111 umaal rdlo, rdhi, rn, rm unsigned multiply accumulate accumulate long (32 x 32 + 32 +32), 64-bit result — 3.6.2 on page 110 umlal rdlo, rdhi, rn, rm unsigned multiply with ac...

  • Page 56

    The stm32 cortex-m4 instruction set pm0214 56/260 docid022708 rev 6 vcmp.F32 sd, compare two floating-point registers, or one floating-point register and zero fpscr 3.10.3 on page 152 vcmpe.F32 sd, compare two floating-point registers, or one floating-point register and zero with invalid operation c...

  • Page 57: 3.2

    Docid022708 rev 6 57/260 pm0214 the stm32 cortex-m4 instruction set 259 3.2 cmsis intrinsic functions iso/iec c code cannot directly access some cortex-m4 instructions. This section describes intrinsic functions that can generate these instructions, provided by the cmis, and that might be provided b...

  • Page 58

    The stm32 cortex-m4 instruction set pm0214 58/260 docid022708 rev 6 the cmsis also provides a number of functions for accessing the special registers using mrs and msr instructions (see table 22 ). Table 21. Cmsis intrinsic functions to generate some cortex-m4 instructions instruction cmsis intrinsi...

  • Page 59: 3.3

    Docid022708 rev 6 59/260 pm0214 the stm32 cortex-m4 instruction set 259 3.3 about the instruction descriptions the following sections give more information about using the instructions: • operands on page 59 • restrictions when using pc or sp on page 59 • flexible second operand on page 59 • shift o...

  • Page 60

    The stm32 cortex-m4 instruction set pm0214 60/260 docid022708 rev 6 constant you specify an operand2 constant in the form #constant, where constant can be: • any constant that can be produced by shifting an 8-bit value left by any number of bits within a 32-bit word. • any constant of the form 0x00x...

  • Page 61

    Docid022708 rev 6 61/260 pm0214 the stm32 cortex-m4 instruction set 259 3.3.4 shift operations register shift operations move the bits in a register left or right by a specified number of bits, the shift length. Register shift can be performed: • directly by the instructions asr, lsr, lsl, ror, and ...

  • Page 62

    The stm32 cortex-m4 instruction set pm0214 62/260 docid022708 rev 6 lsr logical shift right by n bits moves the left-hand 32-n bits of the rm register to the right by n places, into the right-hand 32-n bits of the result. And it sets the left-hand n bits of the result to 0 (see figure 14 ). You can ...

  • Page 63

    Docid022708 rev 6 63/260 pm0214 the stm32 cortex-m4 instruction set 259 ror rotate right by n bits moves the left-hand 32-n bits of the rm register to the right by n places, into the right-hand 32-n bits of the result. It also moves the right-hand n bits of the register into the left-hand n bits of ...

  • Page 64

    The stm32 cortex-m4 instruction set pm0214 64/260 docid022708 rev 6 3.3.5 address alignment an aligned access is an operation where a word-aligned address is used for a word, dual word, or multiple word access, or where a halfword-aligned address is used for a halfword access. Byte accesses are alwa...

  • Page 65

    Docid022708 rev 6 65/260 pm0214 the stm32 cortex-m4 instruction set 259 conditional execution is available by using conditional branches or by adding condition code suffixes to instructions. See table 23: condition code suffixes on page 66 for a list of the suffixes to add to instructions to make th...

  • Page 66

    The stm32 cortex-m4 instruction set pm0214 66/260 docid022708 rev 6 condition code suffixes the instructions that can be conditional have an optional condition code, shown in syntax descriptions as {cond}. Conditional execution requires a preceding it instruction. An instruction with a condition cod...

  • Page 67

    Docid022708 rev 6 67/260 pm0214 the stm32 cortex-m4 instruction set 259 cmpgt r2, r3; if 'greater than', compare r2 and r3, setting flags movgt r4, r5 ; if still 'greater than', do r4 = r5 3.3.8 instruction width selection there are many instructions that can generate either a 16-bit encoding or a 3...

  • Page 68: 3.4

    The stm32 cortex-m4 instruction set pm0214 68/260 docid022708 rev 6 3.4 memory access instructions table 24 shows the memory access instructions: table 24. Memory access instructions mnemonic brief description see adr load pc-relative address adr on page 69 clrex clear exclusive clrex on page 79 ldm...

  • Page 69

    Docid022708 rev 6 69/260 pm0214 the stm32 cortex-m4 instruction set 259 3.4.1 adr load pc-relative address. Syntax adr{cond} rd, label where: • ‘cond’ is an optional condition code (see conditional execution on page 64 ) • ‘rd’ is the destination register • ‘label’ is a pc-relative expression (see p...

  • Page 70

    The stm32 cortex-m4 instruction set pm0214 70/260 docid022708 rev 6 3.4.2 ldr and str, immediate offset load and store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset. Syntax op{type}{cond} rt, [rn {, #offset}]; immediate offset op{type}{cond} rt, [rn, #offset]!...

  • Page 71

    Docid022708 rev 6 71/260 pm0214 the stm32 cortex-m4 instruction set 259 the value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can either be signed or unsigned (see address alignment on page 64 ). Table 25 shows the range of offsets for immediate, pre-indexed and...

  • Page 72

    The stm32 cortex-m4 instruction set pm0214 72/260 docid022708 rev 6 3.4.3 ldr and str, register offset load and store with register offset. Syntax op{type}{cond} rt, [rn, rm {, lsl #n}] where: • ‘op’ is either ldr (load register) or str (store register). • ‘type’ is one of the following: b: unsigned...

  • Page 73

    Docid022708 rev 6 73/260 pm0214 the stm32 cortex-m4 instruction set 259 ; to a word value and put it in r0 str r0, [r1, r2, lsl #2]; stores r0 to an address equal to sum of r1 ; and four times r2 3.4.4 ldr and str, unprivileged load and store with unprivileged access. Syntax op{type}t{cond} rt, [rn ...

  • Page 74

    The stm32 cortex-m4 instruction set pm0214 74/260 docid022708 rev 6 3.4.5 ldr, pc-relative load register from memory. Syntax ldr{type}{cond} rt, label ldrd{cond} rt, rt2, label; load two words where: • ‘type’ is one of the following: b: unsigned byte, zero extends to 32 bits. Sb: signed byte, sign e...

  • Page 75

    Docid022708 rev 6 75/260 pm0214 the stm32 cortex-m4 instruction set 259 condition flags these instructions do not change the flags. Examples ldr r0, lookuptable; load r0 with a word of data from an address ; labelled as lookuptable ldrsb r7, localdata; load a byte value from an address labelled ; as...

  • Page 76

    The stm32 cortex-m4 instruction set pm0214 76/260 docid022708 rev 6 lowest numbered register using the lowest memory address and the highest number register using the highest memory address. If the writeback suffix is specified, the value of rn + 4 * (n-1) is written back to rn. For ldmdb, ldmea, st...

  • Page 77

    Docid022708 rev 6 77/260 pm0214 the stm32 cortex-m4 instruction set 259 3.4.7 push and pop push registers onto, and pop registers off a full-descending stack. Push and pop are synonyms for stmdb and ldm (or ldmia) with the memory addresses for the access based on sp, and with the final address for t...

  • Page 78

    The stm32 cortex-m4 instruction set pm0214 78/260 docid022708 rev 6 3.4.8 ldrex and strex load and store register exclusive. Syntax ldrex{cond} rt, [rn {, #offset}] strex{cond} rd, rt, [rn {, #offset}] ldrexb{cond} rt, [rn] strexb{cond} rd, rt, [rn] ldrexh{cond} rt, [rn] strexh{cond} rd, rt, [rn] wh...

  • Page 79

    Docid022708 rev 6 79/260 pm0214 the stm32 cortex-m4 instruction set 259 restrictions in these instructions: • do not use pc. • do not use sp for rd and rt. • for strex, rd must be different from both rt and rn. • the value of offset must be a multiple of four in the range 0-1020. Condition flags the...

  • Page 80: 3.5 General

    The stm32 cortex-m4 instruction set pm0214 80/260 docid022708 rev 6 3.5 general data processing instructions table 27 shows the data processing instructions. Table 27. Data processing instructions mnemonic brief description see adc add with carry add, adc, sub, sbc, and rsb on page 82 add add add, a...

  • Page 81

    Docid022708 rev 6 81/260 pm0214 the stm32 cortex-m4 instruction set 259 shasx signed halving add and subtract with exchange shasx and shsax on page 94 shsax signed halving subtract and add with exchange shasx and shsax on page 94 shsub16 signed halving subtract 16 shsub16 and shsub8 on page 95 shsub...

  • Page 82

    The stm32 cortex-m4 instruction set pm0214 82/260 docid022708 rev 6 3.5.1 add, adc, sub, sbc, and rsb add, add with carry, subtract, subtract with carry, and reverse subtract. Syntax op{s}{cond} {rd,} rn, operand2 op{cond} {rd,} rn, #imm12; add and sub only where: • ‘op’ is one of the following: add...

  • Page 83

    Docid022708 rev 6 83/260 pm0214 the stm32 cortex-m4 instruction set 259 restrictions in these instructions: • operand2 must be neither sp nor pc • rd can be sp only in add and sub, and only with the following additional restrictions: – rn must also be sp. – any shift in operand2 must be limited to a...

  • Page 84

    The stm32 cortex-m4 instruction set pm0214 84/260 docid022708 rev 6 multiword values do not have to use consecutive registers. Specific example 5: 96-bit subtraction shows instructions that subtract a 96-bit integer contained in r9, r1, and r11 from another contained in r6, r2, and r8. The example s...

  • Page 85

    Docid022708 rev 6 85/260 pm0214 the stm32 cortex-m4 instruction set 259 condition flags if s is specified, these instructions: • update the n and z flags according to the result. • can update the c flag during the calculation of operand2, see flexible second operand on page 59 . • do not affect the ...

  • Page 86

    The stm32 cortex-m4 instruction set pm0214 86/260 docid022708 rev 6 operation asr, lsl, lsr, and ror move the bits in the rm register to the left or right by the number of places specified by constant n or register rs. Rrx moves the bits in rm register to the right by 1. In all these instructions, t...

  • Page 87

    Docid022708 rev 6 87/260 pm0214 the stm32 cortex-m4 instruction set 259 examples clz r4,r9 clzne r2,r3 3.5.5 cmp and cmn compare and compare negative. Syntax cmp{cond} rn, operand2 cmn{cond} rn, operand2 where: • ‘cond’ is an optional condition code (see conditional execution on page 64 ). • ‘rn’ is...

  • Page 88

    The stm32 cortex-m4 instruction set pm0214 88/260 docid022708 rev 6 3.5.6 mov and mvn move and move not. Syntax mov{s}{cond} rd, operand2 mov{cond} rd, #imm16 mvn{s}{cond} rd, operand2 where: • ‘s’ is an optional suffix. If s is specified, the condition code flags are updated on the result of the op...

  • Page 89

    Docid022708 rev 6 89/260 pm0214 the stm32 cortex-m4 instruction set 259 restrictions you can use sp and pc only in the mov instruction, with the following restrictions: • the second operand must be a register without shift • you must not specify the s suffix when rd is pc in a mov instruction: • bit...

  • Page 90

    The stm32 cortex-m4 instruction set pm0214 90/260 docid022708 rev 6 3.5.7 movt move top. Syntax movt{cond} rd, #imm16 where: • ‘cond’ is an optional condition code (see conditional execution on page 64 ). • ‘rd’ is the destination register. • ‘imm16’ is a 16-bit immediate constant. Operation movt wr...

  • Page 91

    Docid022708 rev 6 91/260 pm0214 the stm32 cortex-m4 instruction set 259 3.5.8 rev, rev16, revsh, and rbit reverse bytes and reverse bits. Syntax op{cond} rd, rn where: • ‘op’ is one of the following: rev: reverse byte order in a word. Rev16: reverse byte order in each halfword independently. Revsh: ...

  • Page 92

    The stm32 cortex-m4 instruction set pm0214 92/260 docid022708 rev 6 3.5.9 sadd16 and sadd8 signed add 16 and signed add 8 syntax op{cond}{rd,} rn, rm where: • op is any of the following: sadd16: performs two 16-bit signed integer additions. Sadd8: performs four 8-bit signed integer additions. • ‘con...

  • Page 93

    Docid022708 rev 6 93/260 pm0214 the stm32 cortex-m4 instruction set 259 3.5.10 shadd16 and shadd8 signed halving add 16 and signed halving add 8 syntax op{cond}{rd,} rn, rm where: • op is any of the following: shadd16: signed halving add 16. Shadd8: signed halving add 8. • ‘cond’ is an optional cond...

  • Page 94

    The stm32 cortex-m4 instruction set pm0214 94/260 docid022708 rev 6 3.5.11 shasx and shsax signed halving add and subtract with exchange / signed halving subtract and add with exchange. Syntax op{cond} {rd}, rn, rm where: • op is any of the following: shasx: add and subtract with exchange and halvin...

  • Page 95

    Docid022708 rev 6 95/260 pm0214 the stm32 cortex-m4 instruction set 259 ; r4 and writes halved result to bottom halfword of r7 shsax r0, r3, r5 ; subtracts bottom halfword of r5 from top halfword ; of r3 and writes halved result to top halfword of r0 ; adds top halfword of r5 to bottom halfword of r...

  • Page 96

    The stm32 cortex-m4 instruction set pm0214 96/260 docid022708 rev 6 ; and writes to corresponding byte in r4. 3.5.13 ssub16 and ssub8 signed subtract 16 and signed subtract 8 syntax op{cond}{rd,} rn, rm where: • op is one of the following: ssub16: performs two 16-bit signed integer subtractions. Ssu...

  • Page 97

    Docid022708 rev 6 97/260 pm0214 the stm32 cortex-m4 instruction set 259 3.5.14 sasx and ssax signed add and subtract with exchange and signed subtract and add with exchange. Syntax op{cond} {rd}, rm, rn where: • op is any of the following: sasx: signed add and subtract with exchange. Ssax: signed su...

  • Page 98

    The stm32 cortex-m4 instruction set pm0214 98/260 docid022708 rev 6 ; adds top halfword of r3 with bottom halfword of r2 and ; writes to top halfword of r7. 3.5.15 tst and teq test bits and test equivalence. Syntax tst{cond} rn, operand2 teq{cond} rn, operand2 where: • ‘cond’ is an optional conditio...

  • Page 99

    Docid022708 rev 6 99/260 pm0214 the stm32 cortex-m4 instruction set 259 3.5.16 uadd16 and uadd8 unsigned add 16 and unsigned add 8 syntax op{cond}{rd,} rn, rm where: • op is one of the following: uadd16: performs two 16-bit unsigned integer additions. Uadd8: performs four 8-bit unsigned integer addi...

  • Page 100

    The stm32 cortex-m4 instruction set pm0214 100/260 docid022708 rev 6 3.5.17 uasx and usax add and subtract with exchange and subtract and add with exchange. Syntax op{cond} {rd}, rn, rm where: • op is one of: uasx: add and subtract with exchange. Usax: subtract and add with exchange. • ‘cond’ is an ...

  • Page 101

    Docid022708 rev 6 101/260 pm0214 the stm32 cortex-m4 instruction set 259 ; writes to top halfword of r7. 3.5.18 uhadd16 and uhadd8 unsigned halving add 16 and unsigned halving add 8 syntax op{cond}{rd,} rn, rm where: • op is any of the following: uhadd16: unsigned halving add 16. Uhadd8: unsigned ha...

  • Page 102

    The stm32 cortex-m4 instruction set pm0214 102/260 docid022708 rev 6 3.5.19 uhasx and uhsax unsigned halving add and subtract with exchange and unsigned halving subtract and add with exchange. Syntax op{cond} {rd}, rn, rm where: • op is one of the following: uhasx: add and subtract with exchange and...

  • Page 103

    Docid022708 rev 6 103/260 pm0214 the stm32 cortex-m4 instruction set 259 uhsax r0, r3, r5 ; subtracts bottom halfword of r5 from top halfword of ; r3 and writes halved result to top halfword of r0 ; adds top halfword of r5 to bottom halfword of r3 and ; writes halved result to bottom halfword of r0....

  • Page 104

    The stm32 cortex-m4 instruction set pm0214 104/260 docid022708 rev 6 uhsub8 r4, r0, r5 ; subtracts bytes of r5 from corresponding byte in r0 and ; writes halved result to corresponding byte in r4. 3.5.21 sel select bytes. Selects each byte of its result from either its first operand or its second op...

  • Page 105

    Docid022708 rev 6 105/260 pm0214 the stm32 cortex-m4 instruction set 259 3.5.22 usad8 unsigned sum of absolute differences syntax usad8{cond}{rd,} rn, rm where: • ‘cond’ is an optional condition code (see conditional execution on page 64 ). • ‘rd’ is the destination register. • ‘rn’ is the first ope...

  • Page 106

    The stm32 cortex-m4 instruction set pm0214 106/260 docid022708 rev 6 3.5.23 usada8 unsigned sum of absolute differences and accumulate syntax usada8{cond}{rd,} rn, rm, ra where: • ‘cond’ is an optional condition code (see conditional execution on page 64 ). • ‘rd’ is the destination register. • ‘rn’...

  • Page 107

    Docid022708 rev 6 107/260 pm0214 the stm32 cortex-m4 instruction set 259 3.5.24 usub16 and usub8 unsigned subtract 16 and unsigned subtract 8 syntax op{cond}{rd,} rn, rm where: • op is any of: usub16: unsigned subtract 16. Usub8: unsigned subtract 8. • ‘cond’ is an optional condition code (see condi...

  • Page 108: 3.6

    The stm32 cortex-m4 instruction set pm0214 108/260 docid022708 rev 6 3.6 multiply and divide instructions table 28 shows the multiply and divide instructions. Table 28. Multiply and divide instructions mnemonic brief description see mla multiply with accumulate, 32-bit result mul, mla, and mls on pa...

  • Page 109

    Docid022708 rev 6 109/260 pm0214 the stm32 cortex-m4 instruction set 259 3.6.1 mul, mla, and mls multiply, multiply with accumulate, and multiply with subtract, using 32-bit operands, and producing a 32-bit result. Syntax mul{s}{cond} {rd,} rn, rm ; multiply mla{cond} rd, rn, rm, ra ; multiply with ...

  • Page 110

    The stm32 cortex-m4 instruction set pm0214 110/260 docid022708 rev 6 3.6.2 umull, umaal and umlal unsigned long multiply, with optional accumulate, 32-bit operands, producing a 64-bit result. Syntax op{cond} rdlo, rdhi, rn, rm where: • ‘op’ is one of the following: umull: unsigned long multiply. Uma...

  • Page 111

    Docid022708 rev 6 111/260 pm0214 the stm32 cortex-m4 instruction set 259 ; top 32 bits to r6, and the bottom 32 bits to r3 umlal r2, r1, r3, r5 ; multiplies r5 and r3, adds r1:r2, writes to r1:r2. 3.6.3 smla and smlaw signed multiply accumulate (halfwords). Syntax op{xy}{cond} rd, rn, rm op{y}{cond}...

  • Page 112

    The stm32 cortex-m4 instruction set pm0214 112/260 docid022708 rev 6 condition flags if an overflow is detected, the q flag is set. Examples smlabb r5, r6, r4, r1 ; multiplies bottom halfwords of r6 and r4, adds ; r1 and writes to r5 smlatb r5, r6, r4, r1 ; multiplies top halfword of r6 with bottom ...

  • Page 113

    Docid022708 rev 6 113/260 pm0214 the stm32 cortex-m4 instruction set 259 3.6.4 smlad signed multiply accumulate long dual syntax op{x}{cond} rd, rn, rm, ra ; where: • op is one of the following: smlad: signed multiply accumulate dual. Smladx: signed multiply accumulate dual reverse. X specifies whic...

  • Page 114

    The stm32 cortex-m4 instruction set pm0214 114/260 docid022708 rev 6 3.6.5 smlal and smlald signed multiply accumulate long, signed multiply accumulate long (halfwords) and signed multiply accumulate long dual. Syntax op{cond} rdlo, rdhi, rn, rm op{xy}{cond} rdlo, rdhi, rn, rm op{x}{cond} rdlo, rdhi...

  • Page 115

    Docid022708 rev 6 115/260 pm0214 the stm32 cortex-m4 instruction set 259 the smlald and smlaldx instructions interpret the values from rn and rm as four halfword two’s complement signed 16-bit integers. These instructions: • if x is not present, multiply the top signed halfword value of rn with the ...

  • Page 116

    The stm32 cortex-m4 instruction set pm0214 116/260 docid022708 rev 6 3.6.6 smlsd and smlsld signed multiply subtract dual and signed multiply subtract long dual syntax op{x}{cond} rd, rn, rm, ra where: • op is one of: smlsd: signed multiply subtract dual. Smlsdx: signed multiply subtract dual revers...

  • Page 117

    Docid022708 rev 6 117/260 pm0214 the stm32 cortex-m4 instruction set 259 for the thumb instruction set, these instructions do not affect the condition code flags. Examples smls r0, r4, r5, r6 ; multiplies bottom halfword of r4 with bottom ; halfword of r5, multiplies top halfword of r4 ; with top ha...

  • Page 118

    The stm32 cortex-m4 instruction set pm0214 118/260 docid022708 rev 6 3.6.7 smmla and smmls signed most significant word multiply accumulate and signed most significant word multiply subtract. Syntax op{r}{cond} rd, rn, rm, ra where: • op is one of the following: smmla: signed most significant word m...

  • Page 119

    Docid022708 rev 6 119/260 pm0214 the stm32 cortex-m4 instruction set 259 smmls r4, r5, r3, r8 ; multiplies r5 and r3, extracts top 32 bits, ; subtracts r8, truncates and writes to r4. 3.6.8 smmul signed most significant word multiply syntax op{r}{cond} rd, rn, rm where: • op is one of the following:...

  • Page 120

    The stm32 cortex-m4 instruction set pm0214 120/260 docid022708 rev 6 3.6.9 smuad and smusd signed dual multiply add and signed dual multiply subtract syntax op{x}{cond} rd, rn, rm where: • op is one of: smuad: signed dual multiply add. Smuadx: signed dual multiply add reversed. Smusd: signed dual mu...

  • Page 121

    Docid022708 rev 6 121/260 pm0214 the stm32 cortex-m4 instruction set 259 smusd r3, r6, r2 ; multiplies bottom halfword of r4 with bottom halfword ; of r6, subtracts multiplication of top halfword of r6 ; with top halfword of r3, writes to r3 smusdx r4, r5, r3 ; multiplies bottom halfword of r5 with ...

  • Page 122

    The stm32 cortex-m4 instruction set pm0214 122/260 docid022708 rev 6 smulbb r0, r4, r5 ; multiplies the bottom halfword of r4 with the bottom ; halfword of r5, multiplies results and writes to r0 smultt r0, r4, r5 ; multiplies the top halfword of r4 with the top ; halfword of r5, multiplies results ...

  • Page 123

    Docid022708 rev 6 123/260 pm0214 the stm32 cortex-m4 instruction set 259 restrictions in these instructions: • do not use either sp or pc • rdhi and rdlo must be different registers. Condition flags these instructions do not affect the condition code flags. Examples umull r0, r4, r5, r6 ; unsigned (...

  • Page 124: 3.7 Saturating

    The stm32 cortex-m4 instruction set pm0214 124/260 docid022708 rev 6 3.7 saturating instructions this section describes the saturating instructions. For signed n-bit saturation, this means that: • if the value to be saturated is less than -2 n-1 , the result returned is -2 n-1 • if the value to be s...

  • Page 125

    Docid022708 rev 6 125/260 pm0214 the stm32 cortex-m4 instruction set 259 3.7.1 ssat and usat signed saturate and unsigned saturate to any bit position, with optional shift before saturating. Syntax op{cond} rd, #n, rm {, shift #s} where: • op’ is one of: ssat: saturates a signed value to a signed ra...

  • Page 126

    The stm32 cortex-m4 instruction set pm0214 126/260 docid022708 rev 6 3.7.2 ssat16 and usat16 signed saturate and unsigned saturate to any bit position for two halfwords. Syntax op{cond} rd, #n, rm where: • op’ is one of: ssat16 saturates a signed halfword value to a signed range. Usat16 saturates a ...

  • Page 127

    Docid022708 rev 6 127/260 pm0214 the stm32 cortex-m4 instruction set 259 3.7.3 qadd and qsub saturating add and saturating subtract, signed. Syntax op{cond} {rd}, rn, rm op{cond} {rd}, rn, rm where: • op’ is one of: qadd: saturating 32-bit add. Qadd8: saturating four 8-bit integer additions. Qadd16:...

  • Page 128

    The stm32 cortex-m4 instruction set pm0214 128/260 docid022708 rev 6 ; of r2, saturates to 16 bits, writes to corresponding ; halfword of r4 qsub8 r4, r2, r5 ; subtracts bytes of r5 from the corresponding byte in r2 ; saturates to 8 bits, writes to corresponding byte ofr4. 3.7.4 qasx and qsax satura...

  • Page 129

    Docid022708 rev 6 129/260 pm0214 the stm32 cortex-m4 instruction set 259 ; subtracts top highword of r2 from bottom halfword of ; r4, saturates to 16 bits and writes to bottom halfword ; of r7 qsax r0, r3, r5 ; subtracts bottom halfword of r5 from top halfword of ; r3, saturates to 16 bits, writes t...

  • Page 130

    The stm32 cortex-m4 instruction set pm0214 130/260 docid022708 rev 6 ; from r5, saturates to 32 bits, writes to r0. 3.7.6 uqasx and uqsax saturating add and subtract with exchange and saturating subtract and add with exchange, unsigned. Syntax op{cond} {rd}, rm, rn where: • op’ is one of: uqasx add ...

  • Page 131

    Docid022708 rev 6 131/260 pm0214 the stm32 cortex-m4 instruction set 259 ; r4, saturates to 16 bits, writes to bottom halfword of r7 uqsax r0, r3, r5 ; subtracts bottom halfword of r5 from top halfword of ; r3, saturates to 16 bits, writes to top halfword of r0 ; adds bottom halfword of r4 to top ha...

  • Page 132

    The stm32 cortex-m4 instruction set pm0214 132/260 docid022708 rev 6 restrictions do not use sp and do not use pc. Condition flags these instructions do not affect the condition code flags. Examples uqadd16 r7, r4, r2; adds halfwords in r4 to corresponding halfword in r2, ; saturates to 16 bits, wri...

  • Page 133: 3.8 Packing

    Docid022708 rev 6 133/260 pm0214 the stm32 cortex-m4 instruction set 259 3.8 packing and unpacking instructions table 30 shows the instructions that operate on packing and unpacking data: table 30. Packing and unpacking instructions mnemonic brief description see pkh pack halfword pkhbt and pkhtb on...

  • Page 134

    The stm32 cortex-m4 instruction set pm0214 134/260 docid022708 rev 6 3.8.1 pkhbt and pkhtb pack halfword syntax op{cond} {rd}, rn, rm {, lsl #imm} op{cond} {rd}, rn, rm {, asr #imm} where: • op’ is one of: pkhbt pack halfword, bottom and top with shift. Pkhtb pack halfword, top and bottom with shift...

  • Page 135

    Docid022708 rev 6 135/260 pm0214 the stm32 cortex-m4 instruction set 259 3.8.2 sxt and uxt sign extend and zero extend. Syntax op{cond} {rd,} rm {, ror #n} op{cond} {rd}, rm {, ror #n} where: • op’ is one of: sxtb sign extends an 8-bit value to a 32-bit value. Sxth sign extends a 16-bit value to a 3...

  • Page 136

    The stm32 cortex-m4 instruction set pm0214 136/260 docid022708 rev 6 examples sxth r4, r6, ror #16 ; rotates r6 right by 16 bits, obtains bottom halfword ; of result, sign extends to 32 bits and writes to r4 uxtb r3, r10 ; extracts lowest byte of value in r10, zero extends, and ; writes to r3. 3.8.3...

  • Page 137: 3.9 Bitfield

    Docid022708 rev 6 137/260 pm0214 the stm32 cortex-m4 instruction set 259 restrictions do not use sp and do not use pc. Condition flags these instructions do not affect the flags. Examples sxtah r4, r8, r6, ror #16 ; rotates r6 right by 16 bits, obtains bottom ; halfword, sign extends to 32 bits, add...

  • Page 138

    The stm32 cortex-m4 instruction set pm0214 138/260 docid022708 rev 6 3.9.1 bfc and bfi bit field clear and bit field insert. Syntax bfc{cond} rd, #lsb, #width bfi{cond} rd, rn, #lsb, #width where: • ‘cond’ is an optional condition code, see conditional execution on page 64 . • ‘rd’ is the destinatio...

  • Page 139

    Docid022708 rev 6 139/260 pm0214 the stm32 cortex-m4 instruction set 259 3.9.2 sbfx and ubfx signed bit field extract and unsigned bit field extract. Syntax sbfx{cond} rd, rn, #lsb, #width ubfx{cond} rd, rn, #lsb, #width where: • ‘cond’ is an optional condition code, see conditional execution on pag...

  • Page 140

    The stm32 cortex-m4 instruction set pm0214 140/260 docid022708 rev 6 3.9.3 sxt and uxt sign extend and zero extend. Syntax sxtextend{cond} {rd,} rm {, ror #n} uxtextend{cond} {rd}, rm {, ror #n} where: • ‘extend’ is one of: b: extends an 8-bit value to a 32-bit value. H: extends a 16-bit value to a ...

  • Page 141

    Docid022708 rev 6 141/260 pm0214 the stm32 cortex-m4 instruction set 259 3.9.4 branch and control instructions table 32 shows the branch and control instructions: 3.9.5 b, bl, bx, and blx branch instructions. Syntax b{cond} label bl{cond} label bx{cond} rm blx{cond} rm where: • ‘b’ is branch (immedi...

  • Page 142

    The stm32 cortex-m4 instruction set pm0214 142/260 docid022708 rev 6 b cond label is the only conditional instruction that can be either inside or outside an it block. All other branch instructions must be conditional inside an it block, and must be unconditional outside the it block, see it on page...

  • Page 143

    Docid022708 rev 6 143/260 pm0214 the stm32 cortex-m4 instruction set 259 blx r0 ; branch with link and exchange (call) to a address stored ; in r0 3.9.6 cbz and cbnz compare and branch on zero, compare and branch on non-zero. Syntax cbz rn, label cbnz rn, label where: • ‘rn’ is the register holding ...

  • Page 144

    The stm32 cortex-m4 instruction set pm0214 144/260 docid022708 rev 6 3.9.7 it if-then condition instruction. Syntax it{x{y{z}}} cond where: • ‘x’ specifies the condition switch for the second instruction in the it block. • ‘y’ specifies the condition switch for the third instruction in the it block....

  • Page 145

    Docid022708 rev 6 145/260 pm0214 the stm32 cortex-m4 instruction set 259 other restrictions when using an it block are: • a branch or any instruction that modifies the pc must either be outside an it block or must be the last instruction inside the it block. These are: – add pc, pc, rm – mov pc, rm ...

  • Page 146

    The stm32 cortex-m4 instruction set pm0214 146/260 docid022708 rev 6 3.9.8 tbb and tbh table branch byte and table branch halfword. Syntax tbb [rn, rm] tbh [rn, rm, lsl #1] where: • ‘rn’ is the register containing the address of the table of branch lengths. If rn is pc, then the address of the table...

  • Page 147

    Docid022708 rev 6 147/260 pm0214 the stm32 cortex-m4 instruction set 259 branchtable_h dci ((casea - branchtable_h)/2) ; casea offset calculation dci ((caseb - branchtable_h)/2) ; caseb offset calculation dci ((casec - branchtable_h)/2) ; casec offset calculation casea ; an instruction sequence foll...

  • Page 148: 3.10 Floating-Point

    The stm32 cortex-m4 instruction set pm0214 148/260 docid022708 rev 6 3.10 floating-point instructions these instructions are only available if the fpu is included, and enabled, in the system. See enabling the fpu on page 256 for information about enabling the floating-point unit. Table 34. Floating-...

  • Page 149

    Docid022708 rev 6 149/260 pm0214 the stm32 cortex-m4 instruction set 259 vmrs move to arm core register from floating-point system register vmrs on page 168 vmsr move to floating-point system register from arm core register vmsr on page 169 vmul multiply floating-point vmul on page 170 vneg floating...

  • Page 150

    The stm32 cortex-m4 instruction set pm0214 150/260 docid022708 rev 6 3.10.1 vabs floating-point absolute. Syntax vabs{cond}.F32 sd, sm where: • ‘cond’ is an optional condition code, see conditional execution on page 64 . • ‘sd, sm’ are the destination floating-point value and the operand floating-po...

  • Page 151

    Docid022708 rev 6 151/260 pm0214 the stm32 cortex-m4 instruction set 259 3.10.2 vadd floating-point add syntax vadd{cond}.F32 {sd,} sn, sm where: • ‘cond’ is an optional condition code, see conditional execution on page 64 . • ‘sd’ is the destination floating-point value • ‘sn, sm’ are the operand f...

  • Page 152

    The stm32 cortex-m4 instruction set pm0214 152/260 docid022708 rev 6 3.10.3 vcmp, vcmpe compares two floating-point registers, or one floating-point register and zero. Syntax vcmp{e}{cond}.F32 sd, sm vcmp{e}{cond}.F32 sd, #0.0 where: • ‘cond’ is an optional condition code, see conditional execution ...

  • Page 153

    Docid022708 rev 6 153/260 pm0214 the stm32 cortex-m4 instruction set 259 3.10.4 vcvt, vcvtr between floating-point and integer converts a value in a register from floating-point to a 32-bit integer. Syntax vcvt{r}{cond}.Tm.F32 sd, sm vcvt{cond}.F32.Tm sd, sm where: • ‘r’ . If r is specified, the ope...

  • Page 154

    The stm32 cortex-m4 instruction set pm0214 154/260 docid022708 rev 6 3.10.5 vcvt between floating-point and fixed-point converts a value in a register from floating-point to and from fixed-point. Syntax vcvt{cond}.Td.F32 sd, sd, #fbits vcvt{cond}.F32.Td sd, sd, #fbits where: • ‘cond’ is an optional ...

  • Page 155

    Docid022708 rev 6 155/260 pm0214 the stm32 cortex-m4 instruction set 259 3.10.6 vcvtb, vcvtt converts between a half-precision value and a single-precision value. Syntax vcvt{y}{cond}.F32.F16 sd, sm vcvt{y}{cond}.F16.F32 sd, sm where: • ‘y’ specifies which half of the operand register sm or destinat...

  • Page 156

    The stm32 cortex-m4 instruction set pm0214 156/260 docid022708 rev 6 3.10.7 vdiv divides floating-point values. Syntax vdiv{cond}.F32 {sd,} sn, sm where: • ‘cond’ is an optional condition code, see conditional execution on page 64 . • ‘sd’ is the destination register • ‘sn, sm’ are the operand regis...

  • Page 157

    Docid022708 rev 6 157/260 pm0214 the stm32 cortex-m4 instruction set 259 3.10.8 vfma, vfms floating-point fused multiply accumulate and subtract. Syntax vfma{cond}.F32 {sd,} sn, sm vfms{cond}.F32 {sd,} sn, sm where: • ‘cond’ is an optional condition code, see conditional execution on page 64 . • ‘sd...

  • Page 158

    The stm32 cortex-m4 instruction set pm0214 158/260 docid022708 rev 6 3.10.9 vfnma, vfnms floating-point fused negate multiply accumulate and subtract. Syntax vfnma{cond}.F32 {sd,} sn, sm vfnms{cond}.F32 {sd,} sn, sm where: • ‘cond’ is an optional condition code, see conditional execution on page 64 ...

  • Page 159

    Docid022708 rev 6 159/260 pm0214 the stm32 cortex-m4 instruction set 259 3.10.10 vldm floating-point load multiple syntax vldm{mode}{cond}{.Size} rn{!}, list where: • ‘mode’ is the addressing mode: ia: increment after. The consecutive addresses start at the address specified in rn. Db: decrement bef...

  • Page 160

    The stm32 cortex-m4 instruction set pm0214 160/260 docid022708 rev 6 3.10.11 vldr loads a single extension register from memory syntax vldr{cond}{.64} dd, [rn{#imm}] vldr{cond}{.64} dd, label vldr{cond}{.64} dd, [pc, #imm}] vldr{cond}{.32} sd, [rn {, #imm}] vldr{cond}{.32} sd, label vldr{cond}{.32} ...

  • Page 161

    Docid022708 rev 6 161/260 pm0214 the stm32 cortex-m4 instruction set 259 3.10.12 vlma, vlms multiplies two floating-point values, and accumulates or subtracts the results. Syntax vlma{cond}.F32 sd, sn, sm vlms{cond}.F32 sd, sn, sm where: • ‘cond’ is an optional condition code, see conditional execut...

  • Page 162

    The stm32 cortex-m4 instruction set pm0214 162/260 docid022708 rev 6 3.10.13 vmov immediate move floating-point immediate syntax vmov{cond}.F32 sd, #imm where: • ‘cond’ is an optional condition code, see conditional execution on page 64 . • ‘sd’ is the branch destination • ‘imm’ is a floating-point ...

  • Page 163

    Docid022708 rev 6 163/260 pm0214 the stm32 cortex-m4 instruction set 259 3.10.14 vmov register copies the contents of one register to another. Syntax vmov{cond}.F64 dd, dm vmov{cond}.F32 sd, sm where: • ‘cond’ is an optional condition code, see conditional execution on page 64 . • ‘dd’ is the destin...

  • Page 164

    The stm32 cortex-m4 instruction set pm0214 164/260 docid022708 rev 6 3.10.15 vmov scalar to arm core register transfers one word of a doubleword floating-point register to an arm core register. Syntax vmov{cond} rt, dn[x] where: • ‘cond’ is an optional condition code, see conditional execution on pa...

  • Page 165

    Docid022708 rev 6 165/260 pm0214 the stm32 cortex-m4 instruction set 259 3.10.16 vmov arm core register to single precision transfers a single-precision register to and from an arm core register. Syntax vmov{cond} sn, rt vmov{cond} rt, sn where: • ‘cond’ is an optional condition code, see conditiona...

  • Page 166

    The stm32 cortex-m4 instruction set pm0214 166/260 docid022708 rev 6 3.10.17 vmov two arm core registers to two single precision transfers two consecutively numbered single-precision registers to and from two arm core registers. Syntax vmov{cond} sm, sm1, rt, rt2 vmov{cond} rt, rt2, sm, sm where: • ...

  • Page 167

    Docid022708 rev 6 167/260 pm0214 the stm32 cortex-m4 instruction set 259 3.10.18 vmov arm core register to scalar transfers one word to a floating-point register from an arm core register. Syntax vmov{cond}{.32} dd[x], rt where: • ‘cond’ is an optional condition code, see conditional execution on pa...

  • Page 168

    The stm32 cortex-m4 instruction set pm0214 168/260 docid022708 rev 6 3.10.19 vmrs move to arm core register from floating-point system register. Syntax vmrs{cond} rt, fpscr vmrs{cond} apsr_nzcv, fpscr where: • ‘cond’ is an optional condition code, see conditional execution on page 64 . • ‘rt’ is the...

  • Page 169

    Docid022708 rev 6 169/260 pm0214 the stm32 cortex-m4 instruction set 259 3.10.20 vmsr move to floating-point system register from arm core register. Syntax vmsr{cond} fpscr, rt where: • ‘cond’ is an optional condition code, see conditional execution on page 64 . • ‘rt’ is the general-purpose registe...

  • Page 170

    The stm32 cortex-m4 instruction set pm0214 170/260 docid022708 rev 6 3.10.21 vmul floating-point multiply. Syntax vmul{cond}.F32 {sd,} sn, sm where: • ‘cond’ is an optional condition code, see conditional execution on page 64 . • ‘sd’ is the destination floating-point value • ‘sn, sm’ are the operan...

  • Page 171

    Docid022708 rev 6 171/260 pm0214 the stm32 cortex-m4 instruction set 259 3.10.22 vneg floating-point negate. Syntax vneg{cond}.F32 sd, sm where: • ‘cond’ is an optional condition code, see conditional execution on page 64 . • ‘sd’ is the destination floating-point value • ‘sm’ is the operand floatin...

  • Page 172

    The stm32 cortex-m4 instruction set pm0214 172/260 docid022708 rev 6 3.10.23 vnmla, vnmls, vnmul floating-point multiply with negation followed by add or subtract. Syntax vnmla{cond}.F32 sd, sn, sm vnmls{cond}.F32 sd, sn, sm vnmul{cond}.F32 {sd,} sn, sm where: • ‘cond’ is an optional condition code,...

  • Page 173

    Docid022708 rev 6 173/260 pm0214 the stm32 cortex-m4 instruction set 259 3.10.24 vpop floating-point extension register pop. Syntax vpop{cond}{.Size} list where: • ‘cond’ is an optional condition code, see conditional execution on page 64 . • ‘size’ is an optional data size specifier. If present, it...

  • Page 174

    The stm32 cortex-m4 instruction set pm0214 174/260 docid022708 rev 6 3.10.25 vpush floating-point extension register push. Syntax vpush{cond}{.Size} list where: • ‘cond’ is an optional condition code, see conditional execution on page 64 . • ‘size’ is an optional data size specifier. If present, it ...

  • Page 175

    Docid022708 rev 6 175/260 pm0214 the stm32 cortex-m4 instruction set 259 3.10.26 vsqrt floating-point square root. Syntax vsqrt{cond}.F32 sd, sm where: • ‘cond’ is an optional condition code, see conditional execution on page 64 . • ‘sd’ is the destination floating-point value • ‘sm’ is the operand ...

  • Page 176

    The stm32 cortex-m4 instruction set pm0214 176/260 docid022708 rev 6 3.10.27 vstm floating-point store multiple. Syntax vstm{mode}{cond}{.Size} rn{!}, list where: • ‘mode’ is the addressing mode: ia increment after. The consecutive addresses start at the address specified in rn. This is the default ...

  • Page 177

    Docid022708 rev 6 177/260 pm0214 the stm32 cortex-m4 instruction set 259 3.10.28 vstr floating-point store. Syntax vstr{cond}{.32} sd, [rn{, #imm}] vstr{cond}{.64} dd, [rn{, #imm}] where: • ‘cond’ is an optional condition code, see conditional execution on page 64 . • ‘32, 64’ are the optional data ...

  • Page 178

    The stm32 cortex-m4 instruction set pm0214 178/260 docid022708 rev 6 3.10.29 vsub floating-point subtract. Syntax vsub{cond}.F32 {sd,} sn, sm where: • ‘cond’ is an optional condition code, see conditional execution on page 64 . • ‘sd’ is the destination floating-point value • ‘sn, sm’ are the operan...

  • Page 179

    Docid022708 rev 6 179/260 pm0214 the stm32 cortex-m4 instruction set 259 3.11 miscellaneous instructions table 35 shows the remaining cortex-m4 instructions: table 35. Miscellaneous instructions mnemonic brief description see bkpt breakpoint bkpt on page 180 cpsid change processor state, disable int...

  • Page 180

    The stm32 cortex-m4 instruction set pm0214 180/260 docid022708 rev 6 3.11.1 bkpt breakpoint. Syntax bkpt #imm where: • ‘imm’ is an expression evaluating to an integer in the range 0-255 (8-bit value). Operation the bkpt instruction causes the processor to enter debug state. Debug tools can use this ...

  • Page 181

    Docid022708 rev 6 181/260 pm0214 the stm32 cortex-m4 instruction set 259 3.11.2 cps change processor state. Syntax cpseffect iflags where: • ‘effect’ is one of: ie: clears the special purpose register. Id: sets the special purpose register. • ‘iflags’ is a sequence of one or more flags: i: set or cl...

  • Page 182

    The stm32 cortex-m4 instruction set pm0214 182/260 docid022708 rev 6 3.11.3 dmb data memory barrier. Syntax dmb{cond} where: ‘cond’ is an optional condition code, see conditional execution on page 64 . Operation dmb acts as a data memory barrier. It ensures that all explicit memory accesses that app...

  • Page 183

    Docid022708 rev 6 183/260 pm0214 the stm32 cortex-m4 instruction set 259 3.11.4 dsb data synchronization barrier. Syntax dsb{cond} where: ‘cond’ is an optional condition code, see conditional execution on page 64 . Operation dsb acts as a special data synchronization memory barrier. Instructions tha...

  • Page 184

    The stm32 cortex-m4 instruction set pm0214 184/260 docid022708 rev 6 3.11.5 isb instruction synchronization barrier. Syntax isb{cond} where: ‘cond’ is an optional condition code, see conditional execution on page 64 . Operation isb acts as an instruction synchronization barrier. It flushes the pipel...

  • Page 185

    Docid022708 rev 6 185/260 pm0214 the stm32 cortex-m4 instruction set 259 3.11.6 mrs move the contents of a special register to a general-purpose register. Syntax mrs{cond} rd, spec_reg where: • ‘cond’ is an optional condition code, see conditional execution on page 64 . • ‘rd’ is the destination reg...

  • Page 186

    The stm32 cortex-m4 instruction set pm0214 186/260 docid022708 rev 6 3.11.7 msr move the contents of a general-purpose register into the specified special register. Syntax msr{cond} spec_reg, rn where: • ‘cond’ is an optional condition code, see conditional execution on page 64 . • ‘rn’ is the sourc...

  • Page 187

    Docid022708 rev 6 187/260 pm0214 the stm32 cortex-m4 instruction set 259 3.11.8 nop no operation. Syntax nop{cond} where: • ‘cond’ is an optional condition code, see conditional execution on page 64 . Operation nop does nothing. Nop is not necessarily a time-consuming nop. The processor might remove...

  • Page 188

    The stm32 cortex-m4 instruction set pm0214 188/260 docid022708 rev 6 3.11.9 sev send event. Syntax sev{cond} where: • ‘cond’ is an optional condition code, see conditional execution on page 64 . Operation sev is a hint instruction that causes an event to be signaled to all processors within a multip...

  • Page 189

    Docid022708 rev 6 189/260 pm0214 the stm32 cortex-m4 instruction set 259 3.11.10 svc supervisor call. Syntax svc{cond} #imm where: • ‘cond’ is an optional condition code, see conditional execution on page 64 . • ‘imm’ is an expression evaluating to an integer in the range 0-255 (8-bit value). Operat...

  • Page 190

    The stm32 cortex-m4 instruction set pm0214 190/260 docid022708 rev 6 3.11.11 wfe wait for event. Wfe is a hint instruction. Syntax wfe{cond} where: ‘cond’ is an optional condition code, see conditional execution on page 64 . Operation if the event register is 0, wfe suspends execution until one of t...

  • Page 191

    Docid022708 rev 6 191/260 pm0214 the stm32 cortex-m4 instruction set 259 3.11.12 wfi wait for interrupt. Syntax wfi{cond} where: • ‘cond’ is an optional condition code, see conditional execution on page 64 . Operation wfi is a hint instruction that suspends execution until one of the following event...

  • Page 192: 4 Core

    Core peripherals pm0214 192/260 docid022708 rev 6 4 core peripherals 4.1 about the stm32 cortex-m4 core peripherals the address map of the private peripheral bus (ppb) is: in register descriptions, • register type is described as follows: – rw: read and write. – ro: read-only. – wo: write-only. • re...

  • Page 193

    Docid022708 rev 6 193/260 pm0214 core peripherals 259 when memory regions overlap, a memory access is affected by the attributes of the region with the highest number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps region 7. The background re...

  • Page 194

    Core peripherals pm0214 194/260 docid022708 rev 6 4.2.1 mpu access permission attributes this section describes the mpu access permission attributes. The access permission bits, tex, c, b, s, ap, and xn, of the mpu_rasr register, control access to the corresponding memory region. If an access is mad...

  • Page 195

    Docid022708 rev 6 195/260 pm0214 core peripherals 259 table 40 shows the ap encodings that define the access permissions for privileged and unprivileged software. 4.2.2 mpu mismatch when an access violates the mpu permissions, the processor generates a memory management fault, see section 2.1.4: exc...

  • Page 196

    Core peripherals pm0214 196/260 docid022708 rev 6 ; r3 = attributes ; r4 = address ldr r0,=mpu_rnr ; 0xe000ed98, mpu region number register str r1, [r0, #0x0] ; region number bic r2, r2, #1 ; disable strh r2, [r0, #0x8] ; region size and enable str r4, [r0, #0x4] ; region base address strh r3, [r0, ...

  • Page 197

    Docid022708 rev 6 197/260 pm0214 core peripherals 259 ; r1 = address and region number in one ; r2 = size and attributes in one ldr r0, =mpu_rbar ; 0xe000ed9c, mpu region base register str r1, [r0, #0x0] ; region base address and ; region number combined with valid (bit 4) set to 1 str r2, [r0, #0x4...

  • Page 198

    Core peripherals pm0214 198/260 docid022708 rev 6 4.2.4 mpu design hints and tips to avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers might access. Ensure software uses aligned accesses of the correct size to access mpu register...

  • Page 199

    Docid022708 rev 6 199/260 pm0214 core peripherals 259 4.2.5 mpu type register (mpu_typer) address offset: 0x00 reset value: 0x0000 0800 required privilege: privileged the mpu_typer register indicates whether the mpu is present, and if so, how many regions it supports. 31 30 29 28 27 26 25 24 23 22 2...

  • Page 200

    Core peripherals pm0214 200/260 docid022708 rev 6 4.2.6 mpu control register (mpu_ctrl) address offset: 0x04 reset value: 0x0000 0000 required privilege: privileged the mpu_ctrl register: • enables the mpu • enables the default memory map background region • enables use of the mpu when in the hard f...

  • Page 201

    Docid022708 rev 6 201/260 pm0214 core peripherals 259 4.2.7 mpu region number register (mpu_rnr) address offset: 0x08 reset value: 0x0000 0000 required privilege: privileged the mpu_rnr register selects which memory region is referenced by the mpu_rbar and mpu_rasr registers. Bits 31:3 reserved, for...

  • Page 202

    Core peripherals pm0214 202/260 docid022708 rev 6 4.2.8 mpu region base address register (mpu_rbar) address offset: 0x0c reset value: 0x0000 0000 required privilege: privileged the mpu_rbar register defines the base address of the mpu region selected by the mpu_rnr register, and can update the value...

  • Page 203

    Docid022708 rev 6 203/260 pm0214 core peripherals 259 4.2.9 mpu region attribute and size register (mpu_rasr) address offset: 0x10 reset value: 0x0000 0000 required privilege: privileged the mpu_rasr register defines the region size and memory attributes of the mpu region specified by the mpu_rnr, a...

  • Page 204

    Core peripherals pm0214 204/260 docid022708 rev 6 size field values the size field defines the size of the mpu memory region specified by the mpu_rnr regsiter as follows: (region size in bytes) = 2 (size+1) the smallest permitted region size is 32b, corresponding to a size value of 4. Table 42 gives...

  • Page 205

    Docid022708 rev 6 205/260 pm0214 core peripherals 259 4.2.10 mpu register map table 43. Mpu register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 mpu_typer reserved iregion[7:0] dregion[7:0] reserved sep ara t e reset...

  • Page 206

    Core peripherals pm0214 206/260 docid022708 rev 6 0x1c mpu_rbar_a3 (1) addr[31:n]... Va li d r e gion[3:0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x20 mpu_rasr_a3 (2) reserved xn reserved ap[2:0] reserved tex[2:0] s c b srd[7:0] reserved size en able reset value ...

  • Page 207: 4.3

    Docid022708 rev 6 207/260 pm0214 core peripherals 259 4.3 nested vectored interrupt controller (nvic) this section describes the nested vectored interrupt controller (nvic) and the registers it uses. The nvic supports: • up to 81 interrupts (interrupt number depends on the stm32 device type; refer t...

  • Page 208

    Core peripherals pm0214 208/260 docid022708 rev 6 4.3.1 accessing the cortex-m4 nvic registers using cmsis cmsis functions enable software portability between different cortex-m profile processors. To access the nvic registers when using cmsis, use the following functions: table 45. Cmsis access nvi...

  • Page 209

    Docid022708 rev 6 209/260 pm0214 core peripherals 259 4.3.2 interrupt set-enable registers (nvic_iserx) address offset: 0x00 - 0x0b reset value: 0x0000 0000 required privilege: privileged 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 setena[31:16] rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs 15...

  • Page 210

    Core peripherals pm0214 210/260 docid022708 rev 6 4.3.3 interrupt clear-enable registers (nvic_icerx) address offset: 0x00 - 0x0b reset value: 0x0000 0000 required privilege: privileged the icer0-icer2 registers disable interrupts, and show which interrupts are enabled. 31 30 29 28 27 26 25 24 23 22...

  • Page 211

    Docid022708 rev 6 211/260 pm0214 core peripherals 259 4.3.4 interrupt set-pending registers (nvic_isprx) address offset: 0x00 - 0x0b reset value: 0x0000 0000 required privilege: privileged the ispr0-ispr2 registers force interrupts into the pending state, and show which interrupts are pending. 31 30...

  • Page 212

    Core peripherals pm0214 212/260 docid022708 rev 6 4.3.5 interrupt clear-pending registers (nvic_icprx) address offset: 0x00 - 0x0b reset value: 0x0000 0000 required privilege: privileged the icpr0-icpr2 registers remove the pending state from interrupts, and show which interrupts are pending. 31 30 ...

  • Page 213

    Docid022708 rev 6 213/260 pm0214 core peripherals 259 4.3.6 interrupt active bit registers (nvic_iabrx) address offset: 0x00- 0x0b reset value: 0x0000 0000 required privilege: privileged the iabr0-iabr2 registers indicate which interrupts are active. The bit assignments are: 31 30 29 28 27 26 25 24 ...

  • Page 214

    Core peripherals pm0214 214/260 docid022708 rev 6 4.3.7 interrupt priority registers (nvic_iprx) address offset: 0x00- 0x0b reset value: 0x0000 0000 required privilege: privileged the nvic_ipr0-ipr80 registers provide an 8-bit priority field for each interrupt. These registers are byte-accessible. E...

  • Page 215

    Docid022708 rev 6 215/260 pm0214 core peripherals 259 4.3.8 software trigger interrupt register (nvic_stir) address offset: 0xe00 reset value: 0x0000 0000 required privilege: when the usersetmpend bit in the scr is set to 1, unprivileged software can access the stir, see section 4.4.6: system contro...

  • Page 216

    Core peripherals pm0214 216/260 docid022708 rev 6 4.3.9 level-sensitive and pulse interrupts stm32 interrupts are both level-sensitive and pulse-sensitive. Pulse interrupts are also described as edge-triggered interrupts. A level-sensitive interrupt is held asserted until the peripheral deasserts th...

  • Page 217

    Docid022708 rev 6 217/260 pm0214 core peripherals 259 4.3.10 nvic design hints and tips ensure software uses correctly aligned register accesses. The processor does not support unaligned accesses to nvic registers. See the individual register descriptions for the supported access sizes. An interrupt...

  • Page 218

    Core peripherals pm0214 218/260 docid022708 rev 6 4.3.11 nvic register map this table shows the nvic register map and reset values. The base address of the main nvic register block is 0xe000e100. The nvic_stir register is located in a separate block at 0xe000ef00. Table 48. Nvic register map and res...

  • Page 219

    Docid022708 rev 6 219/260 pm0214 core peripherals 259 0x300 nvic_ipr0 ip[3] ip[2] ip[1] ip[0] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : : : 0x368 nvic_ipr25 reserved ip[101] ip[100] reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 scb re...

  • Page 220: 4.4

    Core peripherals pm0214 220/260 docid022708 rev 6 4.4 system control block (scb) the system control block (scb) provides system implementation information, and system control. This includes configuration, control, and reporting of the system exceptions. Table 49. Summary of the system control block ...

  • Page 221

    Docid022708 rev 6 221/260 pm0214 core peripherals 259 4.4.1 auxiliary control register (actlr) address offset: 0x00 (base adress = 0xe000 e008) reset value: 0x0000 0000 required privilege: privileged by default this register is set to provide optimum performance from the cortex-m4 processor, and doe...

  • Page 222

    Core peripherals pm0214 222/260 docid022708 rev 6 bit 2 disfold disables folding of it instructions: 0: enables it instructions folding. 1: disables it instructions folding. In some situations, the processor can start executing the first instruction in an it block while it is still executing the it ...

  • Page 223

    Docid022708 rev 6 223/260 pm0214 core peripherals 259 4.4.2 cpuid base register (cpuid) address offset: 0x00 reset value: 0x410f c241 required privilege: privileged the cpuid register contains the processor part number, version, and implementation information. 31 30 29 28 27 26 25 24 23 22 21 20 19 ...

  • Page 224

    Core peripherals pm0214 224/260 docid022708 rev 6 4.4.3 interrupt control and state register (icsr) address offset: 0x04 reset value: 0x0000 0000 required privilege: privileged the icsr: • provides: – a set-pending bit for the non-maskable interrupt (nmi) exception – set-pending and clear-pending bi...

  • Page 225

    Docid022708 rev 6 225/260 pm0214 core peripherals 259 bit 28 pendsvset: pendsv set-pending bit. Write: 0: no effect 1: change pendsv exception state to pending. Read: 0: pendsv exception is not pending 1: pendsv exception is pending writing 1 to this bit is the only way to set the pendsv exception s...

  • Page 226

    Core peripherals pm0214 226/260 docid022708 rev 6 4.4.4 vector table offset register (vtor) address offset: 0x08 reset value: 0x0000 0000 required privilege: privileged 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved tbloff[29:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 ...

  • Page 227

    Docid022708 rev 6 227/260 pm0214 core peripherals 259 4.4.5 application interrupt and reset control register (aircr) address offset: 0x0c reset value: 0xfa05 0000 required privilege: privileged the aircr provides priority grouping control for the exception model, endian status for data accesses, and...

  • Page 228

    Core peripherals pm0214 228/260 docid022708 rev 6 bits you might require more explanation here, and want to remove invalid rows from the table, and modify the entries in the number of columns. Determining preemption of an exception uses only the group priority field, see section 2.3.6: interrupt pri...

  • Page 229

    Docid022708 rev 6 229/260 pm0214 core peripherals 259 4.4.6 system control register (scr) address offset: 0x10 reset value: 0x0000 0000 required privilege: privileged the scr controls features of entry to and exit from low power state. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 1...

  • Page 230

    Core peripherals pm0214 230/260 docid022708 rev 6 4.4.7 configuration and control register (ccr) address offset: 0x14 reset value: 0x0000 0200 required privilege: privileged the ccr controls entry to thread mode and enables: • the handlers for nmi, hard fault and faults escalated by faultmask to ign...

  • Page 231

    Docid022708 rev 6 231/260 pm0214 core peripherals 259 bit 3 unalign_ trp enables unaligned access traps: 0: do not trap unaligned halfword and word accesses 1: trap unaligned halfword and word accesses. If this bit is set to 1, an unaligned access generates a usage fault. Unaligned ldm, stm, ldrd, a...

  • Page 232

    Core peripherals pm0214 232/260 docid022708 rev 6 4.4.8 system handler priority registers (shprx) the shpr1-shpr3 registers set the priority level, 0 to 255 of the exception handlers that have configurable priority. Shpr1-shpr3 are byte accessible. The system fault handlers and the priority field an...

  • Page 233

    Docid022708 rev 6 233/260 pm0214 core peripherals 259 system handler priority register 3 (shpr3) address: 0xe000 ed20 reset value: 0x0000 0000 required privilege: privileged 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 pri_11[7:4] pri_11[3:0] reserved rw rw rw rw r r r r 15 14 13 12 11 10 9 8 7 6...

  • Page 234

    Core peripherals pm0214 234/260 docid022708 rev 6 4.4.9 system handler control and state register (shcsr) address offset: 0x24 reset value: 0x0000 0000 required privilege: privileged the shcsr enables the system handlers, and indicates: • the pending status of the bus fault, memory management fault,...

  • Page 235

    Docid022708 rev 6 235/260 pm0214 core peripherals 259 bit 8 monitoract: debug monitor active bit, reads as 1 if debug monitor is active bit 7 svcallact: svc call active bit, reads as 1 if svc call is active bits 6:4 reserved, must be kept cleared bit 3 usgfaultact: usage fault exception active bit, ...

  • Page 236

    Core peripherals pm0214 236/260 docid022708 rev 6 4.4.10 configurable fault status register (cfsr; ufsr+bfsr+mmfsr) address offset: 0x28 reset value: 0x0000 0000 required privilege: privileged the following subsections describe the subregisters that make up the cfsr: • usage fault status register (u...

  • Page 237

    Docid022708 rev 6 237/260 pm0214 core peripherals 259 4.4.11 usage fault status register (ufsr) bits 31:26 reserved, must be kept cleared bit 25 divbyzero: divide by zero usage fault. When the processor sets this bit to 1, the pc value stacked for the exception return points to the instruction that ...

  • Page 238

    Core peripherals pm0214 238/260 docid022708 rev 6 4.4.12 bus fault status register (bfsr) bit 15 bfarvalid: bus fault address register (bfar) valid flag. The processor sets this bit to 1 after a bus fault where the address is known. Other faults can set this bit to 0, such as a memory management fau...

  • Page 239

    Docid022708 rev 6 239/260 pm0214 core peripherals 259 4.4.13 memory management fault address register (mmfsr) bit 7 mmarvalid: memory management fault address register (mmar) valid flag. If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler ...

  • Page 240

    Core peripherals pm0214 240/260 docid022708 rev 6 4.4.14 hard fault status register (hfsr) address offset: 0x2c reset value: 0x0000 0000 required privilege: privileged the hfsr gives information about events that activate the hard fault handler. This register is read, write to clear. This means that...

  • Page 241

    Docid022708 rev 6 241/260 pm0214 core peripherals 259 4.4.15 memory management fault address register (mmfar) address offset: 0x34 reset value: undefined required privilege: privileged 4.4.16 bus fault address register (bfar) address offset: 0x38 reset value: undefined required privilege: privileged...

  • Page 242

    Core peripherals pm0214 242/260 docid022708 rev 6 4.4.17 auxiliary fault status register (afsr) address offset: 0x3c reset value: undefined required privilege: privileged 4.4.18 system control block design hints and tips ensure software uses aligned accesses of the correct size to access the system ...

  • Page 243

    Docid022708 rev 6 243/260 pm0214 core peripherals 259 4.4.19 scb register map the table provides shows the system control block register map and reset values. The base address of the scb register block is 0xe000 ed00 for register described in table 52 . Table 52. Scb register map and reset values of...

  • Page 244

    Core peripherals pm0214 244/260 docid022708 rev 6 0x20 shpr3 pri15 pri14 reserved reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x24 shcrs reserved usg f a ul t ena bus f a ul t ena mem f a ul t ena sv call pended bus f a ul t pe nded mem f a ul t pende d usg f a ul t pended sys tick act pends v act r...

  • Page 245: 4.5 Systick

    Docid022708 rev 6 245/260 pm0214 core peripherals 259 4.5 systick timer (stk) the processor has a 24-bit system timer, systick, that counts down from the reload value to zero, reloads (wraps to) the value in the stk_load register on the next clock edge, then counts down on subsequent clocks. When th...

  • Page 246

    Core peripherals pm0214 246/260 docid022708 rev 6 4.5.1 systick control and status register (stk_ctrl) address offset: 0x00 reset value: 0x0000 0000 required privilege: privileged the systick ctrl register enables the systick features. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved count f...

  • Page 247

    Docid022708 rev 6 247/260 pm0214 core peripherals 259 4.5.2 systick reload value register (stk_load) address offset: 0x04 reset value: 0x0000 0000 required privilege: privileged 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved reload[23:16] rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5...

  • Page 248

    Core peripherals pm0214 248/260 docid022708 rev 6 4.5.3 systick current value register (stk_val) address offset: 0x08 reset value: 0x0000 0000 required privilege: privileged 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved current[23:16] rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 ...

  • Page 249

    Docid022708 rev 6 249/260 pm0214 core peripherals 259 4.5.4 systick calibration value register (stk_calib) address offset: 0x0c reset value: 0x0000000 required privilege: privileged the calib register indicates the systick calibration properties. 4.5.5 systick design hints and tips the systick count...

  • Page 250

    Core peripherals pm0214 250/260 docid022708 rev 6 4.5.6 systick register map the table provided shows the systick register map and reset values. The base address of the systick register block is 0xe000 e010. Table 54. Systick register map and reset values offset register 31 30 29 28 27 26 25 24 23 2...

  • Page 251: 4.6

    Docid022708 rev 6 251/260 pm0214 core peripherals 259 4.6 floating point unit (fpu) the cortex-m4f fpu implements the fpv4-sp floating-point extension. The fpu fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conve...

  • Page 252

    Core peripherals pm0214 252/260 docid022708 rev 6 4.6.1 coprocessor access control register (cpacr) address offset (from scb): 0x88 reset value: 0x0000000 required privilege: privileged the cpacr register specifies the access privileges for coprocessors. 4.6.2 floating-point context control register...

  • Page 253

    Docid022708 rev 6 253/260 pm0214 core peripherals 259 bit 31 aspen: enables control setting on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration, for floating-point context, on exception entry and exit. 0: disable control setting on exec...

  • Page 254

    Core peripherals pm0214 254/260 docid022708 rev 6 4.6.3 floating-point context address register (fpcar) address offset: 0x08 reset value: 0x0000000 required privilege: privileged the fpcar register holds the location of the unpopulated floating-point register space allocated on an exception stack fr...

  • Page 255

    Docid022708 rev 6 255/260 pm0214 core peripherals 259 bit 28 v: overflow condition code flag. Floating-point comparison operations update this flag. For more details on the result, refer to table 56 . 0: operation did not result in an overflow 1: operation resulted in an overflow. Bit 27 reserved. B...

  • Page 256

    Core peripherals pm0214 256/260 docid022708 rev 6 4.6.5 floating-point default status control register (fpdscr) address offset: 0x0c reset value: 0x0000000 required privilege: privileged the fpdscr register holds the default values for the floating-point status control data. 4.6.6 enabling the fpu t...

  • Page 257

    Docid022708 rev 6 257/260 pm0214 core peripherals 259 4.6.7 enabling and clearing fpu exception interrupts the fpu exception flags are generating an interrupt through the interrupt controller. The fpu interrupt is globally controlled through the interrupt controller. A mask bit is also provided in t...

  • Page 258

    Core peripherals pm0214 258/260 docid022708 rev 6 sp = sp + 0x60; } else if(lr == 0xffffffed) { sp = __get_psp() + 0x60 ; } fpscr_val = *(uint32_t*)sp; { check exception flags } fpscr_val &= (uint32_t)~0x8f ; // clear all exception flags *(uint32_t*)sp = fpscr_val; __dmb() ; } // fpu irq handler voi...

  • Page 259: 5 Revision

    Docid022708 rev 6 259/260 pm0214 revision history 259 5 revision history table 57. Document revision history date revision changes 20-feb-2012 1 initial release. 09-jul-2012 2 changed reset value in section 4.6.2: floating-point context control register (fpccr) . Added table 1: applicable products ....

  • Page 260

    Pm0214 260/260 docid022708 rev 6 important notice – please read carefully stmicroelectronics nv and its subsidiaries (“st”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. Purchasers shou...