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Xilinx I2S Product Manual
Summary of I2S
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I2s transmitter and i2s receiver v1.0 logicore ip product guide vivado design suite pg308 (v1.0) april 4, 2018.
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Table of contents chapter 1: ip facts ......................................................................................................... 4 features........................................................................................................................................4 ip facts...
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Simulating the example design.............................................................................................. 33 test bench for example design...............................................................................................34 appendix a: debugging ...........................
Page 4: Features
Chapter 1 ip facts the xilinx ® logicore™ ip i2s transmitter and logicore™ receiver cores are soft xilinx ip cores for use with the xilinx vivado ® design suite, which makes it easy to implement inter-ic-sound (i2s) interface used to connect audio devices for transmitting and receiving pcm audio. Fe...
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Logicore ip facts table tested design flows 3 design entry vivado ® design suite vivado ip integrator simulation for supported simulators, see the xilinx design tools: release notes guide . Synthesis vivado synthesis support provided by xilinx ® at the xilinx support web page notes: 1. For a complet...
Page 6: Applications
Chapter 2 overview the i2s tramsmitter and i2s receiver cores provide an easy way to interface the i2s based audio dac/adc. These ips require minimal register programming and also support any audio sampling rates. These ips can be used along side hdmi, displayport, and sdi for complete audio video s...
Page 7: License Checkers
Note : to verify that you need a license, check the license column of the ip catalog. Included means that a license is included with the vivado ® design suite; purchase means that you have to purchase a license to use the core. For more information about this core, visit the i2s tramsmitter and i2s ...
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Chapter 3 product specification the i2s tramsmitter and i2s receiver ips can be used to develop audio solution using i2s adc/ dacs. These ips support any sampling rate and are very easy to configure with minimal register programming. Figure 1: tx audio sampling aes3 audio decoder fifo register inter...
Page 9: Performance
Figure 2: rx audio sampling aes3 audio encoder fifo register interface i2s rx i2s timing gen sdata[3:0] sck lrclk axis audio (aes3) m_axis_aud_aclk axi4lite s_axi_ctrl_aclk aud_mclk x20720-042318 performance for full details about performance and resource use, visit the performance and resource use ...
Page 10: Port Descriptions
Port descriptions port names table 1: port names port name i/o clock description transmitter ports s_axi_ctrl_aclk i clock input clock for axi4-lite interface s_axi_ctrl_aresetn i reset active-low reset for axi4-lite interface s_axi_ctrl_* s_axi_ctrl axi4-lite interface aud_mclk i clock input audio ...
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Table 1: port names (cont'd) port name i/o clock description irq o interrupt active-high interrupt lrclk_out o lrclk output lr clock. Available when core is configured as master sclk_out o sclk output sck clock. Available when core is configured as master lrclk_in i lrclk input lr clock. Available w...
Page 12: Core Version (0X00)
Table 2: register address space (cont'd) address (hex) register name 0x50 aes channel status 0: register that returns the lsb 32 bit of the aes channel status 0x54 aes channel status 1: register that returns the next lsb 32 bit of the aes channel status 0x58 aes channel status 2: register that retur...
Page 13: Control Register (0X08)
Control register (0x08) this register provides capability to enable/disable the core. Table 5: transmitter control register (0×08) bit default value access type description 31:1 0 ro reserved 0 0x0 r/w enable: setting this bit to ‘1’ will enable the core operations. Setting this bit to ‘0’ disables ...
Page 14: I2S Timing Control (0X20)
Table 7: transmitter interrupt status (0×14) (cont'd) bit default value access type description 0 0 r/w aes block completed: this bit is set when a complete aes block has been received (192 aes frames). This bit is set every time the ip receives one block of audio. Write a ‘1’ to clear this flag. I2...
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Table 10: transmitter channel 2/3 control (0x34) bit default value access type description 31:3 reserved 2:0 0x2 r/w channel mux value: specify a value to multiplex the audio channel output. 0x0 : output on i2s channel 1 is disabled 0x1 : i2s channel 1 outputs the audio received on channel 0 /1 0x2 ...
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Table 12: transmitter channel 6/7 control (0x3c) (cont'd) bit default value access type description 2:0 0x4 r/w channel mux value: specify a value to multiplex the audio channel output. 0x0 : output on i2s channel 3 is disabled 0x1 : i2s channel 3 outputs the audio received on channel 0 /1 0x2 : i2s...
Page 17: Core Version (0X00)
Table 14: register address space (cont'd) address (hex) register name 0x34 channel 2/3 control: channel 2/3 control register 0x38 channel 4/5 control: channel 4/5 control register 0x3c channel 6/7 control: channel 6/7 control register 0x50 aes channel status 0: register to specify the lsb 32 bit of ...
Page 18: Control Register (0X08)
Table 16: receiver core configuration (0x04) (cont'd) bit default value access type description 7:1 rsvd 0 ro is i2s master: indicates if the core has been generated as an i2s master or slave. 1 = i2s master control register (0x08) this register provides capability to enable/disable the core. Table ...
Page 19: I2S Timing Control (0X20)
Table 19: receiver interrupt status (0×14) bit default value access type description 31:2 reserved 1 0 r/w1c overflow interrupt: this bit is set when the ip is not able to send all enabled audio channels in time. This interrupt would indicate loss of samples. Write a ‘1’ to clear this flag. 0 0 r/w1...
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Channel 2/3 control (0x34) the ip provides a mechanism to route the audio from any i2s input. For example, audio received on i2s channel 0 can be routed to any of the 8 audio channels. Similarly audio received on one i2s channel can be routed to all of the 8 audio channels. Table 22: receiver channe...
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Table 24: receiver channel 6/7 control (0x3c) bit default value access type description 31:3 reserved 2:0 0x4 r/w channel mux value: specify a value to multiplex the audio channel output. 0x0 : disabled 0x1 : audio received on i2s channel 3 is routed as audio channel 0 /1 0x2 : audio received on i2s...
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Chapter 4 designing with the core the i2s tx and rx ips can be used in systems to send and receive i2s audio. A typical use case is as shown below. Figure 3: system using tx rx audio source i2s tx audio sink i2s rx external i2s dac external i2s adc to speakers or amp line in axis axis mclk x20719-04...
Page 23: General Design Guidelines
General design guidelines use the example design each instance of the i2s tramsmitter and i2s receiver core created by the vivado design tool is delivered with an example design that can be implemented in a device and then simulated. This design can be used as a starting point for your own design or...
Page 24: Clocking
Clocking there are three possible clock inputs available. Ensure that a proper aud_clk is supplied so that the correct sclk can be generated by the ip. Audio clock is typically an interger multiple of 128×fs and is decided by the dac/adc being used. It is advisable to use a very stable clock source ...
Page 25: Interrupts
Note : it is not recommended to change this value at runtime. 2. Program the sclk divider. Note : it is not recommended to change this value at runtime. 3. Program the aes registers to specify the 192 bits of channel status value 4. Enable the core and latch the aes channel bit. Note : after asserti...
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Table 27: audio axis interface patterns bits [3:0] description 0001 start of audio block/channel 0 audio sample 0010 channel 0/2/4/6 audio data 0011 channel 1/3/5/7 audio data chapter 4: designing with the core pg308 (v1.0) april 4, 2018 www.Xilinx.Com [placeholder text] i2s transmitter and i2s rece...
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Chapter 5 design flow steps this section describes customizing and generating the core, constraining the core, and the simulation, synthesis and implementation steps that are specific to this ip core. More detailed information about the standard vivado ® design flows and the ip integrator can be fou...
Page 28: I2S Receiver Customize Ip
I2s receiver customize ip figure 5: i2s receiver configuration tab chapter 5: design flow steps pg308 (v1.0) april 4, 2018 www.Xilinx.Com [placeholder text] i2s transmitter and i2s receiver 28 send feedback.
Page 29: Field Descriptions
Figure 6: i2s transmitter configuration tab field descriptions • component name : the base name of the output files generated for the core. Names must begin with a letter and can be composed of any of the following characters: a- z, 0 to 9, and "_". • audio channels : specify the number of audio cha...
Page 30: User Parameters
User parameters the following table shows the relationship between the fields in the vivado ide and the user parameters (which can be viewed in the tool command language (tcl) console). Table 28: user parameters vivado ide parameters parameter name default value allowed value i2s receiver audio chan...
Page 31: Simulation
Clock placement audio clock, if supplied from an external source, should be connected to a clock capable io so that it can be used by fpga fabric. Banking this section is not applicable for this ip core. Transceiver placement this section is not applicable for this ip core. I/o standard and placemen...
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Chapter 6 example design this chapter contains information about the example design provided in the vivado design suite. The top module instantiates all components of the core and example design that are needed to implement the design in hardware, as shown below. This includes clocking wizard and re...
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Implementing the example design for details about synthesis and implementation, see the vivado design suite user guide: designing with ip ( ug896 ). After following the steps described in chapter 5: design flow steps , implement the example design as follows: 1. Right-click the core in the hierarchy...
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Test bench for example design this section contains information about the provided test bench in the vivado design suite figure 8: test bench axis data checker axis data generator exdes axis axis clk_in x20718-042318 the above figure shows the test bench for example design. The top-level test bench ...
Page 35: Documentation
Appendix a debugging this appendix includes details about resources available on the xilinx support website and debugging tools. If the ip requires a license key, the key must be verified. The vivado ® design tools have several license checkpoints for gating licensed ip through the flow. If the lice...
Page 36: Answer Records
Answer records answer records include information about commonly encountered problems, helpful information on how to resolve these problems, and any known issues with a xilinx product. Answer records are created and maintained daily ensuring that users have access to the most accurate information av...
Page 37: Hardware Debug
Hardware debug hardware issues can range from no audio to audio with noise. This section provides debug steps for common issues. Following are some of the common problems encountered and possible solutions: 1. No audio received/played: ensure that the adc/dac/codec is in slave mode. The i2s ips oper...
Page 38: Xilinx Resources
Appendix b additional resources and legal notices xilinx resources for support resources such as answers, documentation, downloads, and forums, see xilinx support . Documentation navigator and design hubs xilinx ® documentation navigator provides access to xilinx documents, videos, and support resou...
Page 39: References
References these documents provide supplemental material useful with this product guide: 1. Vivado design suite user guide: designing ip subsystems using ip integrator ( ug994 ) 2. Vivado design suite user guide: designing with ip ( ug896 ) 3. Vivado design suite user guide: getting started ( ug910 ...
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Please read: important legal notices the information disclosed to you hereunder (the "materials") is provided solely for the selection and use of xilinx products. To the maximum extent permitted by applicable law: (1) materials are made available "as is" and with all faults, xilinx hereby disclaims ...