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Xilinx KC705 User manual

Manual is about: Evaluation Board for the Kintex-7 FPGA

Summary of KC705

  • Page 1

    Kc705 evaluation board for the kintex-7 fpga user guide ug810 (v1.8) march 20, 2018.

  • Page 2: Revision History

    Kc705 evaluation board 2 ug810 (v1.8) march 20, 2018 www.Xilinx.Com revision history the following table shows the revision history for this document. Date version revision 03/20/2018 1.8 in table 1-1 , quad spi flash memory , and [ref 5] , added micron mt25ql128aba8esf-0sit as a possible part for u...

  • Page 3

    Kc705 evaluation board 3 ug810 (v1.8) march 20, 2018 www.Xilinx.Com 05/10/2013 1.3 updated figure 1-1 to show v 1.1 board. Updated table 1-1, page 10 : callout 1 to identify fansink, callouts 25and 26 pointing to user i/o. Added table 1-9 clock source to fpga u1 connections. Updated programmable use...

  • Page 4

    Kc705 evaluation board 4 ug810 (v1.8) march 20, 2018 www.Xilinx.Com table of contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 chapter 1: kc705 evaluation board features overview . . . ....

  • Page 5

    Kc705 evaluation board 5 ug810 (v1.8) march 20, 2018 www.Xilinx.Com documentation navigator and design hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

  • Page 6: Overview

    Kc705 evaluation board 6 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1 kc705 evaluation board features overview the kc705 evaluation board for the kintex®-7 fpga provides a hardware environment for developing and evaluating designs targeting the kintex-7 xc7k325t-2ffg900c fpga. The kc705 boar...

  • Page 7

    Kc705 evaluation board 7 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features • gtx transceivers ° fmc hpc connector (four gtx transceivers) ° fmc lpc connector (one gtx transceiver) ° sma connectors (one pair each for tx, rx, and refclk) ° pci express (eight lanes) ...

  • Page 8

    Kc705 evaluation board 8 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features ° user pushbuttons (five directional) ° cpu reset pushbutton ° user dip switch (4-pole gpio) ° user edge drive rotary encoder switch ° user sma gpio connectors (one pair) ° lcd character di...

  • Page 9: Feature Descriptions

    Kc705 evaluation board 9 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features feature descriptions figure 1-2 shows the kc705 board. Each numbered feature that is referenced in figure 1-2 is described in the sections that follow. Note: the image in figure 1-2 is for ...

  • Page 10

    Kc705 evaluation board 10 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features x-ref target - figure 1-2 figure 1-2: kc705 board components ug841_c1_02_042313 3 30 31 33 14 17 21 4 29 1 8 7 12 15 10 11 18 6 13 16 2 26 9 00 square callout references a component on the...

  • Page 11

    Kc705 evaluation board 11 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features 12 gtx transceivers embedded within fpga u1 9 13 p1 pci express edge connector 8-lane card edge connector 21 14 p5 sfp/sfp+ connector molex 74441-0010 22 15 u37 10/100/1000 tri-speed ether...

  • Page 12: Kintex-7 Fpga

    Kc705 evaluation board 12 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features note: jumper header locations are identified in appendix a, default switch and jumper settings . Kintex-7 fpga [ figure 1-2 , callout 1 ] the kc705 board is populated with the kintex-7 xc7...

  • Page 13

    Kc705 evaluation board 13 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features for full details on configuring the fpga, see 7 series fpgas configuration user guide (ug470) [ref 2] . Encryption key backup circuit fpga u1 implements bitstream encryption key technology...

  • Page 14: Ddr3 Memory Module

    Kc705 evaluation board 14 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features ddr3 memory module [ figure 1-2 , callout 2 ] the memory module at j1 is a 1 gb ddr3 small outline dual-inline memory module (sodimm). It provides volatile synchronous dynamic random acces...

  • Page 15

    Kc705 evaluation board 15 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features table 1-4: ddr3 memory connections to the fpga u1 fpga pin net name i/o standard j1 ddr3 memory pin number pin name ah12 ddr3_a0 sstl15 98 a0 ag13 ddr3_a1 sstl15 97 a1 ag12 ddr3_a2 sstl15 ...

  • Page 16

    Kc705 evaluation board 16 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features aa18 ddr3_d12 sstl15 22 dq12 ab18 ddr3_d13 sstl15 24 dq13 ae18 ddr3_d14 sstl15 34 dq14 ad18 ddr3_d15 sstl15 36 dq15 ag19 ddr3_d16 sstl15 39 dq16 ak19 ddr3_d17 sstl15 41 dq17 ag18 ddr3_d18 ...

  • Page 17

    Kc705 evaluation board 17 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features ah2 ddr3_d43 sstl15 159 dq43 ah4 ddr3_d44 sstl15 146 dq44 aj4 ddr3_d45 sstl15 148 dq45 ak1 ddr3_d46 sstl15 158 dq46 aj1 ddr3_d47 sstl15 160 dq47 af1 ddr3_d48 sstl15 163 dq48 af2 ddr3_d49 s...

  • Page 18

    Kc705 evaluation board 18 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features the kc705 ddr3 sodimm interface adheres to the constraints guidelines documented in the ddr3 design guidelines section of 7 series fpgas memory interface solutions y18 ddr3_dqs1_n diff_sst...

  • Page 19: Linear Bpi Flash Memory

    Kc705 evaluation board 19 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features user guide (ug586) [ref 3] . The kc705 ddr3 sodimm interface is a 40 Ω impedance implementation. Other memory interface details are available in ug586 and 7 series fpgas memory resources u...

  • Page 20

    Kc705 evaluation board 20 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features u23 flash_a6 lvcmos25 c2 a7 w24 flash_a7 lvcmos25 a3 a8 w23 flash_a8 lvcmos25 b3 a9 v20 flash_a9 lvcmos25 c3 a10 v19 flash_a10 lvcmos25 d3 a11 w26 flash_a11 lvcmos25 c4 a12 v25 flash_a12 l...

  • Page 21

    Kc705 evaluation board 21 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features additional fpga bitstreams can be stored and used for configuration by setting the warm boot start address (wbstar) register contained in 7 series fpgas. More information is available in t...

  • Page 22

    Kc705 evaluation board 22 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features figure 1-5 shows the connections of the linear bpi flash memory on the kc705 board. For more information about the micron pc28f00ap30tf part, see [ref 5] . X-ref target - figure 1-5 figure...

  • Page 23: Quad Spi Flash Memory

    Kc705 evaluation board 23 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features quad spi flash memory [ figure 1-2 , callout 4 ] the quad spi flash memory located at u7 on the back side of the board provides 128 mb of nonvolatile storage that can be used for configura...

  • Page 24: Sd Card Interface

    Kc705 evaluation board 24 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features the configuration section of 7 series fpgas configuration user guide (ug470) [ref 2] provides details on using the quad spi flash memory. Figure 1-6 shows the connections of the quad spi f...

  • Page 25

    Kc705 evaluation board 25 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features and the sd card connector (u9). Figure 1-7 shows the connections of the sd card interface on the kc705 board. Table 1-7 lists the sd card interface connections to the fpga. X-ref target - ...

  • Page 26: Usb Jtag Module

    Kc705 evaluation board 26 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features usb jtag module [ figure 1-2 , callout 6 ] jtag configuration is provided through a digilent onboard usb-to-jtag configuration logic module (u59) where a host computer accesses the kc705 b...

  • Page 27

    Kc705 evaluation board 27 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features configures the fpga with a temporary design to access and program the bpi or quad spi flash memory device. The jtag circuit is shown in figure 1-9 . X-ref target - figure 1-9 figure 1-9: j...

  • Page 28: Clock Generation

    Kc705 evaluation board 28 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features clock generation there are five clock sources available for the fpga fabric on the kc705 board (refer to table 1-8 ). Table 1-9 lists the pin-to-pin connections from each clock source to t...

  • Page 29

    Kc705 evaluation board 29 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features system clock source [ figure 1-2 , callout 7 ] the kc705 board has a 2.5v lvds differential 200 mhz oscillator (u6) soldered onto the back side of the board and wired to an fpga mrcc clock...

  • Page 30

    Kc705 evaluation board 30 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features the user clock circuit is shown in figure 1-11 . For more information about the silicon labs si570 see [ref 7] . Reference design files are available to demonstrate how to program the si57...

  • Page 31

    Kc705 evaluation board 31 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features termination resistor). The user-provided 2.5v differential clock circuit is shown in figure 1-12 . Gtx sma clock input [ figure 1-2 , callout 10 ] the kc705 board includes a pair of sma co...

  • Page 32

    Kc705 evaluation board 32 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features jitter attenuated clock [ figure 1-2 , callout 11 ] the kc705 board includes a silicon labs si5324 jitter attenuator u70 on the back side of the board. Fpga user logic can implement a cloc...

  • Page 33: Gtx Transceivers

    Kc705 evaluation board 33 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features for more information about the silicon labs si5324 see [ref 7] . Gtx transceivers [ figure 1-2 , callout 12 ] the kc705 board provides access to 16 gtx transceivers: • eight of the gtx tra...

  • Page 34

    Kc705 evaluation board 34 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features the gtx transceivers in 7 series fpgas are grouped into four channels described as quads. The reference clock for a quad can be sourced from the quad above or quad below the gtx quad of in...

  • Page 35: Pci Express Edge Connector

    Kc705 evaluation board 35 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features for more information on the gtx transceivers, see 7 series fpgas gtx transceivers user guide (ug476) [ref 12] . Pci express edge connector [ figure 1-2 , callout 13 ] the 8-lane pci expres...

  • Page 36

    Kc705 evaluation board 36 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features the pcie clock is input from the edge connector. It is ac coupled to the fpga through the mgtrefclk1 pins of quad 115. Pcie_clk_q0_p is connected to fpga u1 pin u8, and the _n net is conne...

  • Page 37

    Kc705 evaluation board 37 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features pcie_rx3_n t5 b28 petn3 integrated endpoint block receive pair gtxe2_channel_x0y4 pcie_rx4_p v6 b33 petp4 integrated endpoint block receive pair gtxe2_channel_x0y3 pcie_rx4_n v5 b34 petn4 ...

  • Page 38

    Kc705 evaluation board 38 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features table 1-12 lists the pcie edge connector connections for quad 115. Pcie_tx5_p u4 a39 perp5 integrated endpoint block transmit pair gtxe2_channel_x0y2 pcie_tx5_n u3 a40 pern5 integrated end...

  • Page 39

    Kc705 evaluation board 39 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features table 1-13 lists the pcie edge connector connections for quad 116. Mgtxtxp2_115_u4 u4 pcie_tx5_p a39 perp5 gtxe2_channel_x0y2 mgtxtxn2_115_u3 u3 pcie_tx5_n a40 pern5 gtxe2_channel_x0y2 mgt...

  • Page 40

    Kc705 evaluation board 40 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features for more information refer to 7 series fpgas gtx transceivers user guide (ug476) [ref 12] and 7 series fpgas integrated block for pci express user guide (axi) (pg054) [ref 13] . Mgtxrxp2_1...

  • Page 41: Sfp/sfp+ Connector

    Kc705 evaluation board 41 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features sfp/sfp+ connector [ figure 1-2 , callout 14 ] the kc705 board contains a small form-factor pluggable (sfp+) connector and cage assembly that accepts sfp or sfp+ modules. Figure 1-17 shows...

  • Page 42

    Kc705 evaluation board 42 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features table 1-14 lists the sfp+ module rx and tx connections to the fpga. Table 1-15 lists the sfp+ module control and status connections to the fpga. Table 1-14: fpga u1 to sfp+ module connecti...

  • Page 43

    Kc705 evaluation board 43 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features 10/100/1000 tri-speed ethernet phy [ figure 1-2 , callout 15 ] the kc705 board utilizes the marvell alaska phy device (88e1111) u37 for ethernet communications at 10, 100, or 1000 mb/s. Th...

  • Page 44

    Kc705 evaluation board 44 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features sgmii gtx transceiver clock generator [ figure 1-2 , callout 16 ] an integrated circuit systems ics844021i chip (u2) generates a high-quality, low-jitter, 125 mhz lvds clock from a 25 mhz ...

  • Page 45: Usb-to-Uart Bridge

    Kc705 evaluation board 45 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features details about the tri-mode ethernet mac core are provided in logicore ip tri-mode ethernet mac user guide (pg051) [ref 14] . For more information about the marvell 88e1111, see [ref 15] . ...

  • Page 46

    Kc705 evaluation board 46 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features connector j6). The cp2103gm is powered by the usb 5v provided by the host pc when the usb cable is plugged into the usb port on the kc705 board. Xilinx uart ip is expected to be implemente...

  • Page 47: Hdmi Video Output

    Kc705 evaluation board 47 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features hdmi video output [ figure 1-2 , callout 18 ] the kc705 board provides a high-definition multimedia interface (hdmi) video output using the analog devices adv7511kstz-p hdmi transmitter (u...

  • Page 48

    Kc705 evaluation board 48 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features figure 1-19 shows the hdmi codec circuit. X-ref target - figure 1-19 figure 1-19: hdmi codec circuit ug810_c1_19_031214 gnd gnd vcc3v3 gnd gnd oe gnd out vcc d31 d32 d33 d34 d35 d12 d13 d1...

  • Page 49

    Kc705 evaluation board 49 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features table 1-21 lists the connections between the codec and the fpga. Table 1-21: fpga to hdmi codec connections (adv7511) u1 fpga pin schematic net name i/o standard adv7511 (u65) pin number p...

  • Page 50: Lcd Character Display

    Kc705 evaluation board 50 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features table 1-22 lists the connections between the codec and the hdmi connector p6. For more information about the adv7511kstz-p part, see [ref 17] . Lcd character display [ figure 1-2 , callout...

  • Page 51

    Kc705 evaluation board 51 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features the character display runs at 5.0v and is connected to the fpga's 1.5v hp bank 33 through a texas instruments txs0108e 8-bit bidirectional voltage level translator (u10). Figure 1-21 shows...

  • Page 52: I2C Bus Switch

    Kc705 evaluation board 52 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features table 1-23 lists the connections between the fpga and the lcd header. For more information about the displaytech s162d lcd, see [ref 18] . I2c bus switch [ figure 1-2 , callout 20 ] the kc...

  • Page 53: Status Leds

    Kc705 evaluation board 53 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features table 1-24 lists the address for each device on the i2c bus. For more information about the ti pca9548 part, see [ref 19] . Status leds [ figure 1-2 , callout 21 ] table 1-25 defines the s...

  • Page 54: Ethernet Phy Status Leds

    Kc705 evaluation board 54 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features ethernet phy status leds [ figure 1-2 , callout 21 ] the ethernet phy status leds are mounted to be visible through the metal bracket on the left edge of the kc705 board when it is install...

  • Page 55

    Kc705 evaluation board 55 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features ° gpio_sw_[neswc]: sw2, sw3, sw4, sw6, sw5 ° cpu_reset: sw7 • 4-position user dip switch (callout 24 ) ° gpio_dip_sw[3:0]: sw11 • user rotary switch (callout 25 , hidden beneath the lcd) °...

  • Page 56

    Kc705 evaluation board 56 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features user pushbuttons [ figure 1-2 , callout 23 ] figure 1-26 shows the user pushbutton switch circuits. X-ref target - figure 1-26 figure 1-26: user pushbuttons ug810_c1_26_031214 vadj gpio sw...

  • Page 57

    Kc705 evaluation board 57 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features cpu reset pushbutton [ figure 1-2 , callout 37 ] figure 1-27 shows the cpu reset pushbutton circuit. Gpio dip switch [ figure 1-2 , callout 24 ] figure 1-28 shows the gpio dip switch circu...

  • Page 58

    Kc705 evaluation board 58 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features rotary switch figure 1-29 shows the rotary switch sw8. [ figure 1-2 , callout 25 ] x-ref target - figure 1-29 figure 1-29: rotary switch sw8 v cc 1v8 gnd gnd sw8 r31 4.7k 1/10w 5% r30 4.7k...

  • Page 59

    Kc705 evaluation board 59 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features gpio sma connectors figure 1-30 shows the gpio smas j13 and j14. [ figure 1-2 , callout 26 ] table 1-27 lists the gpio connections to fpga u1. X-ref target - figure 1-30 figure 1-30: gpio ...

  • Page 60: Switches

    Kc705 evaluation board 60 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features switches [ figure 1-2 , callout 27 - 28 ] the kc705 evaluation board includes a power and a configuration switch: • power on/off slide switch sw15 (callout 27 ) • fpga_prog_b sw14, active-...

  • Page 61

    Kc705 evaluation board 61 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features caution! Do not plug a pc atx power supply 6-pin connector into j49 on the kc705 board the atx 6-pin connector has a different pinout than j49. Connecting an atx 6-pin connector into j49 w...

  • Page 62

    Kc705 evaluation board 62 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features figure 1-33 shows sw14. Configuration mode and upper linear flash address switch (sw13) [ figure 1-2 , callout 29 ] fpga configuration mode: dip switch sw13 positions 3, 4, and 5 control w...

  • Page 63

    Kc705 evaluation board 63 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features fpga mezzanine card interface [ figure 1-2 , callout 30 - 31 ] the kc705 evaluation board for the kintex-7 fpga supports the vita 57.1 fpga mezzanine card (fmc) specification by providing ...

  • Page 64

    Kc705 evaluation board 64 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features ° 34 la pairs (la00-la33) ° 24 ha pairs (ha00-ha23) • 4 gtx transceivers • 2 gtx clocks • 2 differential clocks • 159 ground and 15 power connections the hpc signals are distributed across...

  • Page 65

    Kc705 evaluation board 65 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features c2 fmc_hpc_dp0_c2m_p d2 d1 pwrctl1_vcc4a_pg c3 fmc_hpc_dp0_c2m_n d1 d4 fmc_hpc_gbtclk0_m2c_p lvds c8 c6 fmc_hpc_dp0_m2c_p e4 d5 fmc_hpc_gbtclk0_m2c_n lvds c7 c7 fmc_hpc_dp0_m2c_n e3 d8 fmc...

  • Page 66

    Kc705 evaluation board 66 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features e9 fmc_hpc_ha09_p lvds f12 f8 fmc_hpc_ha04_n lvds e11 e10 fmc_hpc_ha09_n lvds e13 f10 fmc_hpc_ha08_p lvds e14 e12 fmc_hpc_ha13_p lvds l16 f11 fmc_hpc_ha08_n lvds e15 e13 fmc_hpc_ha13_n lvd...

  • Page 67

    Kc705 evaluation board 67 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features g15 fmc_hpc_la12_p lvds c29 h13 fmc_hpc_la07_p lvds e28 g16 fmc_hpc_la12_n lvds b29 h14 fmc_hpc_la07_n lvds d28 g18 fmc_hpc_la16_p lvds b27 h16 fmc_hpc_la11_p lvds g27 g19 fmc_hpc_la16_n l...

  • Page 68

    Kc705 evaluation board 68 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features lpc connector j2 [ figure 1-2 , callout 31 ] the 160-pin lpc connector defined by the fmc specification ( figure b-2, page 87 ) provides connectivity for up to: • 68 single-ended or 34 dif...

  • Page 69

    Kc705 evaluation board 69 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features • 2 differential clocks • 61 ground and 9 power connections table 1-29: lpc connections, j2 to fpga u1 j2 pin schematic net name i/o standard u1 fpga pin j2 pin schematic net name i/o stan...

  • Page 70

    Kc705 evaluation board 70 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features g3 fmc_lpc_clk1_m2c_n lvds ah29 h2 fmc_lpc_prsnt_m2c_b lvcmos25 g6 fmc_lpc_la00_cc_p lvcoms1 8 ad23 h4 fmc_lpc_clk0_m2c_p lvds af22 g7 fmc_lpc_la00_cc_n lvcoms1 8 ae24 h5 fmc_lpc_clk0_m2c_...

  • Page 71: Power Management

    Kc705 evaluation board 71 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features power management [ figure 1-2 , callout 32 ] the kc705 board uses power regulators and pmbus compliant digital pwm system controllers from texas instruments to supply core and auxiliary vo...

  • Page 72

    Kc705 evaluation board 72 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features the kc705 board power distribution diagram is shown in figure 1-35 . X-ref target - figure 1-35 figure 1-35: kc705 board onboard power regulators ug810_c1_35_031214 vccaux vcc3v3 vadj vcc1...

  • Page 73

    Kc705 evaluation board 73 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features the kc705 board core and auxiliary voltages are listed in table 1-30 . Table 1-30: onboard power system devices device type reference designator description power rail net name power rail ...

  • Page 74

    Kc705 evaluation board 74 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features fmc_vadj voltage control the fmc_vadj rail is set to 2.5v. When the kc705 board is powered on, the state of the fmc_vadj_on_b signal wired to header j65 is sampled by the texas instruments...

  • Page 75

    Kc705 evaluation board 75 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features monitoring voltage and current voltage and current monitoring and control are available for selected power rails through the texas instruments fusion digital power gui. The three onboard t...

  • Page 76

    Kc705 evaluation board 76 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features table 1-31 defines the voltage and current values for each power rail controlled by the ucd9248 pmbus controller at address 52 (u55). Table 1-32 defines the voltage and current values for ...

  • Page 77

    Kc705 evaluation board 77 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features table 1-33 defines the voltage and current values for each power rail controlled by the ucd9248 pmbus controller at address 54 (u89). For more information about the ucd9248pfc, ptd08a010w,...

  • Page 78: Xadc Header

    Kc705 evaluation board 78 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features xadc header [ figure 1-2 , callout 33 ] 7 series fpgas provide an analog-to-digital converter (xadc) block. The xadc block includes a dual 12-bit, 1 msps analog-to-digital converter (adc) ...

  • Page 79

    Kc705 evaluation board 79 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features jumper j47 can be used to select either an external differential voltage reference (xadc_vref) or on-chip voltage reference (jumper j47 2–3) for the analog-to-digital converter. For extern...

  • Page 80: Configuration Options

    Kc705 evaluation board 80 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features configuration options the fpga on the kc705 board can be configured by the following methods: • master bpi (uses the linear bpi flash memory) • master spi (uses the quad spi flash memory) ...

  • Page 81

    Kc705 evaluation board 81 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features figure 1-39 shows mode switch sw13. The mode pins settings on sw13 determine if the linear bpi or the quad spi flash memory is used for configuring the fpga. Dip switch sw13 also provides ...

  • Page 82

    Kc705 evaluation board 82 ug810 (v1.8) march 20, 2018 www.Xilinx.Com chapter 1: kc705 evaluation board features x-ref target - figure 1-40 figure 1-40: kc705 board configuration circuit ug810_c1_40_070114 rst_b clk we_b oe_b adv_b d[15:00] a[27:01] u58 p30 1gb flash memory d q hold_b w_b c s-b u7 n2...

  • Page 83

    Kc705 evaluation board 83 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix a default switch and jumper settings dip switch sw11 user gpio see figure 1-2, page 10 item 24 for location of sw11. Default settings are shown in figure a-1 and details are listed in table a-1 . X-ref target - figure a-1 ...

  • Page 84: Settings

    Kc705 evaluation board 84 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix a: default switch and jumper settings dip switch sw13 mode and flash memory address settings see figure 1-2, page 10 item 29 for location of sw13. Default settings are shown in figure a-2 and details are listed in table a-...

  • Page 85

    Kc705 evaluation board 85 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix a: default switch and jumper settings 5 j56 none u56 ucd9248 reset_b = logic 1 (not reset) 40 6 j65 1-2 fmc vadj = on 36 7 j68 1-2 xadc_vcc5v0 =vcc5v0 (5v) 31 3-pin 8 j27 2-3 sfp rx bw = full 22 9 j28 2-3 sfp tx bw = full ...

  • Page 86

    Kc705 evaluation board 86 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix b vita 57.1 fmc connector pinouts figure b-1 shows the pinout of the fpga mezzanine card (fmc) high pin count (hpc) connector defined by the vita 57.1 fmc specification. For a description of how the kc705 board implements ...

  • Page 87

    Kc705 evaluation board 87 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix b: vita 57.1 fmc connector pinouts figure b-2 shows the pinout of the fmc card low pin count (lpc) connector defined by the vita 57.1 fmc specification. For a description of how the kc705 board implements the fmc specifica...

  • Page 88: Kc705 Board Xdc Listing

    Kc705 evaluation board 88 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix c master constraints file listing the kc705 board xilinx® design constraints (xdc) file template provides for designs targeting the kc705 board. Net names in the constraints listed below correlate with net names on the lat...

  • Page 89

    Kc705 evaluation board 89 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix c: master constraints file listing set_property package_pin w28 [get_ports rec_clock_c_n] set_property iostandard lvds_25 [get_ports rec_clock_c_n] set_property package_pin w27 [get_ports rec_clock_c_p] set_property iostan...

  • Page 90

    Kc705 evaluation board 90 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix c: master constraints file listing set_property package_pin ah19 [get_ports ddr3_d20] set_property iostandard sstl15 [get_ports ddr3_d20] set_property package_pin aj19 [get_ports ddr3_d21] set_property iostandard sstl15 [g...

  • Page 91

    Kc705 evaluation board 91 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix c: master constraints file listing set_property iostandard sstl15 [get_ports ddr3_d49] set_property package_pin ae4 [get_ports ddr3_d50] set_property iostandard sstl15 [get_ports ddr3_d50] set_property package_pin ae3 [get...

  • Page 92

    Kc705 evaluation board 92 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix c: master constraints file listing set_property package_pin ak10 [get_ports ddr3_a14] set_property iostandard sstl15 [get_ports ddr3_a14] set_property package_pin ak11 [get_ports ddr3_a15] set_property iostandard sstl15 [g...

  • Page 93

    Kc705 evaluation board 93 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix c: master constraints file listing set_property iostandard sstl15 [get_ports ddr3_dm5] set_property package_pin af6 [get_ports ddr3_dm6] set_property iostandard sstl15 [get_ports ddr3_dm6] set_property package_pin ac7 [get...

  • Page 94

    Kc705 evaluation board 94 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix c: master constraints file listing set_property iostandard lvcmos25 [get_ports flash_d8] set_property package_pin p29 [get_ports flash_d9] set_property iostandard lvcmos25 [get_ports flash_d9] set_property package_pin r29 ...

  • Page 95

    Kc705 evaluation board 95 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix c: master constraints file listing set_property package_pin n20 [get_ports flash_a21] set_property iostandard lvcmos25 [get_ports flash_a21] set_property package_pin n19 [get_ports flash_a22] set_property iostandard lvcmos...

  • Page 96

    Kc705 evaluation board 96 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix c: master constraints file listing set_property package_pin b2 [get_ports fmc_hpc_dp2_c2m_p] set_property package_pin b5 [get_ports fmc_hpc_dp2_m2c_n] set_property package_pin b6 [get_ports fmc_hpc_dp2_m2c_p] set_property ...

  • Page 97

    Kc705 evaluation board 97 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix c: master constraints file listing set_property package_pin c29 [get_ports fmc_hpc_la12_p] set_property iostandard lvcmos25 [get_ports fmc_hpc_la12_p] set_property package_pin a26 [get_ports fmc_hpc_la13_n] set_property io...

  • Page 98

    Kc705 evaluation board 98 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix c: master constraints file listing set_property iostandard lvcmos25 [get_ports fmc_hpc_la27_n] set_property package_pin c19 [get_ports fmc_hpc_la27_p] set_property iostandard lvcmos25 [get_ports fmc_hpc_la27_p] set_propert...

  • Page 99

    Kc705 evaluation board 99 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix c: master constraints file listing set_property package_pin b14 [get_ports fmc_hpc_ha07_p] set_property iostandard lvcmos25 [get_ports fmc_hpc_ha07_p] set_property package_pin e15 [get_ports fmc_hpc_ha08_n] set_property io...

  • Page 100

    Kc705 evaluation board 100 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix c: master constraints file listing set_property iostandard lvcmos25 [get_ports fmc_hpc_ha22_n] set_property package_pin l11 [get_ports fmc_hpc_ha22_p] set_property iostandard lvcmos25 [get_ports fmc_hpc_ha22_p] set_proper...

  • Page 101

    Kc705 evaluation board 101 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix c: master constraints file listing set_property package_pin ak20 [get_ports fmc_lpc_la06_p] set_property iostandard lvcmos25 [get_ports fmc_lpc_la06_p] set_property package_pin ah25 [get_ports fmc_lpc_la07_n] set_property...

  • Page 102

    Kc705 evaluation board 102 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix c: master constraints file listing set_property iostandard lvcmos25 [get_ports fmc_lpc_la21_n] set_property package_pin ag27 [get_ports fmc_lpc_la21_p] set_property iostandard lvcmos25 [get_ports fmc_lpc_la21_p] set_prope...

  • Page 103

    Kc705 evaluation board 103 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix c: master constraints file listing set_property iostandard lvcmos25 [get_ports gpio_dip_sw2] set_property package_pin y28 [get_ports gpio_dip_sw3] set_property iostandard lvcmos25 [get_ports gpio_dip_sw3] #gpio pushbutton...

  • Page 104

    Kc705 evaluation board 104 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix c: master constraints file listing #gpio user sma set_property package_pin y24 [get_ports user_sma_gpio_n] set_property iostandard lvcmos25 [get_ports user_sma_gpio_n] set_property package_pin y23 [get_ports user_sma_gpio...

  • Page 105

    Kc705 evaluation board 105 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix c: master constraints file listing set_property iostandard lvcmos25 [get_ports hdmi_r_spdif] set_property package_pin h20 [get_ports hdmi_r_vsync] set_property iostandard lvcmos25 [get_ports hdmi_r_vsync] set_property pac...

  • Page 106

    Kc705 evaluation board 106 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix c: master constraints file listing set_property package_pin u25 [get_ports phy_rxd1] set_property iostandard lvcmos25 [get_ports phy_rxd1] set_property package_pin t25 [get_ports phy_rxd2] set_property iostandard lvcmos25...

  • Page 107

    Kc705 evaluation board 107 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix c: master constraints file listing set_property package_pin g8 [get_ports sgmiiclk_q0_p] #pmbus set_property package_pin ab14 [get_ports pmbus_alert_ls] set_property iostandard lvcmos15 [get_ports pmbus_alert_ls] set_prop...

  • Page 108

    Kc705 evaluation board 108 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix c: master constraints file listing #xadc set_property package_pin ab25 [get_ports xadc_gpio_0] set_property iostandard lvcmos25 [get_ports xadc_gpio_0] set_property package_pin aa25 [get_ports xadc_gpio_1] set_property io...

  • Page 109

    Kc705 evaluation board 109 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix d board setup installing kc705 board in a pc chassis installation of the kc705 board inside a computer chassis is required when developing or testing pci express functionality. When the kc705 board is used inside a comput...

  • Page 110

    Kc705 evaluation board 110 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix d: board setup 7. Connect the atx power supply to the kc705 board using the atx power supply adapter cable as shown in figure d-1 : a. Plug the 6-pin 2 x 3 molex connector on the adapter cable into j49 on the kc705 board....

  • Page 111: Dimensions

    Kc705 evaluation board 111 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix e board specifications dimensions height 5.5 in (14.0 cm) length 10.5 in (26.7 cm) note: the kc705 board height exceeds the standard 4.376 in (11.15 cm) height of a pci express card. Environmental temperature operating: 0...

  • Page 112: Declaration of Conformity

    Kc705 evaluation board 112 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix f regulatory compliance and information this product is designed and tested to conform to the european union directives and standards described in this section. Refer to the master answer record concerning the ce requirem...

  • Page 113: Safety

    Kc705 evaluation board 113 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix f: regulatory compliance and information safety iec 60950-1:2005, information technology equipment – safety, part 1: general requirements en 60950-1:2006, information technology equipment – safety, part 1: general require...

  • Page 114: Xilinx Resources

    Kc705 evaluation board 114 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix g additional resources and legal notices xilinx resources for support resources such as answers, documentation, downloads, and forums, see xilinx support . Solution centers see the xilinx solution centers for support on d...

  • Page 115: References

    Kc705 evaluation board 115 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix g: additional resources and legal notices references the most up to date information related to the kc705 board and its documentation is available on these websites: kintex-7 kc705 fpga kc705 evaluation kit kintex-7 kc705...

  • Page 116: Training Resources

    Kc705 evaluation board 116 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix g: additional resources and legal notices 18. Displaytech: www.Displaytech-us.Com (s162d) 19. Texas instruments: www.Ti.Com , www.Ti.Com/fusiondocs, and www.Ti.Com/ww/en/analog/digital-power/index.Html (ucd9248pfc, ptd08a...

  • Page 117

    Kc705 evaluation board 117 ug810 (v1.8) march 20, 2018 www.Xilinx.Com appendix g: additional resources and legal notices updates to the materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the materials without prior written consent. Certain products...