Cadence ALLEGRO FPGA SYSTEM PLANNER System Planner
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The Cadence
®
Allegro
®
FPGA System Planner addresses the
challenges that engineers encounter when designing one or
more large-pin-count FPGAs on the PCB board—which includes
creating the initial pin assignment, integrating with the sche-
matic, and ensuring that the device is routable on the board.
It delivers a complete, scalable technology for FPGA-PCB
co-design that automates creation of optimum “device-rules-
accurate” pin assignment. By replacing manual, error-prone
processes with automatic pin assignment synthesis, this unique
placement-aware solution eliminates unnecessary physical
design iterations while shortening the time required to create
optimum pin assignment.
Cadence FPGA System Planner
technologies are available in the
following product offerings:
•
Allegro FPGA System Planner L,
XL, and GXL
•
Allegro FPGA System Planner Two
FPGA Option L
•
Cadence OrCAD FPGA System
Planner
AllEGro FPGA
SySTEm PlAnnEr
Figure 1: Color-coded map of the I/Os of a multi-bank FPGA with different types of configurable pins
User IO
Configurable
Clock
Capable
Differential
Power