Cadence ALLEGRO FPGA SYSTEM PLANNER System Planner - page 4
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CADEnCE AllEGro FPGA SySTEm PlAnnEr
PLACeMenT AWAre Pin
ASSiGnMenT SYnTHeSiS
The Allegro FPGA System Planner
provides users a way to create an FPGA
system placement view using Allegro
PCB footprints. Users specify connectivity
between components in the placement
view and the FPGA at a high level using
interfaces such as DDRx, PCI Express, SATA,
Front Side Bus, etc. that connect FPGAs
and other components in the design,
shortening the time to specify design
intent for the FPGA system.
Once the connectivity of the FPGA to
other components in the sub-system is
defined, the Allegro FPGA System Planner
then synthesizes the pin assignment based
on the user’s design intent, available FPGA
resources, component placement around
the FPGA, and the FPGA vendor’s pin
assignment rules.
The Allegro FPGA System Planner has
a built-in DRC engine that incorporates
the rules provided by FPGA vendors for
pin assignment, reference voltages, and
terminations. This rules-based engine
prevents PCB physical prototype iterations
as the FPGAs are always correctly
connected.
Pin assignment algorithms are optimized
to assign interface signals to a group of
pins, thereby minimizing net crossovers
and improving routability on the PCB.
ArCHiTeCTurAL eXPLOrATiOn
enABLeD
During the device selection process,
FPGA designers need a way to evaluate if
the FPGA(s) they choose can meet their
application needs while keeping the cost
of devices as low as possible. Estimating
FPGA resource requirements can be
tricky and requires designers to balance
Look Up Tables (LUTs), high-speed I/O
requirements, and memory with I/Os for
low-speed signals. Sometimes choosing
more than one FPGA may be cheaper
than choosing one large FPGA. While
at other times choosing an FPGA with
a larger pin count will suffice, thereby
saving board space and routing channels.
Manual pin assignment approaches make
performing these cost and performance
trade-offs very time consuming and
tedious. With its placement-aware FPGA
I/O pin assignment synthesis, the Allegro
FPGA System Planner helps designers do
trade-offs quickly, enabling architectural
exploration that is not practical with
manual approaches.
ASiC PrOTOTYPinG uSinG FPGAS
Some companies choose to do ASIC
prototyping using FPGAs on the PCB. In
these cases, the number of FPGAs used
grows rapidly. This sometimes requires
using several PCBs to place all the FPGAs.
With a large number of FPGAs, the time
to do initial pin assignment can be very
long using manual processes. Additionally,
without taking placement of these FPGAs
into account, the pin assignment can make
routing of the PCB a very long process,
extending the time it takes for designers to
get to the ASIC prototype using FPGAs.
The Allegro FPGA System Planner shortens
the time required to create pin assignment
for a large number of FPGAs through
placement-aware pin assignment synthesis
that is driven by a device-accurate FPGA
models library. With the ability to export
port information in Verilog
®
and import
Verilog-based connectivity, the Allegro FPGA
System Planner allows users to iterate with
RTL partitioning software, shortening the
time to define the FPGA-based system and
quickly creating DRC-accurate FPGA pin
assignment.
OrCAD FPGA
System Planner
Allegro FPGA
System Planner L
Allegro FPGA
System Planner
Two FPGA Option
Allegro FPGA
System Planner XL
Allegro FPGA
System Planner
GXL
Concurrent device
optimization
1 FPGA
1 FPGA
2 FPGAs
4 FPGAs
Unlimited FPGAs
Placement-aware
synthesis
Yes
Yes
Yes
Yes
Yes
Reuse symbols
and footprints
Yes
Yes
Yes
Yes
Yes
Symbols &
schematic
generation
OrCAD Capture
Allegro Design Entry
CIS / Allegro Design
Entry HDL
Allegro Design Entry
CIS / Allegro Design
Entry HDL
Allegro Design Entry
CIS / Allegro Design
Entry HDL
Allegro Design Entry
CIS / Allegro Design
Entry HDL
Post-placement
optimization
No
Yes
Yes
Yes
Yes
Schematic power
connections
No
Yes
Yes
Yes
Yes
Schematic
terminations
No
Yes
Yes
Yes
Yes