Cadence ENCOUNTER CONFORMAL ECO DESIGNER Datasheet - page 3
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ENCOUNTER CONFORMAL ECO DESIGNER
Figure 2: The Encounter Conformal ECO Designer implementation flow
Design netlist (G3) is the hand-off
point to the back-end physical
implementation tool targeting a
pre-mask or post-mask flow.
Tool features:
• Supports combinational and
sequential (the addition of new
state elements) changes of
the design
• Supports the addition of new
ports
• Preserves the clock trees
• Preserves the scan chain
• Preservers the original netlist
structure (G1) when it creates the
new ECO netlist (G3)
• Recycles freed-up cells during the
ECO analysis process
SoC Encounter System
New RTL
(R2)
Old RTL
(R1)
Encounter Conformal
ECO Designer
Incremental Optimizations
P&R
New Netlist
(G2)
ECO Netlist
(G3)
Final Netlist
Old Netlist
(G1)
Old DEF
Synthesis
Synthesis
Test Insertion
Place & Route
ECO Designer can write out an ECO script
that can be used to make direct changes
to the place-and-route database.
SPARE GATE MAPPING
FOR POST-MASK ECO
Encounter Conformal ECO Designer (GXL)
has the ability to read the DEF layout
database corresponding to the original
design netlist (G1), spef, captable, LEF,
Liberty synthesis libraries, and SDC to
optimally map ECO logic to standard cell
and gate-array spare gates. The mapping
engine is timing- and spare-cell-location
aware. This capability enables the
designer to get an early estimate of the
ECO feasibility and effectively drive the
back-end implementation flow. Encounter
Conformal ECO Designer (GXL) can also
recycle freed-up cells in the ECO mapping
process. The output is the ECO netlist (G3)
and a spare gate mapping file. This map-
ping file instructs the place-and-route
tool how to map the newly added ECO
logic to specific spare logic resources in
the layout.
INTEGRATED ENVIRONMENT
An intuitive graphical user interface (GUI)
is provided for setup and debugging,
allowing the user to work more produc-
tively and quickly pinpoint the cause of
equivalence mismatches. Included are:
• Graphicaldebuggingviaanintegrated
schematic viewer that shows logic
values for each error vector
• Fullcross-highlightingbetween
RTL model and circuit
• Automaticerrorcandidateidentification
with assigned and weighted
percentages
• Logic-conepruningtofocusdebugging
on relevant information
SMART SETUP AND DIAGNOSIS
Encounter Conformal ECO Designer
includes a set of intelligent ‘analyze’ com-
mands to ease setup and diagnosis.
‘analyze setup’ investigates the current
environment and automatically remedies
common setup issues sometimes experi-
enced by new users. In tandem, ‘analyze
nonequivalent’ can be invoked if non-
equivalences are encountered. The com-
mand then presents a one-line answer as
to what is wrong.
PLATFORMS
• Linux(32-bit,64-bit)
• SunSolaris(32-bit,64-bit)
• IBMAIX(32-bit,64-bit)
LANGUAGE SUPPORT
• Verilog
®
(1995, 2001)
• SystemVerilog
• VHDL(87,93)
• SPICE(traditional,LVS)
• EDIF
• Liberty
• Mixedlanguages