Cadence ENCOUNTER LIBRARY CHARACTERIZER Datasheet - page 2
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ENCOUNTER LIBRARY CHARACTERIZER
realizing their ultimate vision. As a result,
ASIC and CoT designers may hesitate to
implement a particular design strategy
due to the need for custom standard-cell
libraries at specialized process, voltage,
and temperature (PVT) points to suit their
requirements. The cost and turnaround
time needed to obtain these libraries
can limit the aggressiveness of the
power-saving strategy employed. Using
Encounter Library Characterizer, designers
are free to generate any PVT corner
in-house, giving them greater flexibility
while minimizing the cost of obtaining
custom libraries from IP providers
(Figure 1).
BENEFITS
• Unified characterization system delivers
faster, simultaneous model generation
• Offers high-throughput parallel job
execution and management
– Supports parallel simulation job
control
– Supports simultaneous corners and
models
– Up to 13X performance improvement
over previous releases
• Support for advanced modeling formats
– ECSM (Effective Current Source
Model) delay, noise, power, and
statistical modeling
– CCS (Composite Current Source
Model) delay, noise and power
– Liberty NLDM (Non-Linear Delay
Model)
– Liberty NLPM (Non-Linear Power
Model)
• Provides automatic optimal vector
generation
– Supports manual vectors
• Enables state-dependent power charac-
terization
• Includes a library validation suite for
output library validation, SPICE corre-
lation, and comparison
• Delivers exceptional ease-of-use
– Supports simultaneous process
corners
– Supports multiple circuit simulators
– Provides advanced automatic logic
recognition for complex gates
– Offers incremental and detailed
runtime status reporting
• Generates HTML data sheets
• Supports adaptive library re-character-
ization
– Saves runtime for re-generated
libraries
– Uses advanced logic recognition
when function statement not present
FEATURES
Encounter Library Characterizer provides
a comprehensive characterization solution
designed to meet the standard-cell
modeling needs of today’s advanced
digital design flows. Encounter Library
Characterizer is designed to support
advanced low-power, 28nm, multi-
corner design methodologies and can
characterize for:
• State-dependant pin-to-pin delay
• Input timing constraints (setup/hold/
pulse width)
• Power consumption (internal/leakage)
• Input/output pin capacitance
• Input pin threshold voltage
• Output pin transition time
• ECSM and CCS Driver/Receiver models
ADVANCED AUTOMATIC LOGIC
RECOGNITION
The propagation delay between some
input ports and output ports depends on
the status of other input ports. Two types
of logic are state dependent: complex
gates: AOI and OAI, and exclusive logic
such as XOR and XNOR. During the logic
recognition stage, Encounter Library
Characterizer automatically detects state-
dependent logic and generates vectors to
comprehensively exercise the logic.
ADAPTIVE LIBRARY
RE-CHARACTERIZATION
Designers needing an extra corner
as well as library vendors updating IP
libraries will benefit from the ability to
use existing .lib files to save runtime
during the characterization process. The
library re-characterization feature utilizes
information in the timing library—such
as function, arcs, I/P slew, and O/P load
range—to reduce the dependence on
gate recognition by performing automatic
sensitization for simulation vectors.
For incomplete cells, adaptive logic
recognition technology will automatically
use logic recognition to determine the
function while preserving the arcs in the
original seed library. This enables fast,
incremental characterization for different
supply voltages and temperatures, process
changes, format changes, or underlying
subckt changes.
SUPPORT FOR LOW POWER CELLS
Encounter Library Characterizer supports
advanced low-power library model
generation and complex state retention
power gating (SRPG) cells. For SRPG
cells, timing constraints between sleep,
save, and restore pins are automatically
recognized and generated. It characterizes
for:
• Combinational cells with or without a
pull-up/down device
• Sequential cells with or without pull-up/
down device
• Sequential cells with balloon structure
with or without pull-up/down device
• Power shut-off cells
• Level shifters
ACCURATE NLDM
CHARACTERIZATION
The industry-standard Liberty (or .lib)
format utilized Non-Linear Delay Models
(NLDMs) to estimate delay as a function
of gate input slew and the network