Cadence ENCOUNTER LIBRARY CHARACTERIZER Datasheet - page 4
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ENCOUNTER LIBRARY CHARACTERIZER
CCS POWER MODEL
CHARACTERIZATION
The CCS Power model provides additional
information for dynamic and static power
analysis similar to that provided by ECSM
power. Characterization includes:
• DC Current
• Output voltage
• Noise Propagation
• Miller Capacitance
SILICON-ON-INSULATOR SUPPORT
Partially depleted Silicon-On-Insulator
(SOI) process technology requires special
handling during library characterization
so that the floating body history effect
can be properly modeled during timing
analysis. Encounter Library Characterizer
can automatically generate the min-SOI
and max-SOI libraries for each Process
Voltage Temperature (PVT) library corner.
This enables the history effect to be
modeled during Static Timing Analysis
when used in conjunction with the
simultaneous min/max mode.
LIBRARY VALIDATION SUITE
Once libraries are generated for the first
time or new PVTs are re-characterized
from an existing set, it is important to
ensure integrity and accuracy. Doing
so allows problems to be corrected
before they cause hard to correct issues
in the design flow. Encounter Library
Characterizer provides an advanced
set of validation tools to enable library
developers to quickly validate the library
output and identify problems early.
The ecsmChecker utility checks for
syntax and semantics issues which would
normally be flagged by library parsers. In
addition, the ecsmChecker can do gross
checks on library data to ensure they meet
specifications.
The LibDiff utility provides valuable
information on the changes from the
original seed library. In addition, it checks
for syntax and semantic problems with the
input libraries (Figure 2). This information
is all presented in an easy-to-read
graphical interface that shows:
• Minimum, maximum, and average error
(absolute or relative) for timing and
power, including waveforms
• CCS and ECSM waveforms
• Line-by-line library text comparison
The suite also includes validation utilities
which can check the accuracy of the
generated libraries compared to static
timing analysis and SPICE.
ADVANCED SIMULATION AND
ANALYSIS SUPPORT
To ensure the flexibility that is critical
in today’s digital design processes,
Encounter Library Characterizer supports
the Cadence Virtuoso
®
Spectre
®
Circuit
Simulator as well as HSpice and Eldo.
Encounter Library Characterizer also
generates statistical timing and leakage
power formats used for modeling
variation in advanced designs.
STATISTICAL PROCESS VARIATION
MODELING
Process variation—which at 90nm and
above had a manageable impact on
delay—has a much more dramatic effect
as process geometries shrink. Process
control at these smaller geometries is
difficult, resulting in a larger variation
as a percentage of the total size of the
shape. For instance, a 0.01μm variation
at the 1μm process node is only 1% of
the nominal. However, the same 0.01μm
variation at the 65nm process node is
greater than 15% of the nominal.
In traditional static timing analysis
(STA), this variability is accounted
for by introducing more aggressive
gross guardbands and new analysis
corners to model different process and
environmental variation combinations
over multiple analysis runs. The corner-
based approach can be overly pessimistic
since it can report timing scenarios that
have an extremely small likelihood of
occurring. In contrast, statistical static
timing analysis (SSTA) signoff uses
Figure 2: LibDiff library comparison utility