Cadence INCISIVE ENTERPRISE VERIFIER Datasheet - page 5
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INCISIVE ENTERPRISE VERIFIER
• Enables “hot swap” of the software-
based, dynamic simulation in/out of
the Cadence Palladium
®
XP verification
computing platform for additional
performance
Enhanced productivity
• Reduces”time to first test” for
verification novices and experts alike
• Speeds the construction, configuration,
understanding, and usage of
verification IP with the Incisive
Verification Builder component
• Accelerates the setup, debug, and
integration of verification environment
components with 500+ HDL analysis
checks that flag syntactic, semantic,
and functional errors
• Automates generation, assertion
checking, and functional and code
coverage to provide a “total
coverage” view
• Single-kernel architecture provides
native, dynamic assertion support with
PSL, SVA, and OVL, plus the Incisive
Assertion Library, which allows users
to insert common assertions into their
designs quickly
• Reduces the time to discover and
correct logic and transaction modeling
errors via an integrated graphical debug
environment
Comprensive standards support
• Supports all IEEE-standard languages
and interfaces, enabling full legacy and
third-party IP usage
• Supports the Si2 Common Power
Format (CPF), an open specification
language that captures all power-
specific design intent
INCISIVE ENTERPRISE
SIMulaToR Xl FEaTuRE
hIGhlIGhTS
hETERoGENEouS SINGlE-KERNEl
aRChITECTuRE
The Incisive heterogeneous single-kernel
architecture enables unified simulation
through behavioral, transaction, register-
transfer, and gate levels of abstraction. It
uses a unique interleaved native-compiled
architecture that supports all open and
IEEE-standard languages including
Verilog
®
, SystemVerilog, VHDL,
e
,
SystemC
®
, the SystemC Verification (SCV)
Library, CPF, PSL, SVA, OVL, and the
Universal Verification Methodology (UVM)
class library. Design and testbench models
can be interleaved in any language and
any level of abstraction without the
performance and integration overhead
caused by co-simulation.
RaPId CREaTIoN oF lIBRaRIES oF
REuSaBlE TESTS
Incisive Enterprise Verifier fully supports
the testbench reuse component of the
Universal Verification Methodology
(UVM). The UVM describes how to create
reusable verification components in any
IEEE-standard language and provides
guidelines for setting up multi-language
interfaces to existing IP for maximum
operational flexibility. Example UVM
guidelines include recommendations for
structuring classes, virtual interfaces, and
packages for unrestricted portability.
CoNSTRaINT-dRIVEN STIMuluS
GENERaTIoN
Using either the IEEE 1647
e
language
or IEEE 1800 SystemVerilog (or both
together), Incisive Enterprise Simulator
XL supports constraint-driven stimulus
generation, which automates the process
of generating functional verification tests.
By specifying constraints, you can target
the generator quickly and easily to create
any test in your functional test plan.
You can even generate tests on-the-fly
based on the current design state, making
it possible to detect hard-to-reach corner
cases.
When combined with the “sequence”
feature of the UVM, stimuli that exercise
corner-case scenarios at the block level
can be reused at the system level to
verify how the entire chip behaves in that
corner case. All scenarios are written out
into a reusable format, supporting the
creation of portable libraries of protocol
checkers and other structured behaviors
for reuse on future projects, or system-
level verification of the same project.
SPECIFICaTIoNS
PuRE FoRMal aNalySIS dESIGN
laNGuaGE SuPPoRT
• Verilog (IEEE 1364-1995, IEEE 1364-
2001)
• SystemVerilog (IEEE 1800)
• VHDL (IEEE 1076-1987, IEEE 1076-
1993)
• Mixed-language environments
– Finite state machine (FSM) coding
– Verilog, VHDL, and mixed-language
support
PuRE FoRMal RESulTS aNalySIS
• Debug and GUI
– Assertion manager
– Waveform viewer
– Source code browser
– Source code value annotation
– Driver and receiver tracing
– Vacuity and sanity checks
– Assertion triggering
• Reporting
– Status and proof diameter reporting
– Assertion coverage reporting
– Formal coverage reporting
– Cone-of-influence analysis
aSSERTIoN SuPPoRT
• PSL and SVA (the IEEE-standard
assertion languages)
• Open Verification Library (OVL)
•
e
testbench assertions
• Incisive Assertion Library (included)
• Common compile and elaboration
mechanism with the Incisive platform