Cadence INCISIVE ENTERPRISE VERIFIER Datasheet - page 6
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INCISIVE ENTERPRISE VERIFIER
• Common user interface with the
Incisive platform
• Dynamic assertion evaluation
– Natively compiled with HDL for
highest performance
– Can be embedded in the HDL or in
separate file(s)
– Recorded as transactions for direct
display in waveform window
– PSL and SVA assertions treated as
first-class simulation objects for easy
debugging
dyNaMIC SIMulaTIoN
• Single-kernel simulation engine
– Verilog (IEEE 1364-1995 and IEEE
1364-2001 extensions)
– SystemVerilog (IEEE 1800)
–
e
(IEEE 1647)
– VHDL (IEEE 1076-1987, IEEE 1076-
1993, IEEE 1076.4-2000 (VITAL
2000))
– SystemC (IEEE 1666, OSCI
®
SystemC
v2.2)
– PSL (IEEE 1850)
– SVA (IEEE 1800)
– CPF
• Compile
– Native compilation technology goes
directly to host processor machine
code, which maximizes performance
– Intelligent incremental compile
reduces compile times
• Capacity
– Typical 10M gate equivalents in
32-bit OS (4GB addressable)
– Typical 100M gate equivalents in
64-bit OS
• Server farm
– Platform computing LSF
– Sun Microsystems Gridware
SIMulaToN aNd MIXEd FoRMal/
SIMulaTIoN RESulTS aNalySIS
• Debug and GUI
– Waveform window
– Register window
– Unified transaction/signal viewing
– Schematic tracer
– Expression calculator
– Signal flow browser
– Source viewer
– Error browser
– Tcl/Tk scripting for customizable
displays
– Log signal and transaction data to
SST database
• Performance analysis software outlines
areas of code where most simulation
time is spent
• Code coverage
– Supports Verilog, SystemVerilog,
VHDL, and mixed-language designs
– Automatic FSM extraction
– Coverage attributes supported
include blocks, paths, expressions,
variables, gates, FSM (states,
sequences), and toggle
– Coverage reuse
– Rank order coverage contributions
– Bit-wise expression scoring
• Functional coverage analysis
– Supports Verilog, SystemVerilog,
VHDL,
e
, SystemC, SCV, PSL, SVA,
and OVL
– Logs data to SST2 database
– Tcl/Tk scripting for custom analysis
hdl aNalySIS
• 500+ checks to lint and analyze
code for:
– Synthesizability
– Race conditions
– Code reusability
– Clock domain synchronization
– FSM coding
– Acceleration policy checks
• Gate-level netlist analysis for any DFT
errors introduced during synthesis
• Verilog, SystemVerilog, VHDL, and
mixed-language support
• Powerful customization capability using
VPI/VHPI
• Graphical interface to sort, filter, and
analyze messages with source code
e
TESTBENCh aNalySIS
• 200+ checks to lint and analyze code
for:
– Code reusability as per Universal
Reuse Methodology (URM)
compliance rules
– Performance analysis
– Race conditions
– Pre-defined coding style rules
– Generation constraints
• Graphical interface to sort, filter, and
analyze messages with source code
VERIFICaTIoN BuIldER
• GUI support for configuration of
UVM-compliant Universal Verification
Components (UVCs)
• Outputs UVCs in either
e
(IEEE 1647) or
SystemVerilog (IEEE 1800)