Cadence NANOROUTE ADVANCED DIGITAL ROUTER Datasheet - page 2
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www.cadence.com
NANOROUTE ADVANCED DIGITAL ROUTER
grid-based router with off-grid flexibility,
and it concurrently evaluates and
optimizes interconnect topology based
on 3D effects on timing, area, power,
manufacturability, and yield.
Powered by a superthreading backplane
(either multi-thread or distributed
processing), the NanoRoute solution
finishes millions of nets of connectivity
per hour. It delivers the highest quality of
results in a fraction of the time taken by
other routers on the market.
BENEFITS
• Enables the implementation of large,
complex designs on advanced or
mainstream process technologies
- Mitigates process variation by sup-
porting a wide range of advanced
node processes
- Improves overall quality of results,
maximizes utilization, and meets
multiple design objectives
- Shrinks die size by 5-10% with robust
routing technology and congestion
handling results
- Offers higher capacity for larger,
more complex designs
• Enhances productivity through efficient
single-CPU and multi-CPU performance
- Delivers 10x or more performance
gain
- Speeds turnaround time with
dynamic multi-thread and distributed
processing capability
• Ensures a convergent path to design
tapeout and production silicon
- Offers a silicon-proven track record
with successful customer tapeouts
and foundry endorsements
CAPABILITIES
SMART ROUTING
NanoRoute Router’s new generation of
SMART
technology (
SMART2
) holistically
and simultaneously evaluates and
optimizes the interdependent objectives
of signal integrity, manufacturing
awareness, routing, and timing.
SMART2
technology features:
• Full support of process design rules
(both restricted and recommended)
from 130nm to 32/28nm and smaller
• Design for manufacturability (DFM) such
as via and interconnect optimization
• Automated prevention and fixing for
lithography effects
• Shielding support and signal integrity
3D coupling effect reduction
• Large capacity and high utilization
support
• Dynamic multi-CPU support with
superthreading technology
In traditional approaches to routing,
issues of coupling effect, power, area, and
especially DFM are addressed sequentially
and mutually exclusive from one another.
This approach is inadequate for today’s
designs. For example, signal integrity and
power are isolated from process variation
and should not be optimized separately
from manufacturability. Otherwise, a fix
for one requirement will likely introduce
a change for the other and create new
conflicts. The same is true for routability
and manufacturing awareness. The
plethora of new foundry-enforced
manufacturing requirements and yield
enhancement guidelines can significantly
alter the RC characteristics and cross-
coupling dynamics of the design, and
changes to either must be aware of both
timing and signal integrity.
By using the
SMART2
approach to
routing—concurrent optimization with
in-context analysis—design teams can
intelligently manage all design objectives
simultaneously. Key capabilities include
wire-spreading, wire-widening, double-cut
via insertion, single via reduction and
optimization, critical area analysis and
optimization, true lithography distortion
prevention and optimization, CMP-aware
metal fill, and a rich set of random and
systematic visual analysis and text-based
reporting vehicles.
Figure 2: NanoRoute
SMART2
technology targets multiple design objectives simultaneously for total
design closure