IBM BladeCenter HS22 Product Manual - page 6
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6.
The
six-core Xeon processors contain six complete processor cores. The processors also
contain one shared
12MB cache. The shared cache is dynamically allocated among cores as
needed. The six cores appear to software as six physical processors. The six-core processors
offer considerably higher performance than a same-speed Xeon processor with four cores.
Turbo Boost Technology dynamically turns off unused processor cores and increases the
clock speed of the cores in use, by up to two model frequencies. For example, a
2.93GHz 6-
core X5670 processor with 3-6 cores active can run the cores at 3.2GHz. With only one or two
cores active, the same processor can run those cores at
3.33GHz. Similarly, a 3.46GHz 4-core
X5677 processor can run at 3.6GHz or even 3.73GHz. When the cores are needed again, they
are dynamically turned back on and the processor frequency is adjusted accordingly.
In processors implementing
Intel Hyper-Threading Technology, each core has two threads
capable of running an independent process. Thus, a 6-core processor can run
12 threads
concurrently.
Intelligent Power Capability powers individual processor elements on and off as needed, to
reduce power draw.
Execute Disable Bit functionality can help prevent certain classes of malicious buffer overflow
attacks when combined with a supporting operating system.
Intel’s
Virtualization Technology (VT) integrates hardware-level virtualization hooks that allow
operating system vendors to better utilize the hardware for virtualization workloads.
DDR-3 Registered Memory with Chipkill ECC Protection
The HS22 uses registered double data rate III (DDR-3) VLP (very-low-profile) DIMMs and provides Active
Memory features, including advanced
Chipkill memory protection, for up to 16X better error correction
than standard ECC memory. In addition to offering
triple the memory bandwidth of DDR-2 or fully-
buffered memory, DDR-3 memory also uses less energy. DDR-2 memory already offered up to
37%
lower energy use than fully buffered memory. Now, a generation later, DDR-3 memory is even more
efficient, using
10-15% less energy than DDR-2 memory.
The HS22 supports up to
96GB of memory in twelve DIMM slots. Redesign in the architecture of the
5500 and 5600 Series processors bring radical changes in the way memory works in these servers. For
example, the Xeon 5500 and 5600 Series processors
integrate the memory controller inside the
processor, resulting in two memory controllers in a two-socket system. Each memory controller has
three memory channels. Depending on the type of memory, population of memory, and processor model,
the memory may be clocked at
1333MHz, 1066MHz or 800MHz.
Note: If only one processor is installed, only the first six DIMM slots can be used. Adding a second
processor not only doubles the amount of memory available for use, but also doubles the number of
memory controllers, thus doubling the system memory bandwidth. If you add a second processor, but no
additional memory for the second processor, the second processor has to access the memory from the
first processor “remotely,” resulting in longer latencies and lower performance. The latency to access
remote memory is almost 75% higher than local memory access. So, the goal should be to always
populate both processors with memory.
The
L5640 and X56xx processor models support memory running at up to 1333MHz, while E56xx-and-up
models support memory at up to 1066MHz, and the
E550x models support memory at 800MHz only.
Running memory at 1333MHz (where supported) versus 1066MHz offers up to
9% better performance,
while running memory at 1066MHz produces up to
28% better performance thanmemory running at
800MHz.
Xeon 5500 and 5600 Series processors access memory with almost
50% lower latency than the
previous generation 5400 Series processors. That can result in faster processing of latency-sensitive
workloads.
Ch1
Ch0
Xeon 5600 / 5500
Processor 0
Memory Controller
1
2
Ch2
3
4
5
6
Xeon 5600 / 5500
Processor 1
Ch0
7
8
Ch2
9
10
Ch1
11
12
QPI
Memory Controller