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Xilinx KCU105 User Manual

Other manuals for KCU105: User Manual, User Manual

Summary of KCU105

  • Page 1

    Kcu105 board user guide ug917 (v1.4) september 25, 2015.

  • Page 2: Revision History

    Kcu105 board user guide www.Xilinx.Com 2 ug917 (v1.4) september 25, 2015 revision history the following table shows the revision history for this document. Date version revision 09/25/2015 1.4 updated fmc hpc connector j22 . Revised figure 1-23 . Updated the binary format for i2c eeprom in table 1-1...

  • Page 3

    Kcu105 board user guide www.Xilinx.Com 3 ug917 (v1.4) september 25, 2015 table of contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 chapter 1: kcu105 evaluation board features overview ....

  • Page 4

    Kcu105 board user guide www.Xilinx.Com 4 ug917 (v1.4) september 25, 2015 appendix c: system controller overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 power-on and reset . . . . . . . . . . . . ...

  • Page 5

    Kcu105 board user guide www.Xilinx.Com 5 ug917 (v1.4) september 25, 2015 appendix h: additional resources and legal notices xilinx resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 solution centers. . . . ....

  • Page 6: Overview

    Kcu105 board user guide www.Xilinx.Com 6 ug917 (v1.4) september 25, 2015 chapter 1 kcu105 evaluation board features overview the kcu105 evaluation board for the xilinx ® kintex ® ultrascale ™ fpga provides a hardware environment for developing and evaluating designs targeting the ultrascale xcku040-...

  • Page 7

    Kcu105 board user guide www.Xilinx.Com 7 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features ° fmc lpc connector (one gth transceiver) ° 8-lane pci express (eight gth transceivers) ° two sfp+ connectors (two gth transceivers) ° tx and rx pair sma connectors (one gth transceiv...

  • Page 8: Board Diagram

    Kcu105 board user guide www.Xilinx.Com 8 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features board diagram the kcu105 board diagram is shown in figure 1-1 x-ref target - figure 1-1 figure 1-1: kcu105 evaluation board block diagram -7$*0rgxoh dqg -7$*+hdghu 3djh 'xdo4xdg63, )o...

  • Page 9: Feature Descriptions

    Kcu105 board user guide www.Xilinx.Com 9 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features feature descriptions figure 1-2 shows the kcu105 board. Each numbered feature that is referenced in figure 1-2 is described in table 1-1 with a link to detailed information provided u...

  • Page 10

    Kcu105 board user guide www.Xilinx.Com 10 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features table 1-1: kcu105 board component descriptions callout component description notes schematic (1) 0381556 page number 1 kintex ultrascale xcku040-2ffva1156e device xcku040-2ffva1156e ...

  • Page 11

    Kcu105 board user guide www.Xilinx.Com 11 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features 19 dual usb-to-uart bridge , bridge device (u34) with mini-b connector (j4) silicon labs cp2105-f01-gm bridge, hirose zx62d-ab-5p8 connector 40 20 hdmi video output , hdmi controller...

  • Page 12

    Kcu105 board user guide www.Xilinx.Com 12 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features kintex ultrascale xcku040-2ffva1156e device [ figure 1-2 , callout 1] the kcu105 board is populated with the kintex ultrascale xcku040-2ffva1156e device. For more information on kint...

  • Page 13

    Kcu105 board user guide www.Xilinx.Com 13 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features fpga configuration the ultrascale fpga is configured using either the master spi or jtag mode as determined by the configuration dip switch sw15. Interfaces supporting these configur...

  • Page 14

    Kcu105 board user guide www.Xilinx.Com 14 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features prior to kcu105 board power-up, the ultrascale fpga u1 configuration method is selected with dip switch sw15 switch settings: • master spi mode ° with both sw15.6 (fpga_m2) and sw15....

  • Page 15

    Kcu105 board user guide www.Xilinx.Com 15 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features encryption key battery backup circuit the xcku040 device u1 implements bitstream encryption key technology. The kcu105 board provides the encryption key backup battery circuit shown ...

  • Page 16

    Kcu105 board user guide www.Xilinx.Com 16 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features i/o voltage rails there are ten i/o banks available on the kcu040 device and the kcu105 board. The voltages applied to the fpga i/o banks (shown in figure 1-5 ) used by the kcu105 bo...

  • Page 17: Ddr4 Component Memory

    Kcu105 board user guide www.Xilinx.Com 17 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features ddr4 component memory [ figure 1-2 , callout 2] the 2 gb ddr4 component memory system is comprised of four 256 mb x 16 ddr4 sdram devices (micron edy4016aabg-dr-f-d) located at u60-u...

  • Page 18

    Kcu105 board user guide www.Xilinx.Com 18 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features af23 ddr4_dq11 pod12_dci c7 dqu3 u60 ah23 ddr4_dq12 pod12_dci c2 dqu4 u60 af24 ddr4_dq13 pod12_dci c8 dqu5 u60 ah22 ddr4_dq14 pod12_dci d3 dqu6 u60 ag25 ddr4_dq15 pod12_dci d7 dqu7 u...

  • Page 19

    Kcu105 board user guide www.Xilinx.Com 19 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features ak26 ddr4_dq33 pod12_dci f7 dql1 u62 ak28 ddr4_dq34 pod12_dci h3 dql2 u62 am27 ddr4_dq35 pod12_dci h7 dql3 u62 aj28 ddr4_dq36 pod12_dci h2 dql4 u62 ah27 ddr4_dq37 pod12_dci h8 dql5 u...

  • Page 20

    Kcu105 board user guide www.Xilinx.Com 20 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features an31 ddr4_dq61 pod12_dci c8 dqu5 u63 al34 ddr4_dq62 pod12_dci d3 dqu6 u63 an32 ddr4_dq63 pod12_dci d7 dqu7 u63 ah33 ddr4_dqs6_t diff_pod12_dci g3 dqsl_t u63 aj33 ddr4_dqs6_c diff_pod...

  • Page 21: Dual Quad-Spi Flash Memory

    Kcu105 board user guide www.Xilinx.Com 21 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features the kcu105 board ddr4 memory component interface adheres to the constraints guidelines documented in the ddr4 design guidelines section of ultrascale architecture pcb design user gui...

  • Page 22

    Kcu105 board user guide www.Xilinx.Com 22 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features the connections between the spi flash memories and the xcku040 device are listed in table 1-5 . Figure 1-6 shows the connections of the linear quad-spi flash memory on the kcu105 eva...

  • Page 23

    Kcu105 board user guide www.Xilinx.Com 23 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features x-ref target - figure 1-6 figure 1-6: dual quad-spi 256 mb flash memory 8 & '4 '4 '4b933b:3b% '4b+2/'b% 1& 1& 1& 1& 1& 1& 1& 1& 6b% 9&& 966 62b3; 14 )3*$b&&/. 463,b,2 1& 1& 1& 1& 1& ...

  • Page 24: Micro-Sd Card Interface

    Kcu105 board user guide www.Xilinx.Com 24 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features micro-sd card interface [ figure 1-2 , callout 4] the kcu105 board includes a secure digital input/output (sdio) interface to provide access to general purpose nonvolatile micro-sd m...

  • Page 25

    Kcu105 board user guide www.Xilinx.Com 25 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features figure 1-7 shows the connections of the sd card interface on the kcu105 board. For more details about the multiplexer devices, see the fairchild fssd07 data sheet at the fairchild se...

  • Page 26: Usb Jtag Interface

    Kcu105 board user guide www.Xilinx.Com 26 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features usb jtag interface [ figure 1-2 , callout 5] jtag configuration is provided through a digilent onboard usb-to-jtag configuration logic module (u115) where a host computer accesses th...

  • Page 27: Fmc Connector Jtag Bypass

    Kcu105 board user guide www.Xilinx.Com 27 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features important: the digilent usb module, xilinx platform usb cable interface header (j3), and the system controller (u111) bank 34 jtag interface cannot be operated simultaneously. Make s...

  • Page 28

    Kcu105 board user guide www.Xilinx.Com 28 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features x-ref target - figure 1-9 figure 1-9: kcu105 board clocking block diagram 94xdg&orfn *hqhudwru &/.31 &/.31 &/.3 &/.3 ;$ 6,$8 %$1. $.3$.1 ;&.88 %$1. *3)1 %$1. . %$1. * %$1. 0301 ;&.88...

  • Page 29

    Kcu105 board user guide www.Xilinx.Com 29 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features table 1-7 lists the source devices for each clock. Table 1-7: kcu105 board clock sources clock name clock ref. Des. Description system clock 300 mhz u122 • silicon labs si5335a 1.8v ...

  • Page 30

    Kcu105 board user guide www.Xilinx.Com 30 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features table 1-8 lists the kcu105 board clock sources to the xcku040 device u1 connections. Table 1-8: kcu105 board clock sources to xcku040 device u1 connections clock source ref. Des. And...

  • Page 31

    Kcu105 board user guide www.Xilinx.Com 31 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features system clock source [ figure 1-2 , callout 6] the system clock source is a silicon labs si5335a quad clock generator/buffer at u122. The system clock (sysclk) is a lvds 300 mhz clock...

  • Page 32

    Kcu105 board user guide www.Xilinx.Com 32 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features programmable user clock source [ figure 1-2 , callout 7] the kcu105 evaluation board has a si570 programmable low-jitter 3.3v lvds differential oscillator (u32) connected to the clk0...

  • Page 33

    Kcu105 board user guide www.Xilinx.Com 33 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features jitter attenuated clock [ figure 1-2 , callout 8] the kcu105 board includes a silicon labs si5328b jitter attenuator u57 (8 khz - 808 mhz) on the back side of the board. The gth tran...

  • Page 34

    Kcu105 board user guide www.Xilinx.Com 34 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features an active low input at u57 pin 1 rst_b performs an external hardware reset of this device. This resets all internal logic to a known state and forces the device registers to their de...

  • Page 35

    Kcu105 board user guide www.Xilinx.Com 35 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features gth sma clock input [ figure 1-2 , callout 10] the kcu105 board includes a pair of sma connectors for a gth clock wired to gth quad bank 226. This differential clock has signal names...

  • Page 36

    Kcu105 board user guide www.Xilinx.Com 36 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features gth tx and rx sma differential pairs [ figure 1-2 , callout 12] the kcu105 board includes two pairs (tx and rx) of sma connectors wired to gth quad bank 226. These differential sma p...

  • Page 37: Gth Transceivers

    Kcu105 board user guide www.Xilinx.Com 37 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features gth transceivers [ figure 1-2 , callout 13] the kcu105 board provides access to 20 gth transceivers: • eight of the gth transceivers are wired to the pci express x8 edge connector (p...

  • Page 38

    Kcu105 board user guide www.Xilinx.Com 38 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features quad 227: • mgtrefclk0 - mgt_si570_clock_c_p/n clock • mgtrefclk1 - si5328_out_c_p/n jitter attenuator clock • contains four gth transceivers allocated to fmc_hpc_dp[7:4]_c2m_p/n qua...

  • Page 39

    Kcu105 board user guide www.Xilinx.Com 39 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features gth bank 225 ah6 mgthtxp0_225 pcie_tx3_p a29 perp3 pcie edge connector p1 ah5 mgthtxn0_225 pcie_tx3_n a30 pern3 ah2 mgthrxp0_225 pcie_rx3_p b27 petp3 ah1 mgthrxn0_225 pcie_rx3_n b28 ...

  • Page 40

    Kcu105 board user guide www.Xilinx.Com 40 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features table 1-10 lists the gth bank 226 interface connections between fpga u1, fmc lpc connector j2, sfp0 connector p5, sfp1 connector p4 and mgt tx sma connectors j29/j28, mgt rx sma conn...

  • Page 41

    Kcu105 board user guide www.Xilinx.Com 41 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features table 1-11 lists the gth banks 227 and 228 interface connections between fpga u1 and the fmc hpc j22 connector. Table 1-11: kcu105 board fpga u1 gth bank 227 and 228 connections tran...

  • Page 42

    Kcu105 board user guide www.Xilinx.Com 42 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features for additional information on gth transceivers, see ultrascale architecture gth transceivers user guide (ug576) [ref 6] and ultrascale fpgas transceivers wizard product guide for viv...

  • Page 43

    Kcu105 board user guide www.Xilinx.Com 43 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features pci express endpoint connectivity [ figure 1-2 , callout 14] the 8-lane pci express edge connector p1 performs data transfers at the rate of 2.5 gt/s for gen1 applications, 5.0 gt/s ...

  • Page 44

    Kcu105 board user guide www.Xilinx.Com 44 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features table 1-12 details the pcie p1 edge connector wiring to fpga u1. Table 1-12: kcu105 board fpga u1 to pcie edge p1 connections fpga (u1) pin schematic net name pcie edge p1 pin number...

  • Page 45: Sfp/sfp+ Module Connectors

    Kcu105 board user guide www.Xilinx.Com 45 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features sfp/sfp+ module connectors [ figure 1-2 , callout 15] the kcu105 board hosts two small form-factor pluggable (sfp/sfp+) p4 and p5 that accept sfp or sfp+ modules. The connectors are ...

  • Page 46

    Kcu105 board user guide www.Xilinx.Com 46 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features table 1-13 lists the sfp+ module connections to fpga u1. Table 1-13: kcu105 board fpga u1 to sfp0 and sfp1 module connections fpga (u1) pin schematic net name fpga (u1) direction pin...

  • Page 47

    Kcu105 board user guide www.Xilinx.Com 47 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features for additional information about the enhanced small form factor pluggable (sfp+) module, see the sff-8431 specification [ref 30] . 10/100/1000 mb/s tri-speed ethernet phy [ figure 1-...

  • Page 48

    Kcu105 board user guide www.Xilinx.Com 48 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features on power-up, or on reset, the phy is configured to operate in sgmii mode with phy address 0b00111 using the settings shown in table 1-15 . These settings can be over written via soft...

  • Page 49: Ethernet Phy Status Leds

    Kcu105 board user guide www.Xilinx.Com 49 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features ethernet phy status leds [ figure 1-2 , callout 17] the ethernet phy status leds are integrated into the metal frame of the p3 rj-45 connector. These leds are visible on the left edg...

  • Page 50: Dual Usb-to-Uart Bridge

    Kcu105 board user guide www.Xilinx.Com 50 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features dual usb-to-uart bridge [ figure 1-2 , callout 19] the kcu105 evaluation board contains a silicon labs cp2105gm dual usb-to-uart bridge device (u34) which allows a connection to a ho...

  • Page 51

    Kcu105 board user guide www.Xilinx.Com 51 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features x-ref target - figure 1-21 figure 1-21: kcu105 board dual uart cp2105gm u34 8*bb send feedback.

  • Page 52: Hdmi Video Output

    Kcu105 board user guide www.Xilinx.Com 52 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features table 1-17 lists the cp2105gm connections to fpga u1. For more technical information on the cp2105gm and the vcp drivers, see the silicon labs website [ref 28] . Xilinx uart ip is ex...

  • Page 53

    Kcu105 board user guide www.Xilinx.Com 53 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features the hdmi u52 circuit is shown in figure 1-22 . X-ref target - figure 1-22 figure 1-22: hdmi codec circuit $'9 ,17 3' 6&/ 6'$ 96 +6 &/. +3' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '...

  • Page 54

    Kcu105 board user guide www.Xilinx.Com 54 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features table 1-18 lists the hdmi codec u52 to the xcku040 device u1 connections. All hdmi nets in this table are series resistor coupled. For more information about the analog devices adv75...

  • Page 55

    Kcu105 board user guide www.Xilinx.Com 55 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features i2c bus, topology, and switches [ figure 1-2 , callouts 21, 22] the kcu105 evaluation board implements a 2-to-1 i2c bus arrangement. A single i2c bus from the fpga u1 xcku040 (iic_ma...

  • Page 56

    Kcu105 board user guide www.Xilinx.Com 56 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features important: the tca9548 u28 reset_b pin 3 is connected to fpga u1 bank 64 pin ap10 via level-shifter u44. The pca9544 does not have a reset pin. Fpga pin ap10 lvcmos18 net iic_mux_res...

  • Page 57: Status and User Leds

    Kcu105 board user guide www.Xilinx.Com 57 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features status and user leds table 1-20 defines kcu105 board status and user leds. Table 1-20: kcu105 board status and user leds reference designator description ds2 init ds3 or'd power good...

  • Page 58: User I/o

    Kcu105 board user guide www.Xilinx.Com 58 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features user i/o [ figure 1-2 , callouts 23-26, 40] the kcu105 board provides these user and general purpose i/o capabilities: • eight user leds (callout 23) ° gpio_led[7-0]: ds31, ds32, ds3...

  • Page 59

    Kcu105 board user guide www.Xilinx.Com 59 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features user gpio leds [ figure 1-2 , callout 23] figure 1-24 shows the gpio led circuit. X-ref target - figure 1-24 figure 1-24: user leds *1' /('*51607 '6 '6 /('*51607 /('*51607 '6 '6 /('*...

  • Page 60

    Kcu105 board user guide www.Xilinx.Com 60 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features user pushbuttons [ figure 1-2 , callout 24] figure 1-25 shows the user pushbuttons circuit. X-ref target - figure 1-25 figure 1-25: user pushbuttons *3,26:: 6: 5 *1' 9&&9b$ 5 *3,26:&...

  • Page 61

    Kcu105 board user guide www.Xilinx.Com 61 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features cpu reset pushbutton [ figure 1-2 , callout 25] figure 1-26 shows the cpu reset pushbutton circuit. Gpio dip switch [ figure 1-2 , callout 26] figure 1-27 shows the gpio dip switch c...

  • Page 62

    Kcu105 board user guide www.Xilinx.Com 62 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features rotary switch [ figure 1-2 , callout 40] figure 1-28 shows the rotary switch sw13. X-ref target - figure 1-28 figure 1-28: rotary switch sw13 % 6:% 6: 6:$ &20 $ *1' *1' (gjh'ulyh -rj...

  • Page 63

    Kcu105 board user guide www.Xilinx.Com 63 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features user sma gpio [ figure 1-2 , callout 11] figure 1-29 shows the gpio smas j36 and j37. Table 1-21 lists the gpio connections to fpga u1. X-ref target - figure 1-29 figure 1-29: gpio s...

  • Page 64

    Kcu105 board user guide www.Xilinx.Com 64 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features 4-pole dip sw (active high) (1) an16 gpio_dip_sw0 input lvcmos12 sw12.4 an19 gpio_dip_sw1 input lvcmos12 sw12.3 ap18 gpio_dip_sw2 input lvcmos12 sw12.2 an14 gpio_dip_sw3 input lvcmos...

  • Page 65

    Kcu105 board user guide www.Xilinx.Com 65 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features user pmod gpio headers [ figure 1-2 , callout 34] the kcu105 evaluation board supports two pmod gpio headers j52 (right-angle female) and j53 (vertical male). The pmod nets connected...

  • Page 66: Switches

    Kcu105 board user guide www.Xilinx.Com 66 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features table 1-22 shows the level-shifter u40 and u41 connections to fpga u1. For more information about pmod connector compatible pmod modules, see [ref 27] . Switches [ figure 1-2 , callo...

  • Page 67

    Kcu105 board user guide www.Xilinx.Com 67 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features power on/off slide switch sw1 [ figure 1-2 , callout 30] the kcu105 board power switch is sw1. Sliding the switch actuator from the off to on position applies 12vdc power from the 6-...

  • Page 68

    Kcu105 board user guide www.Xilinx.Com 68 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features program_b pushbutton switch [ figure 1-2 , callout 27] switch sw4 grounds the xcku040 device u1 program_b pin when pressed. This action clears the fpga programmable logic configurati...

  • Page 69

    Kcu105 board user guide www.Xilinx.Com 69 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features fmc hpc connector j22 [ figure 1-2 , callout 33] the 400-pin hpc connector defined by the fmc specification (figure b-2) provides connectivity for up to: • 160 single-ended or 80 dif...

  • Page 70

    Kcu105 board user guide www.Xilinx.Com 70 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features table 1-23 shows the fmc hpc j22 to the xcku040 device u1 connections in fmc connector section pairs. Table 1-23: fmc hpc j22 connections to xcku040 device u1 j22 pin schematic net n...

  • Page 71

    Kcu105 board user guide www.Xilinx.Com 71 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features c22 fmc_hpc_la18 lvds e22 d18 fmc_hpc_la_13_n lvds c9 c23 fmc_hpc_la18 lvds e23 d20 fmc_hpc_la17_cc_p lvds d24 c26 fmc_hpc_la27 lvds h21 d21 fmc_hpc_la17_cc_n lvds c24 c27 fmc_hpc_la...

  • Page 72

    Kcu105 board user guide www.Xilinx.Com 72 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features e25 nc f25 nc e27 nc f26 nc e28 nc f28 nc e30 nc f29 nc e31 nc f31 nc e33 nc f32 nc e34 nc f34 nc e36 nc f35 nc e37 nc f37 nc e39 vadj_1v8 f38 nc f40 vadj_1v8 g/h connections to fpga...

  • Page 73

    Kcu105 board user guide www.Xilinx.Com 73 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features g36 fmc_hpc_la33_p lvds a27 h34 fmc_hpc_la30_p lvds c26 g37 fmc_hpc_la33_n lvds a28 h35 fmc_hpc_la030_n lvds b26 g39 vadj_1v8 h37 fmc_hpc_la32_p lvds e26 h38 fmc_hpc_la32_n lvds d26 ...

  • Page 74

    Kcu105 board user guide www.Xilinx.Com 74 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features fmc lpc connector j2 [ figure 1-2 , callout 34] the 160-pin lpc connector defined by the fmc specification ( figure b-1, page 91 ) provides connectivity for up to: • 68 single-ended ...

  • Page 75

    Kcu105 board user guide www.Xilinx.Com 75 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features table 1-24 shows the fmc lpc j2 to the xcku040 device u1 connections in fmc connector section pairs. Table 1-24: fmc lpc j2 connections to xcku040 device u1 j2 pin schematic net name...

  • Page 76

    Kcu105 board user guide www.Xilinx.Com 76 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features g6 fmc_lpc_la00_cc_p lvcoms18 w23 h4 fmc_lpc_clk0_m2c_p lvds aa24 g7 fmc_lpc_la00_cc_n lvds w24 h5 fmc_lpc_clk0_m2c_n lvds aa25 g9 fpc_lpc_la03_p lvds w28 h7 fmc_lpc_la02_p lvds aa22...

  • Page 77: Kcu105 Board Power System

    Kcu105 board user guide www.Xilinx.Com 77 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features kcu105 board power system the kcu105 board hosts a maxim pmbus based power system. Each individual maxim max15301 or max15303 voltage regulator has a pmbus interface. Figure 1-34 sho...

  • Page 78

    Kcu105 board user guide www.Xilinx.Com 78 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features the kcu105 evaluation board uses power regulators and pmbus compliant pol controllers from maxim integrated circuits to supply the core and auxiliary voltages listed in table 1-25 . ...

  • Page 79: Fmc Vadj_1V8 Power Rail

    Kcu105 board user guide www.Xilinx.Com 79 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features the maxim gui regulator on/off settings are shown in table 1-26 . Documentation describing pmbus programming for the maxim intune™ power controllers is available at the maxim integra...

  • Page 80

    Kcu105 board user guide www.Xilinx.Com 80 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features the system controller user interface (see fmc menu options in appendix c ) allows the fmc ipmi routine to be overridden and an explicit value can be set for the vadj_1v8_fpga rail. M...

  • Page 81

    Kcu105 board user guide www.Xilinx.Com 81 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features figure 1-35 shows the sysmon external multiplexer u75 circuit block diagram. X-ref target - figure 1-35 figure 1-35: sysmon external multiplexer block diagram ;&.8 )3*$ %dqn 8 $27 $5...

  • Page 82

    Kcu105 board user guide www.Xilinx.Com 82 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features table 1-27 lists the kcu105 board sysmon power system voltage and current measurement details for the external u75 mux . Table 1-27: sysmon measurements through mux u75 controlled ra...

  • Page 83

    Kcu105 board user guide www.Xilinx.Com 83 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features sysmon header j75 [ figure 1-2 , callout 35] ultrascale fpgas provide an analog converter (sysmon) block. The sysmon contains a single 10-bit 0.2 msps adc. Consequently, the sequence...

  • Page 84

    Kcu105 board user guide www.Xilinx.Com 84 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features x-ref target - figure 1-36 figure 1-36: kcu105 board sysmon and sysmon header j75 voltage source options )3*$ 8 9&&$'& *1'$'& 95()3 95()1 93 91 ';3 ';1 വ വ s) 7r +hdghu - $'3 yp$pd[ ...

  • Page 85

    Kcu105 board user guide www.Xilinx.Com 85 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features the kcu105 board supports both the internal fpga sensor measurements and the external measurement capabilities of the sysmon. Internal measurements of the die temperature, vccint, vc...

  • Page 86: Cooling Fan

    Kcu105 board user guide www.Xilinx.Com 86 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features cooling fan the xcku040 device u1 cooling fan connector is shown in figure 1-38 .The fan turns on when the kcu105 board is powered up due to pull-up resistor r422. The sm_fan_pwm and...

  • Page 87

    Kcu105 board user guide www.Xilinx.Com 87 ug917 (v1.4) september 25, 2015 chapter 1: kcu105 evaluation board features the system controller is delivered as a black-box design that communicates with onboard programmable devices over an i2c interface. The zynq-7000 ap soc system controller ip is not p...

  • Page 88: Switches

    Kcu105 board user guide www.Xilinx.Com 88 ug917 (v1.4) september 25, 2015 appendix a default switch and jumper settings the default switch and jumper settings for the kcu105 evaluation board are provided in this appendix. Switches the default switch settings are listed in table a-1 . Table a-1: defa...

  • Page 89: Jumpers

    Kcu105 board user guide www.Xilinx.Com 89 ug917 (v1.4) september 25, 2015 appendix a: default switch and jumper settings jumpers the default jumper settings are listed in table a-2 . The kcu105 board jumper header locations are shown in figure a-1 . Table a-2: default jumper settings jumper function...

  • Page 90

    Kcu105 board user guide www.Xilinx.Com 90 ug917 (v1.4) september 25, 2015 appendix a: default switch and jumper settings x-ref target - figure a-1 figure a-1: kcu105 board header jumper locations 3rzhu /1. 7; 3&,h 8 8 5rxqgfdoorxwuhihuhqfhvdfrpsrqhqw rqwkhiurqwvlghriwkherdug 6txduhfdoorxwuhihuhqfhvd...

  • Page 91: Overview

    Kcu105 board user guide www.Xilinx.Com 91 ug917 (v1.4) september 25, 2015 appendix b vita 57.1 fmc connector pinouts overview figure b-1 shows the pinout of the fpga mezzanine card (fmc) low pin count (lpc) connector defined by the vita 57.1 fmc specification. For a description of how the kcu105 eva...

  • Page 92

    Kcu105 board user guide www.Xilinx.Com 92 ug917 (v1.4) september 25, 2015 appendix b: vita 57.1 fmc connector pinouts figure b-2 shows the pinout of the fmc high pin count (hpc) connector defined by the vita 57.1 fmc specification. For a description of how the kcu105 evaluation board implements the ...

  • Page 93: Overview

    Kcu105 board user guide www.Xilinx.Com 93 ug917 (v1.4) september 25, 2015 appendix c system controller overview the xilinx system controller is an ease-of-use application that runs on a zynq-7000 ap soc at power-up on all ultrascale fpga evaluation boards. These select board features can be controll...

  • Page 94

    Kcu105 board user guide www.Xilinx.Com 94 ug917 (v1.4) september 25, 2015 appendix c: system controller access the system controller menu as follows: 1. Install the silicon labs cp2105gm dual usb-to-uart bridge driver by following the instructions in the silicon labs cp210x usb-to-uart installation ...

  • Page 95

    Kcu105 board user guide www.Xilinx.Com 95 ug917 (v1.4) september 25, 2015 appendix c: system controller the menu system is shown in figure c-2 . X-ref target - figure c-2 figure c-2: system controller menu system 8*bd&bb &/2&. 6hw 6l)uhtxhqf\ 6hw 6l)uhtxhqf\ 6 0$,1 )0& *3,2 30%xv 6$9( 5(6725( 6dyh 6...

  • Page 96: Power-On And Reset

    Kcu105 board user guide www.Xilinx.Com 96 ug917 (v1.4) september 25, 2015 appendix c: system controller power-on and reset prior to displaying the main menu, the system controller initializes the adjustable voltage (vadj) on the fpga fmc expansion port interface within the available choices of 1.8v,...

  • Page 97

    Kcu105 board user guide www.Xilinx.Com 97 ug917 (v1.4) september 25, 2015 appendix c: system controller a kcu105 board power cycle (power off/power on) returns the clock sources to the factory default settings. On the ultrascale fpga evaluation boards, the factory default for the si570 is 156.250 mh...

  • Page 98

    Kcu105 board user guide www.Xilinx.Com 98 ug917 (v1.4) september 25, 2015 appendix c: system controller option 2: set kcu105 si5328 mgt clock frequency enter the si5328 frequency (0.008-808mhz): 200 important: several seconds might elapse before the result is returned. Freq:200.0000000000 fosc=5600....

  • Page 99

    Kcu105 board user guide www.Xilinx.Com 99 ug917 (v1.4) september 25, 2015 appendix c: system controller • restore kcu105 si570 frequency from eeprom freq:200.0000000000 hs_div=7 n1=4 dco=5600.0 rfreq=0x030fff204b restored si570 frequency = 200.000 from eeprom (the returned values include configurati...

  • Page 100

    Kcu105 board user guide www.Xilinx.Com 100 ug917 (v1.4) september 25, 2015 appendix c: system controller • enable kcu105 si570 automatic restore at power-up reset there is no menu response to selecting this option. To verify that the enabling function occurred, select option 1 again. • enable kcu105...

  • Page 101: Pmbus Menu

    Kcu105 board user guide www.Xilinx.Com 101 ug917 (v1.4) september 25, 2015 appendix c: system controller pmbus menu the pmbus is an i2c bus that is used to read the voltage settings of the nine kcu105 power rails controlled by the maxim power system. Through the pmbus menu these power rails can be r...

  • Page 102

    Kcu105 board user guide www.Xilinx.Com 102 ug917 (v1.4) september 25, 2015 appendix c: system controller vccbram = 0.950 v vcc1v8 = 1.800 v vadj1v8 = 1.800 v vcc1v2 = 1.200 v mgtavcc = 1.000 v mgtavtt = 1.200 v util3v3 = 3.297 v option 2: continuous scan pmbus voltages the list of voltages shown in ...

  • Page 103: Sysmon Menu

    Kcu105 board user guide www.Xilinx.Com 103 ug917 (v1.4) september 25, 2015 appendix c: system controller option 8: get vcc1v2 voltage vcc1v2 = 1.200 v unscaled hex: msb = 0x13, lsb = 0x33 (the returned values include configuration setting details.) option 9: get mgtavcc voltage mgtavcc = 1.000 v uns...

  • Page 104: Sysmon Menu Options

    Kcu105 board user guide www.Xilinx.Com 104 ug917 (v1.4) september 25, 2015 appendix c: system controller the system controller reads and displays sysmon based measurements prior to configuring the ultrascale fpga. Bank 66 of the kintex ultrascale device is the default sysmon bank and is ready to mon...

  • Page 105

    Kcu105 board user guide www.Xilinx.Com 105 ug917 (v1.4) september 25, 2015 appendix c: system controller option 1: get temperature temperature = 33.31 c min = 30.65 c max = 33.54 c option 2: get internal channel voltages vccint = 0.955 v max = 0.956 v min = 0.946 v vccbram = 0.954 v max = 0.954 v mi...

  • Page 106: Fmc Menu

    Kcu105 board user guide www.Xilinx.Com 106 ug917 (v1.4) september 25, 2015 appendix c: system controller vcc1v2: 0.07 w 1.20 v 0.06 a 0.05 a 0.06 a mgtavcc: 0.08 w 1.00 v 0.08 a 0.07 a 0.09 a mgtavtt: 0.03 w 1.20 v 0.03 a 0.02 a 0.03 a option 0: return to main menu this option returns to the menu le...

  • Page 107: Fmc Menu Options

    Kcu105 board user guide www.Xilinx.Com 107 ug917 (v1.4) september 25, 2015 appendix c: system controller these mezzanine cards can be attached to the j22 hpc or j2 lpc expansion ports on the kcu105 board. Table c-3 shows the accessible clock resources on each fmc module. Fmc menu options kcu105 syst...

  • Page 108

    Kcu105 board user guide www.Xilinx.Com 108 ug917 (v1.4) september 25, 2015 appendix c: system controller option 1: set fmc xmxxx clocks kcu105 system controller - fmc clock menu - ----------------------------- 1. Set fmc xm101 clocks 2. Set fmc xm104 clocks 3. Set fmc xm105 clocks 4. Set fmc xm107 c...

  • Page 109

    Kcu105 board user guide www.Xilinx.Com 109 ug917 (v1.4) september 25, 2015 appendix c: system controller • set hpc si570_1 frequency fmc hpc card present (the returned values include configuration setting details.) board_area_offset = 008 board_area_format_version = 0x01 board_area_length = 056 boar...

  • Page 110

    Kcu105 board user guide www.Xilinx.Com 110 ug917 (v1.4) september 25, 2015 appendix c: system controller board_mfg_length = 010 readbuffer index = 026 readbuffer[i] = 58 readbuffer[i+1] = 4d readbuffer[i+2] = 31 readbuffer[i+3] = 30 readbuffer[i+4] = 34 enter the si570 frequency (10-810mhz): 125 fre...

  • Page 111

    Kcu105 board user guide www.Xilinx.Com 111 ug917 (v1.4) september 25, 2015 appendix c: system controller set fmc xm105 clocks kcu105 system controller - xm105 menu - ----------------------------- 1. Set hpc si570 frequency 2. Set lpc si570 frequency 0. Return to fmc clock menu select an option • set...

  • Page 112

    Kcu105 board user guide www.Xilinx.Com 112 ug917 (v1.4) september 25, 2015 appendix c: system controller set fmc xm107 clocks kcu105 system controller - xm107 menu - ----------------------------- 1. Set hpc si570 frequency 2. Set lpc si570 frequency 0. Return to fmc clock menu select an option • set...

  • Page 113

    Kcu105 board user guide www.Xilinx.Com 113 ug917 (v1.4) september 25, 2015 appendix c: system controller common header board area info multirecord area - oem fmc record - dc load records (three groups) - dc output records (three groups) if the fmc iic eeprom has not been programmed, readbuffer[000] ...

  • Page 114: Gpio Menu

    Kcu105 board user guide www.Xilinx.Com 114 ug917 (v1.4) september 25, 2015 appendix c: system controller option 0: return to main menu this option returns to the menu level above. Gpio menu the system controller continuously scans specific user activated inputs and several onboard status signals. Po...

  • Page 115: Eeprom Menu

    Kcu105 board user guide www.Xilinx.Com 115 ug917 (v1.4) september 25, 2015 appendix c: system controller pmbus_cable_b = no fpga_iic_busy = no pmbus_alert = no option 0: return to main menu this option returns to the menu level above. Eeprom menu the system controller eeprom menu is used to read the...

  • Page 116: Config Menu

    Kcu105 board user guide www.Xilinx.Com 116 ug917 (v1.4) september 25, 2015 appendix c: system controller config menu the system controller config menu is used to configure the kcu105 ultrascale fpga from a micro-sd card. One of sixteen bitstreams can be selected for use by the configuration engine b...

  • Page 117

    Kcu105 board user guide www.Xilinx.Com 117 ug917 (v1.4) september 25, 2015 appendix c: system controller ultrascale fpga user design considerations the kcu105 system controller provides simplified access to the programmable features on the kcu105 over an i2c interface. This i2c interface is shared w...

  • Page 118: Overview

    Kcu105 board user guide www.Xilinx.Com 118 ug917 (v1.4) september 25, 2015 appendix d master constraints file listing overview the master xilinx design constraints (xdc) file template for the kcu105 board provides for designs targeting the kcu105 evaluation board. Net names in the constraints listed...

  • Page 119

    Kcu105 board user guide www.Xilinx.Com 119 ug917 (v1.4) september 25, 2015 appendix d: master constraints file listing set_property iostandard lvds [get_ports "user_sma_clock_n"] set_property package_pin d23 [get_ports "user_sma_clock_p"] set_property iostandard lvds [get_ports "user_sma_clock_p"] s...

  • Page 120

    Kcu105 board user guide www.Xilinx.Com 120 ug917 (v1.4) september 25, 2015 appendix d: master constraints file listing set_property package_pin ak22 [get_ports "ddr4_dq20"] set_property iostandard pod12_dci [get_ports "ddr4_dq20"] set_property package_pin al24 [get_ports "ddr4_dq21"] set_property io...

  • Page 121

    Kcu105 board user guide www.Xilinx.Com 121 ug917 (v1.4) september 25, 2015 appendix d: master constraints file listing set_property iostandard pod12_dci [get_ports "ddr4_dq49"] set_property package_pin aj34 [get_ports "ddr4_dq50"] set_property iostandard pod12_dci [get_ports "ddr4_dq50"] set_propert...

  • Page 122

    Kcu105 board user guide www.Xilinx.Com 122 ug917 (v1.4) september 25, 2015 appendix d: master constraints file listing set_property package_pin ag14 [get_ports "ddr4_a15_cas_b"] set_property iostandard sstl12_dci [get_ports "ddr4_a15_cas_b"] set_property package_pin af14 [get_ports "ddr4_a16_ras_b"]...

  • Page 123

    Kcu105 board user guide www.Xilinx.Com 123 ug917 (v1.4) september 25, 2015 appendix d: master constraints file listing set_property iostandard diff_sstl12_dci [get_ports "ddr4_ck_c"] set_property package_pin ae16 [get_ports "ddr4_ck_t"] set_property iostandard diff_sstl12_dci [get_ports "ddr4_ck_t"]...

  • Page 124

    Kcu105 board user guide www.Xilinx.Com 124 ug917 (v1.4) september 25, 2015 appendix d: master constraints file listing set_property package_pin j14 [get_ports "fmc_hpc_ha05_n"] set_property iostandard lvds [get_ports "fmc_hpc_ha05_n"] set_property package_pin j15 [get_ports "fmc_hpc_ha05_p"] set_pro...

  • Page 125

    Kcu105 board user guide www.Xilinx.Com 125 ug917 (v1.4) september 25, 2015 appendix d: master constraints file listing set_property iostandard lvds [get_ports "fmc_hpc_ha19_p"] set_property package_pin b19 [get_ports "fmc_hpc_ha20_n"] set_property iostandard lvds [get_ports "fmc_hpc_ha20_n"] set_pro...

  • Page 126

    Kcu105 board user guide www.Xilinx.Com 126 ug917 (v1.4) september 25, 2015 appendix d: master constraints file listing set_property package_pin k8 [get_ports "fmc_hpc_la10_n"] set_property iostandard lvds [get_ports "fmc_hpc_la10_n"] set_property package_pin l8 [get_ports "fmc_hpc_la10_p"] set_prope...

  • Page 127

    Kcu105 board user guide www.Xilinx.Com 127 ug917 (v1.4) september 25, 2015 appendix d: master constraints file listing set_property iostandard lvds [get_ports "fmc_hpc_la24_p"] set_property package_pin d21 [get_ports "fmc_hpc_la25_n"] set_property iostandard lvds [get_ports "fmc_hpc_la25_n"] set_pro...

  • Page 128

    Kcu105 board user guide www.Xilinx.Com 128 ug917 (v1.4) september 25, 2015 appendix d: master constraints file listing set_property package_pin w23 [get_ports "fmc_lpc_la00_cc_p"] set_property iostandard lvds [get_ports "fmc_lpc_la00_cc_p"] set_property package_pin y25 [get_ports "fmc_lpc_la01_cc_n"...

  • Page 129

    Kcu105 board user guide www.Xilinx.Com 129 ug917 (v1.4) september 25, 2015 appendix d: master constraints file listing set_property iostandard lvds [get_ports "fmc_lpc_la15_n"] set_property package_pin ab25 [get_ports "fmc_lpc_la15_p"] set_property iostandard lvds [get_ports "fmc_lpc_la15_p"] set_pr...

  • Page 130

    Kcu105 board user guide www.Xilinx.Com 130 ug917 (v1.4) september 25, 2015 appendix d: master constraints file listing set_property package_pin y32 [get_ports "fmc_lpc_la30_n"] set_property iostandard lvds [get_ports "fmc_lpc_la30_n"] set_property package_pin y31 [get_ports "fmc_lpc_la30_p"] set_pro...

  • Page 131

    Kcu105 board user guide www.Xilinx.Com 131 ug917 (v1.4) september 25, 2015 appendix d: master constraints file listing #gpio pmod0 set_property package_pin ak25 [get_ports "pmod0_0_ls"] set_property iostandard lvcmos12 [get_ports "pmod0_0_ls"] set_property package_pin an21 [get_ports "pmod0_1_ls"] s...

  • Page 132

    Kcu105 board user guide www.Xilinx.Com 132 ug917 (v1.4) september 25, 2015 appendix d: master constraints file listing set_property package_pin ap13 [get_ports "hdmi_r_d2"] set_property iostandard lvcmos18 [get_ports "hdmi_r_d2"] set_property package_pin an13 [get_ports "hdmi_r_d3"] set_property ios...

  • Page 133

    Kcu105 board user guide www.Xilinx.Com 133 ug917 (v1.4) september 25, 2015 appendix d: master constraints file listing set_property iostandard lvcmos18 [get_ports "phy_reset_ls"] set_property package_pin p25 [get_ports "sgmii_rx_n"] set_property iostandard diff_hstl_i_18 [get_ports "sgmii_rx_n"] set...

  • Page 134

    Kcu105 board user guide www.Xilinx.Com 134 ug917 (v1.4) september 25, 2015 appendix d: master constraints file listing set_property package_pin aj10 [get_ports "sysctlr_gpio_5"] set_property iostandard lvcmos18 [get_ports "sysctlr_gpio_5"] set_property package_pin ag9 [get_ports "sysctlr_gpio_6"] se...

  • Page 135

    Kcu105 board user guide www.Xilinx.Com 135 ug917 (v1.4) september 25, 2015 appendix e board setup installing the kcu105 board in a pc chassis installation of the kcu105 board inside a computer chassis is required when developing or testing pci express® functionality. When the kcu105 board is used in...

  • Page 136

    Kcu105 board user guide www.Xilinx.Com 136 ug917 (v1.4) september 25, 2015 appendix e: board setup 6. Install the top mounting bracket screw into the pc expansion cover retainer bracket to secure the kcu105 board in its slot. Important: the kcu105 board is taller than standard pcie cards. Ensure tha...

  • Page 137: Dimensions

    Kcu105 board user guide www.Xilinx.Com 137 ug917 (v1.4) september 25, 2015 appendix f board specifications dimensions height: 5.5 inch (14.0 cm) length: 10.5 inch (26.7 cm) important: the kcu105 board height exceeds the standard 4.376 inch (11.15 cm) height of a pci express ® card. Environmental tem...

  • Page 138: Overview

    Kcu105 board user guide www.Xilinx.Com 138 ug917 (v1.4) september 25, 2015 appendix g regulatory and compliance information overview this product is designed and tested to conform to the european union directives and standards described in this section. Refer to the kcu105 board master answer record...

  • Page 139: Safety

    Kcu105 board user guide www.Xilinx.Com 139 ug917 (v1.4) september 25, 2015 appendix g: regulatory and compliance information electromagnetic compatibility en 55022:2010, information technology equipment radio disturbance characteristics – limits and methods of measurement en 55024:2010, information ...

  • Page 140: Xilinx Resources

    Kcu105 board user guide www.Xilinx.Com 140 ug917 (v1.4) september 25, 2015 appendix h additional resources and legal notices xilinx resources for support resources such as answers, documentation, downloads, and forums, see xilinx support . Solution centers see the xilinx solution centers for support...

  • Page 141

    Kcu105 board user guide www.Xilinx.Com 141 ug917 (v1.4) september 25, 2015 appendix h: additional resources and legal notices 7. Ultrascale fpgas transceivers wizard product guide for vivado design suite ( pg182 ) 8. Ultrascale architecture gen3 integrated block for pci express logicore ip product g...

  • Page 142

    Kcu105 board user guide www.Xilinx.Com 142 ug917 (v1.4) september 25, 2015 appendix h: additional resources and legal notices 28. Silicon labs: www.Silabs.Com (si5335a, si570, si53340, si5328b) 29. Pci express ® standard: www.Pcisig.Com/specifications 30. Sff-8431 specification: ftp.Seagate.Com/sff ...

  • Page 143

    Kcu105 board user guide www.Xilinx.Com 143 ug917 (v1.4) september 25, 2015 appendix h: additional resources and legal notices in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection wi...