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Xilinx Spartan-6 FPGA Series User Manual

Other manuals for Spartan-6 FPGA Series: Design And Pin Planning Manual
Manual is about: Printed circuit boards

Summary of Spartan-6 FPGA Series

  • Page 1

    Spartan-6 fpga power management user guide ug394 (v1.1) september 4, 2012.

  • Page 2: Revision History

    Spartan-6 fpga power management www.Xilinx.Com ug394 (v1.1) september 4, 2012 notice of disclaimer the information disclosed to you hereunder (the “materials”) is provided solely for the selection and use of xilinx products. To the maximum extent permitted by applicable law: (1) materials are made a...

  • Page 3: Table of Contents

    Spartan-6 fpga power management www.Xilinx.Com 3 ug394 (v1.1) september 4, 2012 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 preface: about this guide guide contents . . . . . . . . . . . . . . . . . . . ...

  • Page 4

    4 www.Xilinx.Com spartan-6 fpga power management ug394 (v1.1) september 4, 2012 post-configuration crc limitations when using suspend mode . . . . . . . . . . . . 22 fpga voltage requirements during suspend mode . . . . . . . . . . . . . . . . . . . . . . . . 24 memory controller block . . . . . . ....

  • Page 5: About This Guide

    Spartan-6 fpga power management www.Xilinx.Com 5 ug394 (v1.1) september 4, 2012 preface about this guide this document provides information on the various hardware methods of power management in spartan-6 fpgas, primarily focusing on the suspend mode. Other power management topics include the lower-...

  • Page 6

    6 www.Xilinx.Com spartan-6 fpga power management ug394 (v1.1) september 4, 2012 running h/f 3 • spartan-6 fpga clocking resources user guide this guide describes the clocking resources available in all spartan-6 devices, including the dcms and plls. • spartan-6 fpga block ram resources user guide th...

  • Page 7: Introduction

    Spartan-6 fpga power management www.Xilinx.Com 7 ug394 (v1.1) september 4, 2012 chapter 1 power management with suspend mode introduction some applications require the lowest possible system cost or highest performance, and other applications require the lowest possible standby power. Spartan®-6 fpg...

  • Page 8: Suspend Features

    8 www.Xilinx.Com spartan-6 fpga power management ug394 (v1.1) september 4, 2012 chapter 1: power management with suspend mode suspend features the significant features and benefits of the suspend mode: • quickly and easily puts the fpga into a static condition, eliminating most active current. • red...

  • Page 9

    Spartan-6 fpga power management www.Xilinx.Com 9 ug394 (v1.1) september 4, 2012 entering suspend mode the fpga can only enter suspend mode if enabled in the configuration bitstream (see enable the suspend feature and glitch filtering, page 14 ). The suspend pin must be low during power up and config...

  • Page 10

    10 www.Xilinx.Com spartan-6 fpga power management ug394 (v1.1) september 4, 2012 chapter 1: power management with suspend mode each fpga output pin or bidirectional i/o pin assumes its defined suspend mode behavior, which is described as part of the fpga design using a suspend attribute. The awake p...

  • Page 11

    Spartan-6 fpga power management www.Xilinx.Com 11 ug394 (v1.1) september 4, 2012 entering suspend mode 3. After a delay of t suspendhigh_awake , the fpga drives the awake output low to indicate that it is entering suspend mode. 4. After a delay of t suspend_gts , the fpga switches the normal behavio...

  • Page 12: Exiting Suspend Mode

    12 www.Xilinx.Com spartan-6 fpga power management ug394 (v1.1) september 4, 2012 chapter 1: power management with suspend mode exiting suspend mode there are four possible ways to exit suspend mode in a powered system: • drive the suspend input low, exiting suspend mode. • if multi-pin wake-up mode ...

  • Page 13

    Spartan-6 fpga power management www.Xilinx.Com 13 ug394 (v1.1) september 4, 2012 exiting suspend mode x-ref target - figure 1-3 figure 1-3: exiting suspend mode s u s pend attri bu te s u s pend attri bu te w a ke-up timing clock s o u rce glitch filter sus pend en ab le s rl lut ram flip-flop s l a...

  • Page 14

    14 www.Xilinx.Com spartan-6 fpga power management ug394 (v1.1) september 4, 2012 chapter 1: power management with suspend mode program_b programming pin always overrides suspend mode pulsing the program_b programming pin low always overrides suspend mode and forces the fpga to restart configuration....

  • Page 15

    Spartan-6 fpga power management www.Xilinx.Com 15 ug394 (v1.1) september 4, 2012 enable the suspend feature and glitch filtering define the multi-pin wake-up feature and pins the multi-pin wake-up feature is not required to use the suspend mode feature. If multi-pin wake-up is not enabled, suspend m...

  • Page 16

    16 www.Xilinx.Com spartan-6 fpga power management ug394 (v1.1) september 4, 2012 chapter 1: power management with suspend mode although for any differential standard the settings must be set appropriately for both pins of the complementary pair. When in the high-impedance state, the differential dri...

  • Page 17

    Spartan-6 fpga power management www.Xilinx.Com 17 ug394 (v1.1) september 4, 2012 suspend mode wake-up timing controls design requirements to maintain application data when a design requires that application data be preserved when entering suspend mode, the suspend_sync primitive should be used. When...

  • Page 18

    18 www.Xilinx.Com spartan-6 fpga power management ug394 (v1.1) september 4, 2012 chapter 1: power management with suspend mode • the sw_clk option is specific to the suspend feature. By default, sw_clk:internalclk . • the startupclk option is available on every application. The same option used to c...

  • Page 19

    Spartan-6 fpga power management www.Xilinx.Com 19 ug394 (v1.1) september 4, 2012 dedicated configuration pins unaffected during suspend mode switch outputs from suspend to normal behavior the suspend/wake sw_gts_cycle bitstream option controls when i/o pins are released from their suspend attribute ...

  • Page 20: Suspend Pin

    20 www.Xilinx.Com spartan-6 fpga power management ug394 (v1.1) september 4, 2012 chapter 1: power management with suspend mode do not use any other jtag instructions when in suspend mode or while transitioning into and out of suspend mode. Furthermore, do not enter suspend mode when performing a rea...

  • Page 21: Suspend Input Glitch Filter

    Spartan-6 fpga power management www.Xilinx.Com 21 ug394 (v1.1) september 4, 2012 suspend input glitch filter suspend input glitch filter the suspend pin has a programmable glitch filter to guard against short pulses, which could cause the fpga to spuriously enter suspend mode. Turning off the filter...

  • Page 22

    22 www.Xilinx.Com spartan-6 fpga power management ug394 (v1.1) september 4, 2012 chapter 1: power management with suspend mode the awake output pin is supplied by the v cco power rail on bank 1. When the option drive_awake:yes is set, the awake pin is an active output driver, equivalent to a user i/...

  • Page 23

    Spartan-6 fpga power management www.Xilinx.Com 23 ug394 (v1.1) september 4, 2012 post-configuration crc limitations when using suspend mode several design options are possible: 1. Do not use the post-configuration crc feature when the suspend mode feature is enabled and vice versa. 2. Always reprogr...

  • Page 24: Memory Controller Block

    24 www.Xilinx.Com spartan-6 fpga power management ug394 (v1.1) september 4, 2012 chapter 1: power management with suspend mode fpga voltage requirements during suspend mode during suspend mode, the v ccint and v ccaux rails must remain powered at the data sheet levels for recommended operating condi...

  • Page 25: Voltage Supplies

    Spartan-6 fpga power management www.Xilinx.Com 25 ug394 (v1.1) september 4, 2012 chapter 2 voltage supplies introduction spartan-6 fpgas have multiple voltage supply inputs, as shown in table 2-1 . There are two supply inputs for internal logic functions, v ccint and v ccaux . Each of the i/o banks ...

  • Page 26

    26 www.Xilinx.Com spartan-6 fpga power management ug394 (v1.1) september 4, 2012 chapter 2: voltage supplies v ccint v ccint is the primary power supply for the fpga. In the spartan-6 lxt family and the standard devices in the spartan-6 lx family (-2 and -3 speed grades), v ccint has a nominal value...

  • Page 27

    Spartan-6 fpga power management www.Xilinx.Com 27 ug394 (v1.1) september 4, 2012 vcco setting the v ccaux level the user must set the config v ccaux attribute according to the voltage being provided to the v ccaux rails. The valid values for this attribute are 2.5 (default) or 3.3. This attribute af...

  • Page 28

    28 www.Xilinx.Com spartan-6 fpga power management ug394 (v1.1) september 4, 2012 chapter 2: voltage supplies v ref each i/o bank also has a separate, optional input voltage reference supply, called v ref . If the i/o bank includes an i/o standard that requires a voltage reference such as hstl or sst...

  • Page 29: Introduction

    Spartan-6 fpga power management www.Xilinx.Com 29 ug394 (v1.1) september 4, 2012 chapter 3 lower-power spartan-6 lx devices introduction the lower-power spartan-6 lx devices (-1l) meet lower quiescent and dynamic current levels than the standard spartan-6 lx devices. They also operate at a reduced v...

  • Page 30

    30 www.Xilinx.Com spartan-6 fpga power management ug394 (v1.1) september 4, 2012 chapter 3: lower-power spartan-6 lx devices table 3-1 summarizes the designations for a member of the lower-power spartan-6 lx devices. Lower-power spartan-6 lx device specifications several specifications are different...

  • Page 31: Including Hibernate

    Spartan-6 fpga power management www.Xilinx.Com 31 ug394 (v1.1) september 4, 2012 chapter 4 power-on and power-down behavior including hibernate introduction spartan-6 fpgas are designed for maximum system flexibility and reliability when powering up and powering down. During power-on, the device ens...

  • Page 32: Supply Sequencing

    32 www.Xilinx.Com spartan-6 fpga power management ug394 (v1.1) september 4, 2012 chapter 4: power-on and power-down behavior including hibernate the v cco_2 supplies are part of the por circuit, because the primary configuration pins are in bank 2. V cco_2 is typically at 2.5v or 3.3v for the config...

  • Page 33: Hibernate Power Down

    Spartan-6 fpga power management www.Xilinx.Com 33 ug394 (v1.1) september 4, 2012 configuration data retention and brown out configuration data retention and brown out the fpga's configuration data is stored in robust cmos configuration latches. The data in these latches is retained even when the vol...

  • Page 34

    34 www.Xilinx.Com spartan-6 fpga power management ug394 (v1.1) september 4, 2012 chapter 4: power-on and power-down behavior including hibernate forcing fpga to quiescent current levels before removing the power supplies, it is recommended to first put the device into the quiescent state. Pulse prog...

  • Page 35

    Spartan-6 fpga power management www.Xilinx.Com 35 ug394 (v1.1) september 4, 2012 hibernate power down turn off v cco spartan-6 fpga i/o pins have a floating-well structure, providing full hot-swap/ hot-insertion capability. When a spartan-6 fpga is in the hibernate state, the v cco supply can be saf...

  • Page 36

    36 www.Xilinx.Com spartan-6 fpga power management ug394 (v1.1) september 4, 2012 chapter 4: power-on and power-down behavior including hibernate exiting hibernate the steps for exiting hibernate are as follows. 1. Reapply power to all rails that were switched off. Apply power in any sequence. 2. Bef...

  • Page 37: Power Estimation

    Spartan-6 fpga power management www.Xilinx.Com 37 ug394 (v1.1) september 4, 2012 chapter 5 power estimation introduction xilinx provides a complete power estimation solution using power estimators and analyzers, power-driven implementation tool algorithms, and a variety of power-related documentatio...

  • Page 38: Saving Power

    38 www.Xilinx.Com spartan-6 fpga power management ug394 (v1.1) september 4, 2012 chapter 5: power estimation if necessary, slow the supply voltage ramp to control the charge current. If foldback is not a design requirement, it is best to avoid it, keeping the power-supply design simple. Various powe...

  • Page 39

    Spartan-6 fpga power management www.Xilinx.Com 39 ug394 (v1.1) september 4, 2012 ise design suite power optimization saving clock routing power clocks are a significant aspect of power consumption because of their high fanout nets and also because controlling them limits the number of logic primitiv...

  • Page 40

    40 www.Xilinx.Com spartan-6 fpga power management ug394 (v1.1) september 4, 2012 chapter 5: power estimation.