Cadence ASSURA PHYSICAL VERIFICATION Datasheet
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BENEFITS
• Trusted solution with hundreds of users
worldwide
• Key component of Virtuoso physical
design and simulation platform
• Intuitive and powerful debug
environment based on Virtuoso
platform accelerates check/rework cycle
• Seamless integration with Cadence QRC
transistor-based parasitic extraction
and simulation flow gives fast, silicon-
accurate analysis
• Advanced design rule capabilities
facilitate nanometer process checks
FEATURES
UNIFIEd dESIgN, VERIFIcATIoN,
ANd ANAlySIS ENVIRoNmENT
Assura Physical Verification is an integral
part of the Virtuoso Custom Design
Platform. Every release of Assura Physical
Verification is flow tested with the other
ASSURA PHYSICAL VERIFICATION
ASSURA PHySIcAl
VERIFIcATIoN
Assura Physical Verification forms a
key component of the design, parasitic
extraction and simulation flow within the
Virtuoso Custom Design Platform. As a
trusted solution with many hundreds of
users worldwide, it enables design teams
to check, identify, and correct design and
connectivity errors to achieve design sign-
off before tape-out.
The technology uses hierarchical
processing and multiprocessing
techniques to rapidly facilitate accurate
identification and correction of design
rule errors in even the most advanced
designs. With its GUI-guided debugging
environment, Assura Physical Verification
accelerates the debug and rework cycle
and so reduces overall verification cycle
time. Assura Physical Verification provides
the best choice for fast and silicon-
accurate analysis of custom, AMS, and RF
IC designs and IP blocks.
platform components. The resulting unified
environment accelerates custom design,
verification, analysis, and simulation
leading to increased design productivity,
chip performance, and silicon yield.
PERFoRmANcE ANd cAPAcITy
Assura Physical Verification uses
hierarchical processing and multiprocessor
techniques to increase performance and
capacity. Assura Physical Verification
efficiently processes highly repetitive
structures (such as memory) with its
hierarchical processing techniques. A
hierarchical debugging capability further
accelerates the debug cycle because
multiple instances of errors in the same
hierarchy only have to be corrected once.
Finally, multiprocessing increases design
throughput by leveraging cost-effective
and ubiquitous multi-CPU hardware.
Cadence
®
Assura
®
Physical Verification—a key component
of the design verification suite of tools within the Cadence
Virtuoso
®
Custom Design Platform—is the physical
verification solution of choice for AMS/custom designers. It
utilizes hierarchical processing and multiprocessing for fast,
efficient verification in both interactive and batch mode.