Cadence ASSURA PHYSICAL VERIFICATION Datasheet - page 3
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ASSURA PHYSICAL VERIFICATION
SUPPoRT oF mIxEd-SIgNAl
dESIgNS
Assura Physical Verification has the ability
to recognize standard and special devices
(e.g., n-terminal devices, drawn inductors,
multi-emitter/collector bipolar transistors,
STI, ROMs, etc.), making it an excellent
choice for mixed-signal designs. All devices
extracted by Assura Physical Verification
are automatically netlisted and passed
into Cadence QRC parasitic extraction to
avoid double-counting during parasitic
extraction. Assura Physical Verification also
has the capability to process mixed-signal
designs that combine schematics from
CDL, SPICE, and Verilog.
SPEcIFIcATIoNS
PowERFUl RUlE lANgUAgE/
SyNTAx
• Area-based rules allow multiple design
rules on a single chip
• Pattern checking capability accelerates
implementation of advanced checks
• Hierarchical area fill capabilities with sup-
port for customer-defined filler cells
• SKILL-based rules language facilitates
complex data manipulations and DRC
rules
• Comprehensive set of electrical rule
checks
• Antenna rule syntax supports conjunc-
tive, conditional rules and multiple
checks in one run
• Advanced features include data snap-
ping, end-of-line checks, corner com-
mands
• Supports BSIM well proximity checks
• Width-dependent separation check
(a.k.a. 90nm halation rule)
• Advanced via cluster checks
EASy-To-USE gRAPHIcAl USER
INTERFAcE (gUI)
• Tightly integrated with the Virtuoso
platform
• Fast error correction using edit-in-place
or descend modes within Virtuoso
Layout Editor
• Access layout data in edit- or read-only
modes
• Hierarchical error reporting and cross-
probing for blocks, cells, devices, nets,
and pins
• Show errors by rule type or by layout
cell
• Immediate error and warning messages
during interactive sessions via command
interpreter window (CIW)
• Perform XOR comparison between two
databases
• Support sign-off or false error marker
exception handling
• Window DRC operation allows fast
localized checking, especially useful
during chip assembly or for last minute
edits to reduce redundant checking and
runtimes
• Time-to-error capability
• Integration with QuickView to open
and debug large designs
• Ability to view interim layers (for rule
deck developers)
comPREHENSIVE gUI-gUIdEd lVS
dEBUggINg ToolS
• Extraction errors
• Short Locator
• Open Locator
• Malformed Device Tool
• Comparison errors
• Nets Mismatch
• Devices Mismatch Tool
• Pins Mismatch Tool
• Parameters Mismatch Tool
• Rewire Tool
Figure 3. Assura Physical Verification offers a guided LVS debug environment, integrated into the Virtuoso
Custom Design Platform, that accelerates rework and overall physical verification cycle time