Cadence ASSURA PHYSICAL VERIFICATION Datasheet - page 2
2
www.cadence.com
ASSURA PHYSICAL VERIFICATION
INTERAcTIVE ANd BATcH
VERIFIcATIoN
Assura Physical Verification supports runs
in interactive and batch mode. Interactive
physical verification integrated within the
Virtuoso Custom Design Platform helps
designers to maximize silicon performance
and yield in hand-crafted, full custom IP.
Designers can then script and run Assura
Physical Verification in batch mode once
the custom IP blocks are assembled as a
finished chip. A single rule file supports
both interactive and batch verification
modes.
ElEcTRIcAl RUlE cHEckS
A comprehensive set of electrical rule
check (ERC) commands verifies that
designs conform to connection, tracing,
and specific connectivity properties that
are established for a given fabrication
process or process variant.
Assura Physical Verification provides full
set of ERC capabilities, including:
• External Connection Definition Rules
• Path Tracing Rules
• Nonfunctional Device Checking Rules
• Specific Connectivity
• Debug GUI support for ERC
UNIqUE PATTERN cHEckINg
cAPABIlITy
Certain advanced checks, such as metal
enclosure of contact at line-end, are
not easy to write and are best checked
using pattern recognition methods.
Assura Physical Verification incorporates
unique pattern checking capabilities to
accelerate advanced rule development
and maintenance for checks that would
be difficult to write using traditional
approaches. This approach can provide
up to 20x performance improvement
for advanced checks, which in turn can
improve the overall run-time for the entire
DRC task by up to 2x.
dENSITy cHEck ANd mETAl FIll
Assura Physical Verification offers context-
sensitive fill patterns, meaning users can
place whatever patterns wherever they are
needed in the layout. Users can customize
fill patterns and shapes (e.g., custom fill
cells, squares, rectangles, skewed, bridging
bars) as necessary to balance layout
density. The area fill command is also
capable of connecting area fill features.
Assura Physical Verification can perform
area fill in flat or hierarchical mode.
gUI-gUIdEd lVS dEBUg
ENVIRoNmENT
Assura Physical Verification offers a GUI
debug environment that interactively
steps users through the process of
resolving LVS errors. Once the LVS run
is complete, users can choose to open
the LVS debug tools, such as the short
locator and rewire function, from the
pop-up window to examine and correct
the errors.
Environment polygons
Primary polygons
Figure 1: A set of design rules are described by drawings in a model file (GDSII, DFII, text vertices). A model
contains a primary polygon (e.g., contact, fuse opening, DRC error markers) and environment polygons
(e.g., metals enclosing contact, fuse metals/vias, waivable layout configuration per error marker). Pattern
check is triggered by primary polygons in the design.
3
1
2
Figure 2. Sample context-dependent fill recipe: rectangular fill (1) under bond pad, grounded
multi-layer custom fill (2) pattern in empty areas, skewed square fill (3) under power lines.