Cadence CADENCE CHIP PLANNING SYSTEM Datasheet
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ecosystem at ChipEstimate.com, is hosted
on the enterprise’s server. The server can
then be accesses by dispersed chip design
teams (both internal and external).
This approach enables simple-to-use early
exploration of performance, power, and
size utilizing enterprise-specific IP. Typical
users include: technical team members
(design architects, chip integrators, design
leads, and engineering management),
as well as business team members (field
sales consultants, technical marketing, IC
component procurement, RFQ responders,
and executive management). It is useful for
large fabless semiconductor companies,
integrated device manufacturers (IDMs),
ASIC vendors, and design service providers.
BENEFITS
• For integrated device manufacturers
(IDMs) and large fabless semiconductor
companies
- Facilitate use of your internally
developed process libraries and
CADENCE CHIP PLANNING SYSTEM
CADENCE CHIP
PLANNING SYSTEM
In order to deliver increasingly complex
chips on the same schedules, chip design
projects must be able to take advantage of
re-used IP—both internally and externally
developed. Companies implementing
chips from multiple design teams have
developed large suites of IP that often span
different objectives—such as performance,
power, size, and functionality—in addition
to different processes. The challenge
becomes one of helping design teams
choose the proper IP when planning their
chip projects.
A client-server model enables chip
design teams to explore a variety of IP,
architectures, memories, and processes,
in order to determine how they will meet
their project’s goals. An IP modeler also
enables enterprises to populate the system
with accurate high-level models and
datasheets suitable for pre-RTL exploration.
This data, which can be optionally
supplemented with the industry-leading IP
digital, analog, and mixed-signal IP in
diverse chip design projects
- Control over data access—what
IP and libraries, and what type of
information (technical, economic)—is
available to each user
• For ASIC vendors and design service
providers
- Field sales consultants can always
access the latest data in order to
deliver accurate project estimates and
quotes quickly
- Enable customers to access the
technical data for your IP and library
models for chip planning
• Improve predictability of success by
closing early on a specification that best
balances size, power, and costs, using
real IP, process, and architecture data
• Estimate power at the architectural
level and plan the block- and chip-
level power strategies, model different
power modes, and generate a CPF file
to drive downstream implementation
The Cadence
®
Chip Planning System is an enterprise-level solution
that enables multiple dispersed project teams to perform early
chip planning using models of internally developed intellectual
property. An IP model generator populating a central server allows
internal and external chip design teams to perform “what-if”
estimations of die size, power consumption, performance, and
total chip cost. The Cadence Chip Planning System provides a
complete solution to rapidly explore, plan, and estimate chip
design projects utilizing accurate models of a company’s own IP,
processes, and libraries.