Cadence CADENCE CHIP PLANNING SYSTEM Datasheet - page 2
2
www.cadence.com
VIRTUOSO ANALOG DESIGN ENVIRONMENT GXL
• Centralized tracking of chip estimations
and IP usage to better understand
consumption patterns and customer
needs
• Reduced implementation risk delivered
by early planning followed by a
convergent flow—the architecture
and library data is passed forward to
drive implementation tools, which
feed back implemented block data to
refine accuracy of the model and drive
in-project decisions
• The Cadence Chip Planning System
client is easy to use for technical and
non-technical users alike, enabling
collaboration and communication
between the business and technical
teams starting with early planning and
continuing throughout the course of
the project
FEATURES
The Cadence Chip Planning System
operates in a client-server model. The client
is the CCPS User Estimation application
on the project team’s Windows or Linux
desktop. On the server side, the CCPS
IP Modeler generates accurate models
and datasheets for chip planning and
estimation, populating the CCPS Server
with all the data needed for the client
application to estimate chip design
projects.
CADENCE CHIP PLANNING SYSTEM
SERVER
A centralized server application for hosting
the enterprise’s IP and library models, the
Cadence Chip Planning System Server
enables dispersed users, both internal and
external to the enterprise, to always have
access to up-to-date estimation data.
• Centralized server to host IP, library, and
memory models
• Web-based IP catalog management
system
• Up-to-date model information available
to internal and/or external users
• Access to specific models, technical
specs, and economic data is controllable
per user
• Generate reports on overall IC designs
• Track IP usage by chip and by user
• Custom and tunable process models for
highest degree of technical accuracy
• Tunable economic models for more
accurate business lifecycle planning
• Can optionally include the full
ChipEstimate.com ecosystem of IP
CADENCE CHIP PLANNING
SYSTEM USER
The Cadence Chip Planning System User
client application enables diverse users
such as design teams, technical marketing,
field sales consultants, and management to
access up-to-date model information from
the CCPS Server in order to quickly and
accurately estimate and plan chip design
projects.
• Estimate design size
• Estimate design power (dynamic and
leakage)
• Compare size, power, and performance
of multiple designs or design variations
• Estimate performance achievability in
specific manufacturing processes with
specific IP components
• Create and edit a block diagram of the
design, use drag & drop for blocks, and
drawing tools for connectivity
• Edit the floorplan view to analyze
impact of movement and rotation on
size, power, performance, and cost
Cadence Chip Planning System
Complete infrastructure for chip
planning and estimation
using proprietary IP
CCPS Client
(Project team 2)
CCPS Client
(Project team 1)
CCPS Client
(Management)
CCPS Server
CCPS
IP Modeler
CCPS Client
(Field sales
consultants)