Cadence CADENCE CHIP PLANNING SYSTEM Datasheet - page 3
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21172 09/09 KM/MVC/DM/PDF
• Create power profiles with various
modes, assign percent-active time for
modes
• Easily enable advanced power
management techniques, including
power shutoff, multi-supply/multi-
voltage, and clock gating, while
measuring the size and power impact
of these techniques
• If enabled by the server:
- Economic analysis, including yield-
affected wafer costs yield, package
costs, test & assembly costs, Non-
Recurring Engineering (NRE) charges,
plotted along economic lifecycle
tables and graphs
- Generate complete IC economic
analysis reports and budgetary quotes
• Bi-directional interface to Cadence
Encounter RTL Compiler synthesis
solution, feeding forward SDC, module
definitions, floorplan guidance, and
synthesis scripts; feed back synthesized
gate counts of random logic blocks and
compare versus earlier estimates
• Bi-directional interface to Cadence
Encounter
®
Digital Implementation
System, feeding forward SDC, module
definitions, floorplan guidance, and
implementation scripts; feed back
implementation metrics to enable
economic analysis and compare versus
earlier estimates
CADENCE CHIP PLANNING SYSTEM
IP MODELER
In order to populate the server with data
that can be used for estimation, the
enterprise’s IP, libraries and memories
must be properly modeled. The Cadence
Chip Planning System IP Modeler utilizes
standard design kits and memory compilers
to generate accurate macro models for use
in estimation.
• The same proven-accurate modeling
technology used for the extensive
ChipEstimate.com suite of models,
on-site at the enterprise with full ability
to tune and customize
• Characterizes cell libraries and
processes using industry-standard
Liberty and LEF data
• Memory compilers are analyzed
and exercised to produce accurate
polynomial models
• Modeler scaling technology enables
quick-and-easy modeling of process
migration
STANDALONE CLIENT-ONLY VERSION
For fabless companies and design houses
using commercially available IP and process
technology, the Cadence InCyte Chip
Estimator delivers fast, accurate, and easy to
use estimation to drive “what-if” exploration
and planning. For more information on this
version, please consult the Cadence InCyte
Chip Estimator datasheet.
SYSTEM SPECIFICATION
• Windows XP, Windows XP Pro, and
Windows Vista
• Linux (32-bit, 64-bit) RHEL 4.0, 5.0,
SLES 10, 9
• Sun Solaris (32-bit, 64-bit) Solaris 10
Visit www.ChipEstimate.com to
register and search through 7000
pieces of IP from over 200 IP Providers
and Foundries.
For more information
contact Cadence sales at:
+1.408.943.1234
or log on to:
www.cadence.com/
contact_us