Cadence CADENCE ORCAD FPGA SYSTEM PLANNER System Planner - page 3
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CADEnCE OrCAD FPGA SySTEm PlAnnEr
pin-assignment suggestions from the
PCB layout designer. Once a change is
made to the pin assignment by the FPGA
designer, the pin assignment change has
to be made in the schematic design by
the hardware designer. Such iterations
add several days if not weeks to the
design cycle and possibly a great deal of
frustration for the team members. Since
this is a manual process, mistakes that
are not detected can also cause expensive
physical prototype iterations.
While it may help to automate the
synchronization of changes made to the
pin assignment by the FPGA designer,
hardware designer, or PCB layout
designer, it doesn’t reduce the root cause
of these iterations. Pin assignment that
is not guided by all three aspects—FPGA
resource availability, FPGA vendor pin
assignment rules, and routability of FPGA
pins on a PCB—requires many iterations
at the tail end of the design process,
thereby extending the time it takes to
integrate today’s complex, large-pin-count
FPGAs on a PCB.
SPeCiFYinG DeSiGn inTenT
The OrCAD FPGA System Planner comes
with an FPGA device library to help with
selection of devices to be placed. It uses
OrCAD PCB Editor footprints for the
floorplan view and allows users to quickly
create relative placement of the FPGA
system components.
The OrCAD FPGA System Planner allows
users to specify connectivity between
components within the FPGA sub-system
at a higher level through interface
definitions. Users can create interfaces
such as DDR2, DDR3, and PCI Express,
and use these to specify connectivity
between an FPGA and a memory DIMM
module or between two FPGAs. The
OrCAD FPGA System Planner understands
differential signals, and power signals, as
well as clock signals.
FPGA DeViCe ruLeS
The OrCAD FPGA System Planner comes
with a library of device-accurate FPGA
models that incorporate pin assignment
rules and electrical rules specified by FPGA
device vendors. These FPGA models are
used by the synthesis engine to ensure
that the vendor-defined electrical usage
rules of the FPGAs are strictly adhered
to. These rules dictate such things as
clock and clock region selection, bank
allocation, SSO budgeting, buffer driver
utilization, I/O standard voltage reference
levels, etc. During synthesis, the OrCAD
FPGA System Planner automatically checks
hundreds of combinations of these rules
to ensure that the FPGA pins are optimally
and accurately utilized.
OrCAD
FPGA
System Planner
OrCAD
Capture/CIS
OrCAD
Part Library
Symbols, Footprints
FPGA
Vendor
Tools
OrCAD
PCB
Designer
Figure 3: The OrCAD FPGA System Planner uses symbols and footprints from existing libraries
Figure 4: OrCAD FPGA System Planner optimization