Cadence CADENCE ORCAD FPGA SYSTEM PLANNER System Planner - page 4
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CADEnCE OrCAD FPGA SySTEm PlAnnEr
PLACeMenT AWAre Pin
ASSiGnMenT SYnTHeSiS
The OrCAD FPGA System Planner
provides users a way to create an FPGA
system placement view using OrCAD
PCB footprints. Users specify connectivity
between components in the placement
view and the FPGA at a high level using
interfaces such as DDRx, PCI Express, SATA,
Front Side Bus, etc. that connect FPGAs
and other components in the design,
shortening the time to specify design
intent for the FPGA system.
Once the connectivity of the FPGA to
other components in the sub-system is
defined, the OrCAD FPGA System Planner
then synthesizes the pin assignment based
on the user’s design intent, available FPGA
resources, component placement around
the FPGA, and the FPGA vendor’s pin
assignment rules.
The OrCAD FPGA System Planner has
a built-in DRC engine that incorporates
the rules provided by FPGA vendors for
pin assignment, reference voltages, and
terminations. This rules-based engine
prevents PCB physical prototype iterations
as the FPGAs are always correctly
connected.
Pin assignment algorithms are optimized
to assign interface signals to a group of
pins, thereby minimizing net crossovers
and improving routability on the PCB.
TiGHT inTeGrATiOn WiTH
CADenCe DeSiGn CreATiOn
The OrCAD FPGA System Planner
generates OrCAD Capture, schematics
for the FPGA sub-system. It uses existing
symbols for FPGA in OrCAD Capture
symbol libraries. If the user desires, the
FPGA System Planner products can create
split symbols for FPGA based on the
connectivity or one split symbol per bank.
inTeGrATiOn WiTH FPGA
VenDOr TOOLS
In addition to integration with OrCAD
PCB design tools, the OrCAD FPGA
System Planner communicates seamlessly
with FPGA design tools. It generates
and reads supported FPGA vendors’ pin
assignment constraint files. This capability
enables the FPGA designer to evaluate
pin assignments against the functional
needs of the FPGA. Any changes made by
the FPGA designer to account for these
requirements can be imported into to the
OrCAD FPGA System Planner so that the
complete set of pin assignments remain
in sync.
Pre-rOuTe Pin ASSiGnMenT
OPTiMiZATiOn
The initial pin assignment—that accounts
for placement and routability of the
FPGA on a PCB—goes a long way toward
reducing costly design iterations between
FPGA designer, PCB layout designer, and
hardware designer. Once the PCB layout
designer starts to plan the routing of
interfaces and signals on FPGA, it is possible
to further refine the FPGA pin assignment
based on route intent, layer constraints,
and fanout chosen for the FPGA. The
OrCAD FPGA System Planner offers users
a way to optimize FPGA pin assignment
after placement and during routing of the
interfaces and signals on an FPGA.
OrCAD FPGA
System Planner
Allegro FPGA
System Planner L
Allegro FPGA
System Planner
Two FPGA Option
Allegro FPGA
System Planner XL
Allegro FPGA
System Planner
GXL
Concurrent device
optimization
1 FPGA
1 FPGA
2 FPGAs
4 FPGAs
Unlimited FPGAs
Placement-aware
synthesis
Yes
Yes
Yes
Yes
Yes
Reuse symbols
and footprints
Yes
Yes
Yes
Yes
Yes
Symbols &
schematic
generation
OrCAD Capture
Allegro Design Entry
CIS / Allegro Design
Entry HDL
Allegro Design Entry
CIS / Allegro Design
Entry HDL
Allegro Design Entry
CIS / Allegro Design
Entry HDL
Allegro Design Entry
CIS / Allegro Design
Entry HDL
Post-placement
optimization
No
Yes
Yes
Yes
Yes
Schematic power
connections
No
Yes
Yes
Yes
Yes
Schematic
terminations
No
Yes
Yes
Yes
Yes