Cadence CADENCE PALLADIUM XP - TECH BRIEF Manual
T
E
C
H
N
IC
A
L
B
R
IE
F
Cadence
®
Palladium
®
XP is a state-of-the-art hardware/software
verification computing platform. It unifies best-in-class simulation
acceleration and emulation capabilities in a single environment to
boost verification throughput and productivity. Its processor-based
compute engine and Unified Xccelerator Emulator software runs high-
performance verification applications and introduces flexible new
use models that transcend traditional emulation. With unmatched
scalability, advanced debug, hardware/software co-verification, and
support for dynamic power analysis, hard and soft IP, and metric-
driven verification, Palladium XP optimizes system design and
verification.
SYSTEM-LEVEL VERIFICATION CHALLENGE
Traditional verification tools have not kept pace with the rapid
rate at which system-on-chip (SoC) design size and complexity
are growing. This widens the hardware/software (HW/SW)
verification gap, limiting reusability and productivity and
increasing the likelihood of re-spins and schedule delays.
Traditional software simulators are ideal for IP or small design
development and verification, and they can simulate cluster- to
chip-level designs. However, as RTL design size increases, these
simulators slow down significantly, which delays HW/SW
(system) integration and prolongs the overall verification cycle.
CADENCE PALLADIUM XP
VERIFICATION COMPUTING PLATFORM
Figure 1: Palladium XP offers a unified high-performance
verification computing platform