Cadence CADENCE PALLADIUM XP - TECH BRIEF Manual - page 12
12
www.cadence.com
PALLADIUM XP VERIFICATION COMPUTING PLATFORM
level. Users can set up trigger conditions for power on/off and can use force operations to create
low-power scenarios just as they would use them for functional verification during normal acceleration/
emulation runs.
Palladium XP reads a common side file and helps designers verify power intent through the integrated
SimVision waveform viewer and log file messages. Low-power verification capabilities are inherent to
Palladium XP.
THIRD-PARTY SUPPORT
IP, MODELS, AND SOFTWARE
The Cadence IP Alliance Program enables interoperability and facilitates open collaboration among
leading IP providers to build, validate, and deliver accurate models for Cadence design and verification
solutions. It offers a broad and growing portfolio of world-class IP solutions paired with corresponding
verification IP components in most cases. The Cadence Verification Alliance Program helps Cadence
customers accelerate their adoption of new verification technologies and boosts their productivity.
TESTERS
To exercise (generate stimulus patterns) and to analyze protocol traffic patterns in a system-level
environment, Palladium XP enables the use of various third-party testers supporting most industry-
standard protocols. This helps verify protocol layers (full stack) while running software applications and
debug issues.
SPECIFICATIONS
Palladium XP is available in two main configurations: XL and GXL. Both are RoHS compliant. They share a
common architecture (MCM, memory cards, cables, software), providing the same functionality; however,
they differ in physical characteristics and scalability requirements.
Palladium XP (XL)
Palladium XP (GXL)
Scalable capacity and I/O
•Capacity: Up to 32 million gates
•I/O: Up to 3,072
•CMOS3.3V, 2.5V, 1.8V, 1.5V,
LVDS, HSTL, SSTL
•Capacity: Up to 2 billion gates
•I/O: Up to 147,456
•CMOS3.3V, 2.5V, 1.8V, 1.5V,
LVDS, HSTL, SSTL
Default dedicated user memory
Up to 16 gigabytes
Up to 1 terabyte
Simultaneous users
From 1 to 8 users
From 1 to 512 users
Architecture
Custom advanced processors (MCMs)
Design format and language
support
•HDL: RTL (VHDL, Verilog, SystemVerilog) and gate-level netlist
•HVL: C++, SystemC, Specman ‘e’, SystemVerilog, and Open
Verification Methodology (OVM) acceleration
•Assertions: System Verilog Assertions (SVA), Property Specification
Language (PSL), Incisive Assertion Library, and Open Verilog
Library (OVL)
Memory transformation
Options for memory placement, compaction, squeezing, read port
splitting, and merging