Cadence ENCOUNTER CONFORMAL EQUIVALENCE CHECKER Datasheet
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Cadence
®
Encounter
®
Conformal
®
Equivalence Checker (EC),
makes it possible to verify and debug multi-million-gate designs
without using test vectors. It offers the only complete equivalence
checking solution available for verifying SoC designs—from RTL
to final LVS netlist (SPICE)—as well as FPGA designs. Encounter
Conformal EC enables designers to verify the widest variety of
circuits, including complex arithmetic logic, datapaths, memories,
and custom logic.
ENCOUNTER CONFORMAL
EQUIVALENCE CHECKER
ENCOUNTER CONFORMAL
EQUIVALENCE CHECKER
Already proven in thousands of tapeouts,
Encounter Conformal EC is the industry’s
most widely supported equivalence
checking product. In addition, it is
production-proven on more physical
design closure products, advanced
synthesis software, ASIC libraries, and IP
cores than any other formal verification
technology.
Encounter Conformal EC is available in L,
XL, and GXL offerings.
BENEFITS
• Exhaustively verifies multimillion-gate
ASICs and FPGAs—several times faster
than traditional gate-level simulation
• Decreases the risk of missing critical
bugs with independent verification
technology
• Enables faster, more accurate bug
detection and correction throughout
the entire design flow
ENCOUNTER
TI
MING
AREA POWER SI YIE
LD
STA
Test & Diagnostics
Power & SI Analysis
Constraint
Management
& Equivalence
Checking
Silicon Virtual Prototyping
Nanometer Routing
Manufacturing
RTL Synthesis
Global Physical Synthesis
G0001
Figure 1: Encounter digital IC design platform