Cadence ENCOUNTER CONFORMAL EQUIVALENCE CHECKER Datasheet - page 4
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Parallel Processing
For larger designs, overall verification time
can be reduced with multiple licenses by
running Encounter Conformal EC XL on
many machines simultaneously. LSF is also
supported.
ENCOUNTER CONFORMAL
EQUIVALENCE CHECKER GXL
In addition to all the features in Encounter
Conformal EC XL, Encounter Conformal
EC GXL offers transistor circuit analysis for
custom designs and embedded memories.
Designers can use Encounter Conformal
EC GXL with custom embedded memories,
arithmetic blocks, datapaths, standard and
extended libraries, and all other custom
and semi-custom digital circuit functions.
Circuit styles supported include standard
and complex Boolean functions, latches
and registers, pass-gate, transmission-gate,
tri-state switch logic, pre-charged logic
cells, domino logic blocks, and dual-rail.
Custom Logic Abstraction
Encounter Conformal EC GXL analyzes
digital transistor circuits and derives an
equivalent logical Verilog
®
model. The
underlying abstraction algorithms are more
powerful than pattern-based solutions.
A Verilog gate logic model of the
abstracted circuit can be used for:
• Equivalence checking
• Fault grading—Preserves the circuit
hierarchy and structure for maximum
debugging efficiency
• Emulation—Provides accurate emulation
models for actual transistor-level circuits
• Simulation acceleration—Using the
abstracted Verilog model allows
simulation to run many times faster than
with SPICE circuit
Memory Verification
Traditional and symbolic simulation tools
do not scale for verifying today’s memory
functions and their ever increasing
complexity. Encounter Conformal EC
GXL provides exhaustive logic verification
and— since no testbench is needed—the
quality of results is not limited by
availability of time or resources to develop
comprehensive tests. Encounter Conformal
EC GXL generates memory primitive
models for Verilog system simulation and
complete logic function verification of the
transistor circuit design using equivalence
checking.
• Intuitive graphical interface to generate
specific primitives
• Generated primitives are address, word,
and column MUX configurable
• All read-write, read-only, and write-only
combinations can be generated
• Generated simulation models have
the highest performance and contain
built-in assertions for trapping illegal
memory use such as address collision and
simultaneous read-write
PLATFORMS
• Linux (32-bit, 64-bit)
• Sun Solaris (32-bit, 64-bit)
• IBM AIX (32-bit, 64-bit)
LANGUAGE SUPPORT
• Verilog (1995, 2001)
• SystemVerilog
• VHDL (87, 93)
• SPICE (traditional, LVS)
• EDIF
• Liberty
• Mixed languages
For more information Email
us at
icinfo@cadence.com
or visit
www.cadence.com
.