Cadence POWER RAIL VERIFICATION Datasheet
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(timing, area, and power with wires),
accurate verification, signal-integrity—
aware routing, and the latest yield and
low-power design capabilities that are
critical for advanced 65nm designs. With
Encounter technology, you can boost
your productivity, manage complexity,
and get your products to market
faster. Encounter platform products are
available in L, XL, and GXL offerings.
VOLTAGESTORM POWER
AND POWER RAIL
VERIFICATION
Delivering the accuracy, capacity,
and performance to handle the most
complex multi-million gate designs,
the VoltageStorm hierarchical solution
gives design teams the confidence
that IR (voltage) drop and power rail
electromigration are managed effectively.
VOLTAGESTORM POWER AND
POWER RAIL VERIFICATION
VoltageStorm power verification has been
proven to validate IR drop and power
electromigration (EM) on thousands
of designs. Initially used as an IR drop
and power EM signoff solution prior to
tapeout, VoltageStorm technology has
evolved to become an integral component
of design creation, which requires early
and up-front power rail analysis to help
create robust power networks during
power planning. Employing parasitic
extraction that is manufacturing aware,
and using patented static and dynamic
algorithms, VoltageStorm technology
continues to deliver power estimation
and power rail analysis functionality and
automation that you can depend on to
both analyze and optimize your power
networks throughout the design flow.
ENCOUNTER PLATFORM
To release innovative products in
narrow market windows, companies
need to focus precious engineering
resources on where they add the most
value—differentiating their designs.
The Cadence
®
Encounter
®
digital IC
design platform offers a full spectrum of
technologies for nanometer-scale SoC
design, helping both logic design
www.
cadence.com/solutions/logic_design/
index.aspx
and physical implementation
www.cadence.com/solutions/digital_
implementation/index.aspx
teams
achieve high-quality silicon quickly.
As an integrated RTL-to-GDSII design
environment, the Encounter platform
provides a complete flow—from RTL
synthesis and test design through silicon
virtual prototyping and partitioning to
final timing and manufacturing closure.
It delivers the highest quality of silicon
The complexities associated with today’s power-sensitive
designs increases the risk that IR drop will be a cause of silicon
failure. Design teams require comprehensive power and power
rail analysis solutions that can accurately validate on-chip
power delivery networks, from initial power planning through
final signoff prior to tapeout. Within the Cadence
®
Encounter
®
digital IC design platform, VoltageStorm
®
power verification
helps you quickly validate and optimize your power networks
using both static and dynamic analysis approaches.