Cadence POWER RAIL VERIFICATION Datasheet - page 2
www.cadence.com
VOLTAGESTORM
BENEFITS
• Enables efficient creation of on-chip
power networks
− Power routing sizes
− De-coupling capacitance size and
location
• Minimizes risk of power-related silicon
failures
− Outputs comprehensive static and
dynamic IR drop reports
− Enables IR drop-aware timing and
SI noise analysis (requires Cadence
Encounter Timing System or CeltIC
®
NDC)
• Optimizes low-power designs
− Reports on-chip power density
− Allows tradeoff between de-coupling
capacitance and leakage
− Validates power-switch sizes
and power-up time
− Verifies impact of power-up rush
current on surrounding logic
• Delivers an efficient, hierarchical
analysis solution
− Uses power grid views to maximize
accuracy, performance, and capacity
− Accurately models IP, custom digital,
analog, and mixed-signal blocks
• Supported by major reference flows,
ASIC and IP vendors, and IDMs
− Recommended by TSMC 7.0
Reference Flow
− Recommended by Starc ZD 3.0 Flow
− Library power grid views available
directly from ARM and TSMC
FEATURES
VoltageStorm power and power rail
verification provides a comprehensive
solution for power analysis and contains
the functionality to accurately address
the requirements associated with multiple
design styles, including SoC, low-power,
ASIC, and custom digital designs.
Employing a combination of static
and dynamic analysis approaches,
VoltageStorm solutions can be used for
power rail verification during the complete
physical design creation flow, from early
power planning through signoff prior to
tapeout. To enable this comprehensive
support, the VoltageStorm solution
contains the functionality to calculate
static and dynamic power consumption
plus the functionality to perform both
static and dynamic power rail analysis.
POWER-DRIVEN DESIGN
REqUIREMENTS
For design teams to manage power
consumption effectively, they must under-
stand the source of the power, typically
either active power or leakage power.
For design teams to create robust power
networks, in addition to understanding
the details of power consumption, they
must understand how to optimize power
rail routing and sizes and the size and
location of power switches (low-power
designs) and de-coupling capacitors.
VoltageStorm technology contains all of
the functionality required to help you with
these power-driven design requirements.
POWERMETER POWER ESTIMATION
PowerMeter is the power estimation
functionality within the hierarchical,
cell-based VoltageStorm solution.
PowerMeter allows you to calculate static
power consumption and dynamic power
Figure 1: Example VoltageStorm plots (from left to right: IR drop, current density, and recommended
de-coupling capacitance)
Static Power
DSPF
SPEF
TWF
SLEW
SDC
TFC/
VCD
1
Dynamic Power
Instance-based
Static Current
cell
mA
cell
Instance-based
Dynamic Current
Waveform
DSPF
SPEF
TWF
SLEW
SDC
VCD
2
.lib
DEF
1. Optional VCD input used
to seed activity
2. VCD required for vector-based
analysis or to seed vectorless
analysis
PowerMeter
PowerMeter
Figure 2: PowerMeter data flow and usage