Cadence POWER RAIL VERIFICATION Datasheet - page 3
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VOLTAGESTORM
transients for all instances within a design.
Optional VCD vectors can be used to seed
the activity for static or vectorless dynamic
power calculation. VCD vectors can also
be used to directly drive PowerMeter for
vector-based dynamic power calculation.
PowerMeter uses a proprietary activity
propagation algorithm that enables
comprehensive nodal activity to
always be generated, driven by default
activity or seeded by partial activity
information supplied by the designer.
VOLTAGESTORM PE
VoltageStorm PE enables hierarchical
static power estimation using PowerMeter
and hierarchical static power rail analysis.
A static approach to power rail verification
helps you rapidly check that the power
rails can supply the amount of power
needed by the design, without creating
high amounts of IR drop. Static analysis
if often used for pre-tapeout signoff
for process technologies at and above
130nm, where the amount of natural
de-coupling capacitance diminishes
the need for dynamic analysis.
Static analysis is a necessary step prior to
executing dynamic analysis, to ensure that
the power rails are robust prior to fine-
tuning with de-coupling capacitance—
incorrectly sized power routing cannot be
fixed by adding de-coupling capacitance.
VOLTAGESTORM DG
With hierarchical vectorless and vector-
based dynamic analysis, VoltageStorm
DG extends the static analysis
capabilities of VoltageStorm PE.
At and below 90nm, high dynamic
currents caused by simultaneously
switching logic can cause high transients
of dynamic IR drop on both power
and ground rails. Using VoltageStorm
DG, design teams can determine the
dynamic power consumption created by
simultaneous switching and the dynamic
IR drop caused by these high currents.
Both VoltageStorm PE and DG provide
full support for low-power design
methodologies that employ multiple
voltage domains, multiple thresholds,
level-shifting logic, voltage clamp
circuitry, and the use of power switches
to minimize leakage. VoltageStorm DG
gives you additional insight on how fast
a block powers up after it was powered
down, and the IR drop impact of the
block powering up on surrounding logic.
TRANSISTOR-LEVEL ANALySIS
With the VoltageStorm hierarchical
analysis solution, you can use the
technology at the transistor-level to
perform power rail analysis for custom
digital blocks. Using GDSII input and the
Virtuoso
®
UltraSim simulation engine,
the VoltageStorm solution enables static-
and vector-based dynamic analysis.
AUTOMATED DE-COUPLING
CAPACITANCE OPTIMIZATION
Once you’ve completed dynamic
power rail analysis using VoltageStorm
DG, the solution can calculate and
recommend the amount of additional
de-coupling capacitance necessary to
limit the dynamic IR to user-specified
limits. This recommended additional
de-coupling capacitance can then
drive an automated optimization flow
within the SoC Encounter
™
system,
where filler cells are swapped with
de-coupling capacitance cells.
Boundary
Voltages
Block
Powergrid
Views
Transistor
Dynamic
Transistor
Dynamic
Cell-based
Dynamic
Cell-based
Static
VoltageStorm PE + DG
VoltageStorm PE + DG
VAVO
VoltageStorm DG
VoltageStorm PE
Full-chip
Analysis
Block-level
Analysis
GDS/
DEF
GDS
DEF
IP or
Memory
IP or
Memory
Analog
or AMS
Analog
or AMS
Power Grid
View Library
LibGen
Figure 3: Hierarchical power rail analysis
ECO
File to
SoC
Encounter
Optimize de-caps
User IR Drop limit = 75mV
1. IR drop before
optimization
2. Recommended
De-caps
3. IR drop after
optimization
Analysis result after
adding de-cap
Worst-case IR
63mV
Original analysis result
Worst-case IR
75mV (red)
Figure 4: Automated de-coupling capacitance optimization flow