E2v TSEV8308500 User Manual - Section 3
TSEV8308500 Evaluation Board User Guide
3-1
0968D–BDC–01/09
e2v semiconductors SAS 2009
Section 3
Operating Procedures and
Characteristics
3.1
Introduction
This section describes a typical single-ended configuration for analog inputs and clock
inputs.
The single-ended configuration is preferable, as it corresponds to the most straightfor-
ward and quickest TSEV8308500 board setting for evaluating the TS8308500 at full
speed in the military temperature range.
The inverted analog input V
INB
and clock input CLKB common mode level is Ground
(on-board 50
Ω terminated). In this configuration, no balun transformer is needed to con-
vert properly single-ended mixer output to balanced differential signals for the analog
inputs.
In the same way, no balun is necessary to feed the TS8308500 clock inputs with bal-
anced signals.
Connect directly the RF sources to the in-phase analog and clock inputs of the
converter.
However, dynamic performances can be somewhat improved by entering either analog
or clock inputs in differential mode.
3.2
Operating
Procedure
1.
Connect the power supplies and Ground accesses
(V
CC
= +5V, GND = 0V, V
PLUSD
= 0V, V
EAE
= V
EED
= -5V) through the dedicated
banana jacks.
The -5V power supplies should be turned on first.
Note: one single -5V power supply can be used for supplying the digital V
EED
and
analog V
EEA
power planes.
2.
The board is set by default for digital outputs in binary format.
3.
Connect the CLK clock signal.
The inverted phase clock input CLKB may be left open (as on-board 50
Ω termi-
nated). Use a low phase noise RF source. The clock input level is typically
4 dBm and should not exceed +10 dBm into the 50
Ω termination resistor (maxi-
mum ratings for clock input power level is 15 dBm). Clock frequency can range
between 10 MHz and 700 MHz.