1. DL manuals
  2. FPGANETWORKING
  3. Adapter
  4. SGA10GD
  5. Reference Manual

FPGANETWORKING SGA10GD Reference Manual - Contents

Manual is about: Dual 10Gbps PCI Expressx8

Summary of SGA10GD

  • Page 1

    Sga10gd dual 10gbps pci expressx8 ethernet adapter reference manual ver.: 2009.09.29., ver. 1.1 (c) budapest university of technology and economics department of telecommunications and media informatics 1.

  • Page 2: Contents

    Contents contents...........................................................................................................................................................................................2 1. Introduction..................................................................................

  • Page 3: 1. Introduction

    1. Introduction 1.1 what is sga10gd? Sga10gd is a pci-express x8 adapter card, primarily developed for 10gbits ethernet network monitoring. It's on-board resources, and reconfigurability of its fpga extends its functionality beyond the 10g application, 1.2 what is on-board? The figures below show th...

  • Page 4: 1.3 Conformity

    1.3 conformity sga10gd aims the following standards/recommendations: xfp 10 gigabit small form factor pluggable module sff committee inf-8077i 10 gigabit small form factor pluggable module ...Gbe gigabit ethernet (optical/copper) ieee std 802.3 carrier sense multiple access with collision detection ...

  • Page 5: 2. Architecture

    2. Architecture the simple and robust architecture of sga10gd is shown on the block diagram below. The heart of the board is a xilinx virtex-5 family fpga device. The pcb can accomodate two types of devices: xc5vlx110t-2ff1136c (for sga10gd board) xc5vlx50t-1ff1136c (for sga10gdl board) the main cha...

  • Page 6: 2.1 Power Supply

    In addition, both types have clock management tiles (cmts) having two digital clock managers (dcm) and a phase locked loop per cmt one pci express endpoint controller 4 tri-mode (10/100/1000)ethernet media access controller (mac) 2 internal configuration acces ports (icap) core logic can run at 550m...

  • Page 7: 2.2 Clock Sources

    The signal names, nominal voltages, maximum load current, and designated targets are the following: signal name v a targets notes vcc1 1.010fpga core voltage vcc1v8 1.810ddr2 ram main supply . . Ldo feed for ddr2 ref. . . Fpga i/o bank 11,13,15,17,(19,21) . . Flash internal voltage vcc2v5 2.510ldo f...

  • Page 8

    2.3 dual xfps for 10gbps ethernet the sga10gd board has two xfp module cages (p1,p2) that support user-installed xfp modules for gigabit ethernet (10gbps) interfaces. Dedicated 156.25 mhz reference clock source is available for fpga reference, and and other xo reference for xaui/xfi converter chips....

  • Page 9

    The table below lists the xaui/xfi converter vs. Fpga connectivity. Common signal function fpga# prtad[0] port base address 0aj11 prtad[1] port base address 1ap12 prtad[2] port base address 2ak11 prtad[3] port base address 3an12 prtad[4] port base address 4am11 u12 signals function fpga# u14 signals...

  • Page 10: 2.4 Pci Express X8 Endpoint

    2.4 pci express x8 endpoint the pci express endpoint connector (designated as j1 on-board) allows an fpga design to support x1, x4 and x8 gigabit lanes to communicate with the host, at the speed of 2.5 gbps of each. Caution! There are jumpers - designated as j2, j9 - on board to select the proper pr...

  • Page 11

    Gnd a38 - petn5 b38 ap3 perp5 a39 an3 * gnd b39 - pern5 a40 an4 gnd b40 - gnd a41 - petp6 b41 ap6 gnd a42 - petn6 b42 ap7 perp6 a43 an5 gnd b43 - pern6 a44 an6 gnd b44 - gnd a45 - petp7 b45 ap8 ** gnd a46 - petn7 b46 ap9 perp7 a47 an9 * gnd b47 - pern7 a48 an10 present8_n b48 to j9 gnd a49 - gnd b49...

  • Page 12: 2.5 Ddr2 Sodimm Ram

    2.5 ddr2 sodimm ram the sga10gd board contains a 200-pin, small-outline dual in-line memory module (sodimm) receptacle ( j3 ) that supports installation of ddr2 sdram sodimms of 128mb, 256mb, or 512 mb. Dual-rank sodimms may not be supported. Also, the speed grade of -1 of the default fpga installat...

  • Page 13

    Dq[25] 063 h33 dq[29] 064 g32 gnd 065 - gnd 066 - dm[3] 067 j34 dqs_n[3] 068 k34 nc/reset_n 069 - dqs[3] 070 l34 gnd 071 - gnd 072 - dq[26] 073 k32 dq[30] 074 j32 dq[27] 075 l33 dq[31] 076 k33 gnd 077 - gnd 078 - cke[0] 079 n32 cke[1] 080 m32 vcc1v8 081 - vcc1v8 082 - nc/csn[2] 083 - a[15] 084 r32 b...

  • Page 14: 2.6 Feature Connector

    Nc/test 163 - ck[1] 164 an34 gnd 165 - ck_n[1] 166 an33 dqs_n[6] 167 al33 gnd 168 - dqs[6] 169 al34 dm[6] 170 an32 gnd 171 - gnd 172 - dq[50] 173 ak33 dq[54] 174 ap32 dq[51] 175 aj32 dq[55] 176 am32 gnd 177 - gnd 178 - dq[56] 179 af31 dq[60] 180 ak31 dq[57] 181 ag30 dq[61] 182 ad30 gnd 183 - gnd 184...

  • Page 15

    For pdh applications, a passive child board (type d1558001-liu) has to be connected to j5. The pinout can be found in the table below. Signal (even)j5#fpga#.Signal (odd)j5#fpga# nc 01 h14 gnd 02 - ttxa[0] 03 j14 ttxb[0] 04 h20 rtxa[0] 05 k14 ttxb[0] 06 j20 ttxa[1] 07 l14 ttxa[1] 08 l20 rtxa[1] 09 g1...

  • Page 16: 2.7 Fpga Programming

    2.7 fpga programming three configuration methods are available on sga10gd to upload (program) the fpga core. 2.7.1 programming through jtag fpga core can be loaded directly through the jtag port (designated as j7 on-board) as shown in the figure below 2.7.2 programming from flash from the platform f...

  • Page 17: 2.8 Status Leds

    2.7.3 partial reconfiguration if the platform flash contains the proper core implementing a pci express endpoint, and a controller core for icap (internal configuration access port) - this resident core allows the partial reconfiguration of the fpga. Transient cores can be loaded that way. J6 jumper...

  • Page 18: 4. Fpga Test Cores

    4. Fpga test cores the on-board subsystems have been successfully tested using the xilinx's coregen generated cores. User constraints files were modified according to the boards metric. Further modifications are discussed below on a per-core bases. These test cores are available in the distribution ...

  • Page 19: 4.4 Clock Domains

    The test is passed if sga10gd shows green lit for all leds (p2 blinks slowly). 4.4 clock domains the following table summarizes the proposed clock domains to help devloping new/combined fpga cores. It can also be used for estimating the performace of core by using the data bits column for a given cl...