Intermec CK30 Service Manual - I/o Control

Chapter 4 — Theory of Operation 

POR Reset (Cold Boot) 

Power-On Reset circuit VR3 simultaneously asserts the PSC reset input 

and the PXA255 nRESET. This ensures that the processor is always in 

reset as its power is ramped up. 

Soft Reset (Warm Boot) 

Warm boot forces code execution to vector to boot code, where the kernel 

is restarted without reinitializing the object store. Warm boot is 

implemented as in the 700 and 241X products: Pressing and holding the 

I key for several seconds: 

•  The PSC first wakes the system if it is suspended. 

•  The PSC starts a timer on I key down. 

•  If the IO key is still down after approximately 5 seconds, the PSC asserts 

signal VDD_FAULT* to command a warm boot. 

• If the I key is released before the timer expires, the PSC treats it as a 

simple Suspend/Resume command and asserts PSC_IRQ to suspend or 

resume the system. 

The VDD_FAULT* assertion causes the processor to suspend. The PSC 

then awakes the system using PSC_IRQ. Code execution starts as it would 

on a normal resume but checks the PXA255 power management registers 

to determine if the exception was triggered by VDD_FAULT*. If it was, 

code execution vectors to the warm boot in the bootloader. 

Peripheral Resets 

Other functional blocks in the computer have their own resets. 

The FPGA generates its own internal reset as part of the download process. 

Because it is an SRAM-based device and is not even downloaded until well 

after the system reset is release, system reset is not brought out to the 

FPGA. After download, functional blocks within the FPGA are reset 

through their own memory-mapped control registers. 

The audio codec (Proto 0 only) uses the AC97 interface reset (AC_RST). 

The Bluetooth module supplies its own power-on reset. 

PCI slot reset is provided through the PCI bus reset–PCI-RESET–

generated by the FPGA-based PCI host bridge. 

I/O Control 

The I key is a simple contact closure to GND on the keypad PCB. The 

IO_KEY* signal is debounced in software by the PSC, which then issues a 

PSC_IRQ* interrupt to PXA255 GPIO[0] to suspend or resume the 

system PXA255. On a resume, the PSC does not issue the interrupt if 

BATT_FAULT_IRQ* is asserted (main battery too low to resume). 

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CK30 Handheld Computer Service Manual