Jands HP12 Technical Manual - 3.6
Equipment Description
3-8
Revision 2 - 26 April, 2000
HP SERIES DIMMER
TECHNICAL MANUAL
3.6
CPU card
(
Figure 3.2
The HP Series dimmers are fully digital. The CPU reads all inputs and generates all
outputs. The one exception to this is the fan control system which is intended to operate
without CPU intervention - if the CPU were to stop operating the cooling system will
continue to operate normally.
Many of the components on the CPU card are Surface Mount, and will require extreme
care if components are to be replaced at any stage.
The CPU is required to read the following inputs:
•
the temperature sensor
•
three phase voltages
•
all switches
•
the rotary encoder
•
the DMX input
•
mains zero crossing points
The CPU also drives the following outputs:
•
all LEDs
•
the DMX output
•
twelve dimmer channel opto-isolators
3.6.1
Microprocessor
The microprocessor (
µ
P) is a Motorola 68332 (IC1) housed in a 132 pin QFP surface
mount package. This is a highly integrated part consisting of a 68020 core surrounded by
serial ports, a system integration module, and a time processing unit which is used to
control the triacs via the opto-isolators. The system integration module is configured to
generate chip select lines which are used to select the peripherals. The
µ
P’s internal clock
is derived from an external 16 MHz crystal oscillator (OSC1).
The four DIP switches (SW1) are connected directly to the unused CPU interrupt pins.
During normal operation all DIP switches should be off.
3.6.2
Memory
The CPU memory consists of a 256Kx8 program EPROM (IC10) and two 128Kx8 static
RAMs (IC2, IC3). Program is copied from EPROM into RAM at boot and subsequently
executed from RAM to improve execution speed. As of September 1995, the current
software version is “V1.1F”.
The EPROM may in the future be substituted with a FLASH device to allow for in-field
software upgrades. Read and Write control signals are created by a 74HC00 (IC15);
during normal operation the write pulses are not generated as they are only used when
the software is being uploaded into a FLASH device. Diode D2 configures the CPU at
reset to have an 8 bit boot EPROM.