Jands HP12 Technical Manual - page 85
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Jands Electronics P/L
40 Kent Rd
Mascot NSW 2020
Australia
Ph (02) 9582-0909
0
26-Apr-2000
17:08:08
H:\Lab\HPCE\CIRCUIT\Hpcefpn2.sc1
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Size:
Number:
Date:
File:
Revision:
Sheet
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f
Time:
A3
Drawn By:
R75
100K
R74
100K
+5
+5
R23
100R
R16
100R
R15
100R
R8
100R
R25
1R
R4
100R
Q7
BCX17
SIG
CG12
CG11
CG10
CG9
CG8
CG7
CG6
CG5
CG4
CG3
CG2
CG1
CR12
CR11
CR10
CR9
CR8
CR7
CR6
CR5
CR4
CR3
CR2
CR1
NORM
CLR
RUN
BLD
TEST
MODE
CHAN
BANK
C4
F4
G4
H4
J4
P4
A4
B4
DP4
M4
L4
K4
D4
E4
N4
C3
F3
G3
H3
J3
P3
A3
B3
DP3
M3
L3
K3
D3
E3
N3
N2
E2
D2
K2
L2
M2
DP2
B2
A2
P2
J2
H2
G2
F2
C2
C1
F1
G1
H1
J1
P1
A1
B1
DP1
M1
L1
K1
D1
E1
N1
C1,2,3,4,6
100nF
C11
10uF
P0
4
P1
12
P2
13
P3
3
PE
1
CIN
5
U/D
10
CLK
15
RST
9
Q0
6
Q1
11
Q2
14
Q3
2
COUT
7
IC9
4516
12
13
IC8F
40106
+5
1
2
IC8A
40106
+5
+5
S1-S8
S21
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
B0
18
B1
17
B2
16
B3
15
B4
14
B5
13
B6
12
B7
11
E
19
DIR
1
IC4
74HC245
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
B0
18
B1
17
B2
16
B3
15
B4
14
B5
13
B6
12
B7
11
E
19
DIR
1
IC5
74HC245
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
B0
18
B1
17
B2
16
B3
15
B4
14
B5
13
B6
12
B7
11
E
19
DIR
1
IC6
74HC245
OC
1
C
11
1D
2
2D
3
3D
4
4D
5
5D
6
6D
7
7D
8
8D
9
1Q
19
2Q
18
3Q
17
4Q
16
5Q
15
6Q
14
7Q
13
8Q
12
IC1
74HC574
OC
1
C
11
1D
2
2D
3
3D
4
4D
5
5D
6
6D
7
7D
8
8D
9
1Q
19
2Q
18
3Q
17
4Q
16
5Q
15
6Q
14
7Q
13
8Q
12
IC3
74HC574
OC
1
C
11
1D
2
2D
3
3D
4
4D
5
5D
6
6D
7
7D
8
8D
9
1Q
19
2Q
18
3Q
17
4Q
16
5Q
15
6Q
14
7Q
13
8Q
12
IC2
74HC574
S13-S20
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
B0
18
B1
17
B2
16
B3
15
B4
14
B5
13
B6
12
B7
11
E
19
DIR
1
IC7
74HC245
3
4
IC8B
40106
R24
100K
C5
10uF
LED22
LED23
LED24
DRV1
DRV2
DRV12
OUT1
OUT2
OUT12
R26
470R
R27
470R
R28
470R
R29
470R
R48
470R
R49
470R
(100K)
For HP6, place R76
(100K)
For HP12, place R77
NOTE:
R77
R76
to gnd.
pull-down
are 100k
R50-R73
NOTE:
R73
R72
R71
R70
R69
R68
R67
R66
R57
R56
R55
R54
R53
R52
R51
R50
100K
100K
8 x
8 x
R58
R59
R60
R61
R64
R63
R62
R65
8 x
100K
HP12SC HP12TR HP6SC
R22
R21
R20
R19
R18
R17
R14
R13
R12
R11
R10
R9
x
x
x
ENTER
NORMAL
CLEAR
RUN
BUILD
TEST
MODE
CHAN
BANK
DRIVE
LED-MATRIX
100R
Q1
Q2
Q3
Q4
Q5
Q6
dp
p
n
m
l
k
j
h
g
f
e
d
c
b
a
8,9,10
PHASEC
PHASEB
PHASEA
ENCB
ENCA
FC2
FC1
FC0
A19
1
HP FRONTPANEL
Channel
Channel
ch12
ch11
ch10
ch9
ch8
ch7
ch6
ch5
ch4
ch3
ch2
ch1
Keypad
Green
Red
Digit 4
Digit 3
Digit 2
Digit 1
G.HAINES
HPCEFPN2.SC1
2
1
SEGMENT
DISPLAY
LAYOUT
ENCB
ENCA
HC
LC
HC
LC
FC2
FC1
A19
FC0
A3
A5
A7
A1
A4
A6
A0
A2
BG
BG
PHA
PHB
PHC
1
FROM
CONN1
CPU CARD
OUTPUT (LOAD) LEDs
OUT3 - OUT11
R31 - R47
DRIVE LEDs
DRV3 - DRV11
R30 - R46
PWRCARD
FLATCABLE from
POWER CARD
SEE DIAGRAM HPCEPWRx
5
6
IC8C
40106
8
9
IC8D
40106
10
11
IC8E
40106
R3
R2
R1
R6
R5
R7